INTEGRATED CIRCUITS 74F564 Octal D flip-flop (3-State) Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 FEATURES PIN CONFIGURATION • 74F564 is broadside pinout version of 74F534 • Inputs and Outputs on opposite side of package allow easy interface to Microprocessors • Useful as an Input or Ouput port for Microprocessors • 3-State Ouputs for Bus interfacing • Common Output Enable • 74F574 is a non-inverting version of 74F564 DESCRIPTION OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 11 CP GND 10 The 74F564 has a broadside pinout configuration to facilitate PC board layout and allows easy interface with microprocessors. SF01052 It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F564 180MHz 50mA ORDERING INFORMATION The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the register operation. When OE is Low, data in the register appears at the outputs. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG # 20-Pin Plastic DIP N74F564N SOT146-1 20-Pin Plastic SOL N74F564D SOT163-1 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW DESCRIPTION INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA 150/40 3.0mA/24mA Q0 - Q7 3-State outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL 2 LOGIC SYMBOL (IEEE/IEC) 3 4 5 6 7 8 1 9 EN1 11 C2 D0 11 1 19 1996 Jan 05 D2 D3 D4 D5 D6 D7 2 OE Q0 VCC=Pin 20 GND=Pin 10 D1 CP Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 2D 1 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 SF01054 SF01053 2 853-0166 16189 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 LOGIC DIAGRAM D0 D1 2 D2 3 D CP CP OE D3 4 D Q CP D4 5 D Q CP D Q D5 6 CP D Q D6 7 CP D Q D7 8 CP 9 D Q D CP Q CP Q 11 1 19 VCC=Pin 20 GND=Pin 10 18 17 Q1 Q0 16 Q2 15 Q3 14 Q4 13 Q5 Q6 12 Q7 SF01055 FUNCTION TABLE CP Dn INTERNAL REGISTER OUTPUTS OE INPUTS L L ↑ ↑ l h L H H L L ↑ X NC NC H H ↑ ↑ X Dn NC Dn Z Z H = h = L = l = NC= X = Z = ↑ = ↑ = OPERATING MODES Q0 – Q7 Load and read register Hold Disable outputs High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don’t care High impedance “off” state Low-to-High clock transition Not a Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature 1996 Jan 05 3 –30 to +5.0 mA –0.5 to +VCC V 48 mA 0 to +70 °C –65 to +150 °C Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –3 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 70 °C MAX UNIT V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL TEST CONDITIONSNO TAG PARAMETER MIN TYP NO TAG VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX ±10%VCC 2.4 ±5%VCC 2.7 V VOH O High level output voltage High-level VOL O Low level output voltage Low-level VIK Input clamp voltage II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOZH Off-state output current, High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output currentNO TAG –150 mA 45 65 mA ICC Supply current (total) 50 75 mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX ±10%VCC ±5%VCC VCC = MIN, II = IIK VCC = MAX ICCH ICCL VCC = MAX 3.4 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V 100 µA –60 ICCZ 55 80 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 4 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL TEST CONDITIONS PARAMETER Tamb= +25°C VCC = +5V CL = 50pF, RL = 500Ω MIN TYP MAX Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fMAX Maximum Clock frequency Waveform NO TAG 160 180 tPLH tPHL Propagation delay CP to Qn Waveform NO TAG 3.5 3.5 5.0 5.0 8.0 8.0 3.0 3.0 8.5 8.5 ns tPZH tPZL Output Enable time to High or Low level Waveform 4 Waveform 5 2.5 4.0 4.5 5.5 7.5 8.0 2.0 3.5 8.0 8.5 ns tPHZ tPLZ Output Disable time from High or Low level Waveform 4 Waveform 5 1.0 1.0 3.0 2.5 6.0 5.5 1.0 1.0 7.0 6.0 ns 150 MHz AC SETUP REQUIREMENTS LIMITS SYMBOL Tamb= +25°C VCC = +5V CL = 50pF, RL = 500Ω TEST CONDITIONS PARAMETER MIN ts(H) ts(L) Setup time, Dn to CP th(H) th(L) Hold time, Dn to CP tw(H) tw(L) CP pulse width, High or Low TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 3 2.0 2.0 2.0 2.5 ns Waveform 3 1.0 1.0 1.5 1.5 ns Waveform NO TAG 3.5 3.5 3.5 3.5 ns AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX Dn CP VM VM tW(H) tPHL Qn tPLH VM tPLH VM VM VM SF01051 SF00990 Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency 1996 Jan 05 VM tW(L) tPHL Qn VM VM Waveform 2. Propagation Delay for Data to Outputs 5 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. VM Dn VM VM ts(H) OE ts(L) th(H) CP VM VM th(L) VM VM tPZH Qn VM VOH -0.3V tPHZ VM 0V SF00993 SF00994 Waveform 3. Data Setup and Hold Times OE VM Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM tPZL tPLZ Qn VM VOL +0.3V SF00995 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1996 Jan 05 6 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 DIP20: plastic dual in-line package; 20 leads (300 mil) 1996 Jan 05 7 SOT146-1 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 SO20: plastic small outline package; 20 leads; body width 7.5 mm 1996 Jan 05 8 SOT163-1 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 NOTES 1996 Jan 05 9 Philips Semiconductors Product specification Octal D flip-flop (3-State) 74F564 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05138