CBTL02042A; CBTL02042B 3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen2 Rev. 1 — 10 March 2011 Product data sheet 1. General description CBTL02042A/B is a 2 differential channel, 2-to-1 multiplexer/demultiplexer switch for PCI Express Generation 2 (Gen2), and other high-speed serial interface applications. The CBTL02042A/B can switch two differential signals to one of two locations. Using a unique design technique, NXP has minimized the impedance of the switch such that the attenuation observed through the switch is negligible, and also minimized the channel-to-channel skew as well as channel-to-channel crosstalk, as required by the high-speed serial interface. CBTL02042A/B allows expansion of existing high speed ports for extremely low power. The device's pinouts are optimized to match different application layouts. CBTL02042A has input and output pins on the opposite of the package, and is suitable for edge connector(s) with different signal sources on the motherboard. CBTL02042B has outputs on both sides of the package, and the device can be placed between two connectors to multiplex differential signals from a controller. Please refer to Section 8 for layout examples. 2. Features and benefits 2 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer High-speed signal switching for PCIe Gen2 5 Gbit/s High bandwidth: 7 GHz at −3 dB Low insertion loss: −0.5 dB at 100 MHz −1.2 dB at 2.5 GHz Low intra-pair skew: 5 ps typical Low inter-pair skew: 35 ps maximum Low crosstalk: −30 dB at 2.5 GHz Low off-state isolation: −25 dB at 2.5 GHz Low return loss: −20 dB at 2.5 GHz VDD operating range: 3.3 V ± 10 % Shutdown pin (XSD) for power-saving mode Standby current less than 1 μA ESD tolerance: 8 kV HBM 1 kV CDM DHVQFN20 package CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 3. Applications Routing of high-speed differential signals with low signal attenuation PCIe Gen2 DisplayPort 1.2 USB 3.0 SATA 6 Gbit/s 4. Ordering information Table 1. Ordering information Type number Package Name Description Version CBTL02042ABQ DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm[1] SOT764-1 CBTL02042BBQ DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm[1] SOT764-1 [1] Total height after printed-circuit board mounting = 1.0 mm maximum. 5. Functional diagram A0_P B0_P A0_N B0_N A1_P B1_P A1_N B1_N C0_P C0_N C1_P C1_N SEL XSD Fig 1. CBTL02042A_CBTL02042B Product data sheet 002aaf073 Functional diagram of CBTL02042A; CBTL02042B All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 6. Pinning information 6.1 Pinning 20 VDD XSD 2 19 B0_P A0_P 2 19 XSD A0_P 3 18 B0_N A0_N 3 18 B0_P A0_N 4 17 B1_P C0_P 4 17 B0_N GND 5 16 B1_N C0_N 5 16 VDD VDD 6 15 C0_P A1_P 6 15 GND 7 14 B1_P C1_P 8 13 B1_N SEL 9 12 C1_N C1_N 9 12 SEL 002aaf761 VDD 11 A1_N 13 C1_P GND 10 14 C0_N 8 GND 11 7 VDD 10 A1_P A1_N Transparent top view 002aaf762 Transparent top view a. CBTL02042A Fig 2. GND terminal 1 index area 1 1 terminal 1 index area CBTL02042B 20 GND VDD CBTL02042A b. CBTL02042B Pin configuration for DHVQFN20 6.2 Pin description CBTL02042A_CBTL02042B Product data sheet Table 2. Pin description Symbol Pin Type Description channel 0, port A differential signal input/output CBTL02042A CBTL02042B A0_P 3 2 I/O A0_N 4 3 I/O A1_P 7 6 I/O A1_N 8 7 I/O B0_P 19 18 I/O B0_N 18 17 I/O B1_P 17 14 I/O B1_N 16 13 I/O C0_P 15 4 I/O C0_N 14 5 I/O C1_P 13 8 I/O C1_N 12 9 I/O SEL 9 12 CMOS single-ended input All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 channel 1, port A differential signal input/output channel 0, port B differential signal input/output channel 1, port B differential signal input/output channel 0, port C differential signal input/output channel 1, port C differential signal input/output operation mode select SEL = LOW: A ↔ B SEL = HIGH: A ↔ C © NXP B.V. 2011. All rights reserved. 3 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 Table 2. Pin description …continued Symbol Pin Type Description 19 CMOS single-ended input Shutdown pin; should be driven LOW or connected to VSS for normal operation. When HIGH, all paths are switched off (non-conducting high-impedance state), and supply current consumption is minimized. 1, 6, 10 11, 16, 20 power positive supply voltage, 3.3 V (± 10 %) 5, 11, 20, center pad 1, 10, 15, center pad power supply ground CBTL02042A CBTL02042B XSD 2 VDD GND[1] [1] DHVQFN20 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 7. Functional description Refer to Figure 1 “Functional diagram of CBTL02042A; CBTL02042B”. 7.1 Function selection and shutdown function The CBTL02042A/B provides a shutdown function to minimize power consumption when the application is not active, but power to the CBTL02042A/B is provided. The XSD pin (active HIGH) places all channels in high-impedance state (non-conducting) while reducing current consumption to near-zero. When XSD pin is LOW, the device operates normally. Table 3. Function selection X = Don’t care. CBTL02042A_CBTL02042B Product data sheet XSD SEL Function HIGH X An, Bn and Cn pins are high-Z LOW LOW An to Bn and vice versa LOW HIGH An to Cn and vice versa All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 8. Application design-in information CBTL02042A eSATA CONTROLLER MINI CARD/ mSATA CONNECTOR PCIe CONTROLLER CBTL02042A eSATA CONTROLLER eSATA/USB 3.0 COMBO CONNECTOR USB 3.0 CONTROLLER 002aaf776 Fig 3. Applications using CBTL02042A USB 3.0 CONTROLLER CBTL02042B USB 3.0 CONNECTOR USB 3.0 CONNECTOR 002aaf777 Fig 4. CBTL02042A_CBTL02042B Product data sheet Application using CBTL02042B All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 5 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 9. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage Tcase case temperature VESD electrostatic discharge voltage Min Max Unit −0.3 +4.6 V −40 +85 °C HBM [1] - 8000 V CDM [2] - 1000 V [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. [2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 10. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage VI input voltage Tamb ambient temperature Conditions operating in free air Min Typ Max Unit 3.0 3.3 3.6 V - - VDD V −40 - +85 °C 11. Static characteristics Table 6. Static characteristics VDD = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IDD supply current VDD = max.; VI = GND or VDD; XSD = LOW - 1.35 2.5 mA Istb standby current VDD = max.; VI = GND or VDD; XSD = HIGH - - 1 μA IIH HIGH-level input current VDD = max.; VI = VDD - - ±5[2] μA IIL LOW-level input current VDD = max.; VI = GND - - ±5[2] μA VIH HIGH-level input voltage SEL, XSD pins 0.65VDD - - V VIL LOW-level input voltage SEL, XSD pins - - 0.35VDD V VI input voltage differential pins - - 2.4 V SEL, XSD pins - - VDD V 0 - 2.0 V - - 1.6 V VIC common-mode input voltage VID differential input voltage peak-to-peak [1] Typical values are at VDD = 3.3 V, Tamb = 25 °C, and maximum loading. [2] Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW. CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 6 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 12. Dynamic characteristics Table 7. Dynamic characteristics VDD = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Min Typ[1] Max Unit f = 100 MHz - −50 - dB f = 2.5 GHz - −25 - dB f = 100 MHz - −0.5 - dB f = 2.5 GHz - −1.2 - dB f = 100 MHz - −50 - dB f = 2.5 GHz - −30 - dB Symbol Parameter Conditions DDIL differential insertion loss channel is OFF channel is ON DDNEXT differential near-end crosstalk B−3dB −3 dB bandwidth DDRL differential return loss adjacent channels are ON - 7.0 - GHz f = 100 MHz - −25 - dB f = 2.5 GHz - −20 - dB Ron ON-state resistance VDD = 3.3 V; VI = 2 V; II = 19 mA - 6 - Ω tPD propagation delay from Port A to Port B, or Port A to Port C, or vice versa - 80 - ps supply voltage valid or XSD going LOW to channel specified operating characteristics - - 10 ms Switching characteristics tstartup start-up time tPZH OFF-state to HIGH propagation delay - - 300 ns tPZL OFF-state to LOW propagation delay - - 70 ns tPHZ HIGH to OFF-state propagation delay - - 50 ns tPLZ LOW to OFF-state propagation delay - - 50 ns tsk(dif) differential skew time intra-pair - 5 - ps tsk skew time inter-pair - - 35 ps [1] Typical values are at VDD = 3.3 V; Tamb = 25 °C, and maximum loading. CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 VDD SEL 0.5VDD 0.5VDD 0V tPZL tPLZ 0.85VOH output 1 0.25VOH tPZH output 2 VOH VOL tPHZ VOH 0.85VOH 0.25VOH VOL 002aag013 Output 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Output 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. The outputs are measured one at a time with one transition per measurement. Fig 5. CBTL02042A_CBTL02042B Product data sheet Voltage waveforms for enable and disable times All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 8 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 13. Test information VDD VIC PULSE GENERATOR RL 200 Ω VO 2 × VIC open GND DUT CL 50 pF RT RL 200 Ω 002aag014 CL = load capacitance; includes jig and probe capacitance. RT = termination resistance; should be equal to Zo of the pulse generator. All input pulses are supplied by generators having the following characteristics: PRR ≤ 5 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns. Fig 6. Test circuitry for switching times 4-PORT, 20 GHz NETWORK ANALYZER PORT 2 PORT 3 PORT 1 PORT 4 DUT 002aae655 Fig 7. Test circuit Table 8. Test data Test CBTL02042A_CBTL02042B Product data sheet Load Switch CL RL tPLZ, tPZL (output on B side) 50 pF 200 Ω 2 × VIC tPHZ, tPZH (output on B side) 50 pF 200 Ω GND tPD - 200 Ω open All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 14. Package outline DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Package outline SOT764-1 (DHVQFN20) CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 10. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 9. CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 9. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged-Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model I/O Input/Output PCI Peripheral Component Interconnect PCIe PCI express PRR Pulse Repetition Rate SATA Serial Advanced Technology Attachment USB Universal Serial Bus 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTL02042A_CBTL02042B v.1 20110310 Product data sheet - - CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 CBTL02042A; CBTL02042B NXP Semiconductors 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 NXP Semiconductors CBTL02042A; CBTL02042B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] CBTL02042A_CBTL02042B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 March 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 NXP Semiconductors CBTL02042A; CBTL02042B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function selection and shutdown function . . . . 4 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering of SMD packages . . . . . . . . . . . . . . 11 Introduction to soldering . . . . . . . . . . . . . . . . . 11 Wave and reflow soldering . . . . . . . . . . . . . . . 11 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 11 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 March 2011 Document identifier: CBTL02042A_CBTL02042B