INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4104B MSI Quadruple low to high voltage translator with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple low to high voltage translator with 3-state outputs HEF4104B MSI The device uses a common negative supply (VSS) and separate positive supplies for inputs (VDDI) and outputs (VDD0). VDDI must always be less than or equal to VDDO, even during power turn-on and turn-off. For the permissible operating range of VDDI and VDDO see graph Fig.4. DESCRIPTION The HEF4104B quadruple low voltage to high voltage translator with 3-state outputs provides the capability of interfacing low voltage circuits to high voltage circuits, such as low voltage LOCMOS and TTL to high voltage LOCMOS. It has four data inputs (I0 to I3), an active HIGH output enable input (EO), four data outputs (O0 to O3) and their complements (O0 to O3). Each input protection circuit is terminated between VDDO and VSS. This allows the input signals to be driven from any potential between VDDO and VSS, without regard to current limiting. When driving from potentials greater than VDDO or less than VSS, the current at each input must be limited to 10 mA. With EO HIGH, O0 to O3 and O0 to O3 are in the low impedance ON-state, either HIGH or LOW as determined by I0 to I3; with EO LOW, O0 to O3 and O0 to O3 are in the high impedance OFF-state. Fig.2 Pinning diagram. HEF4104BP(N): 16-lead DIL; plastic (SOT38-1) HEF4104BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4104BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING I0 to I3 data inputs EO output enable input O0 to O3 data outputs O0 to O3 complementary data outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications Fig.1 Functional diagram. January 1995 2 Philips Semiconductors Product specification Quadruple low to high voltage translator with 3-state outputs Fig.3 Logic diagram. January 1995 3 HEF4104B MSI Philips Semiconductors Product specification Quadruple low to high voltage translator with 3-state outputs HEF4104B MSI AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays In → On, On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 170 340 ns 143 ns + (0,55 ns/pF) CL 80 160 ns 69 ns + (0,23 ns/pF) CL 15 65 135 ns 57 ns + (0,16 ns/pF) CL 5 170 340 ns 143 ns + (0,55 ns/pF) CL 5 10 tPHL 80 160 ns 69 ns + (0,23 ns/pF) CL 15 70 140 ns 62 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 10 tPLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 70 135 ns 10 tTLH 3-state propagation delays Output disable times EO → On, On HIGH LOW 10 tPHZ 55 110 ns 15 60 120 ns 5 70 135 ns 55 105 ns 15 55 110 ns 5 195 395 ns 10 tPLZ Output enable times EO → On, On HIGH LOW 95 195 ns 15 80 165 ns 5 195 395 ns 95 190 ns 80 160 ns 10 tPZH 10 tPZL 15 Dynamic power VDD V TYPICAL FORMULA FOR P (µW) 5 3 000 fi + ∑ (foCL) × VDD2 dissipation per 10 12 200 fi + ∑ (foCL) × package (P) 15 31 000 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification Quadruple low to high voltage translator with 3-state outputs HEF4104B MSI Fig.4 VDDO as a function of VDDI; the shaded area shows the permissible operating range. January 1995 5