INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4014B MSI 8-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4014B MSI 8-bit static shift register Operation is synchronous and the device is edge-triggered on the LOW to HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop. When PE is HIGH, data is loaded into the register from P0 to P7 on the LOW to HIGH transition of CP. When PE is LOW, data is shifted to the first position from DS, and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0 to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (O5 to O7). Fig.1 Functional diagram. HEF4014BP(N): 16-lead DIL; plastic (SOT38-1) HEF4014BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4014BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI Fig.2 Pinning diagram. January 1995 See Family Specifications 2 Philips Semiconductors Product specification HEF4014B MSI Fig.3 Logic diagram. 8-bit static shift register January 1995 3 Philips Semiconductors Product specification HEF4014B MSI 8-bit static shift register PINNING PE parallel enable input P0 to P7 parallel data inputs DS serial data input CP clock input (LOW to HIGH edge-triggered) O5 to O7 buffered parallel outputs from the last three stages FUNCTION TABLES Serial operation Parallel operation INPUTS n CP OUTPUTS INPUTS OUTPUTS DS PE O5 O6 O7 n 1 D1 L X X X 1 2 D2 L X X X 3 D3 L X X X Notes 6 X L D1 X X 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial 7 X L D2 D1 X 8 X L D3 D2 D1 X X CP DS PE O5 O6 O7 X H P5 P6 P7 X X = positive-going transition = negative-going transition Dn = either HIGH or LOW n = number of clock pulse transitions no change AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) TYPICAL FORMULA FOR P (µW) 5 900 fi + ∑ (foCL) × VDD2 10 4 300 fi + ∑ (foCL) × VDD2 15 12 000 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 no change 4 Philips Semiconductors Product specification HEF4014B MSI 8-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 130 260 ns 103 ns + (0,55 ns/pF) CL 55 110 ns 44 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 115 230 ns 88 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL Propagation delays CP → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 Set-up times 5 PE → CP 10 DS → CP Pn → CP Hold times PE → CP DS → CP Pn → CP Minimum clock pulse width; LOW Maximum clock pulse frequency 120 ns 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 40 10 ns 25 5 ns 15 15 0 ns 5 35 −5 ns tsu 25 −5 ns 15 25 0 ns 5 35 −5 ns 10 tsu 25 −5 ns 15 25 0 ns 5 25 −5 ns 10 10 tsu thold 20 0 ns 15 15 0 ns 5 30 15 ns 10 20 10 ns 15 15 7 ns 5 30 15 ns 10 thold 20 10 ns 15 15 7 ns 5 70 35 ns 30 15 ns 15 24 12 ns 5 6 13 MHz 15 30 MHz 20 40 MHz 10 10 15 January 1995 60 30 thold tWCPL fmax 5 10 ns + (1,0 ns/pF) CL see also waveforms Fig.4 Philips Semiconductors 8-bit static shift register January 1995 6 Fig.4 Waveforms showing minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and P to CP. Set-up and hold times are shown as positive values but may be specified as negative values. • Parallel-to-serial converter • Serial data queueing • General purpose register HEF4014B MSI Some examples of applications for the HEF4014B are: Product specification APPLICATION INFORMATION