PHILIPS AU5780D

INTEGRATED CIRCUITS
AU5780
SAE/J1850/VPW transceiver
Product specification
Supersedes data of 1997 Dec 22
1998 Jun 30
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
FEATURES
DESCRIPTION
• Supports SAE/J1850 VPW standard for in-vehicle class B
The AU5780 is a line transceiver being primarily intended for
in-vehicle multiplex applications. It provides interfacing between a
link controller and the physical bus wire. The device supports the
SAE/J1850 VPWM standard with a nominal bus speed of 10.4 kbps.
multiplexing
• Bus speed 10.4 kbps nominal
• Drive capability 32 bus nodes
• Low RFI due to output waveshaping with adjustable slew rate
• Direct battery operation with protection against +50V load dump,
PIN CONFIGURATION
jump start and reverse battery
• Bus terminals proof against automotive transients up to
–200V/+200V
• Thermal overload protection
• Very low bus idle power consumption
• Diagnostic loop-back mode
• 4X mode (41.6 kbps) reception capability
• ESD protected to 9 KV on bus and battery pins
• 8-pin SOIC
BATT
1
8
GND
TX
2
7
BUS_OUT
R/F
3
6
/LB
RX
4
5
BUS_IN
AU5780
SO8
SL01196
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
6
12
24
V
VBATT.op
Operating supply voltage
TA
Operating ambient temperature
+125
°C
VBATT.ld
Battery voltage
load dump; 1s
+50
V
IBATT.lp
Bus idle supply current
VBATT=12V
200
µA
VB
Bus voltage
0 < VBATT < 24V
–20
+20
V
VBOH
Bus output voltage
300Ω < RL < 1.6kΩ
7.3
8.0
V
–IBO.LIM
Bus output source current
0V < VBO < +8.5V
47
mA
VBI
Bus input threshold
tP
Propagation delay
Tx to Rx
VSR
Bus output slew rate
Rs = 56 kΩ
–40
3.65
4.1
V
16
24
µs
0.3
V/µs
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
DWG #
SO8: 8-pin plastic small outline package; Packed in tubes
DESCRIPTION
–40 to +125°C
AU5780D
SOT96-1
SO8: 8-pin plastic small outline package; Packed on tape & reel
–40 to +125°C
AU5780D–T
SOT96-1
1998 Jun 30
2
853–2087 19650
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
BLOCK DIAGRAM
BATTERY (+12V)
BATT
1
LOW–POWER
VOLTAGE
TIMER
REFERENCE
TEMP.
PROTECTION
BUS_OUT
TX
2
OUTPUT
BUFFER
TX–
BUFFER
7
Rb
Rs
R/F
3
/LB
6
INPUT
BUFFER
Rf
Vcc
Rd
4
INPUT
5
BUS_IN
FILTER
RX
VOLTAGE
REFERENCE
AU5780
8
GND
SL01195
1998 Jun 30
3
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
PIN DESCRIPTION
SYMBOL
PIN
DESCRIPTION
BATT
1
Battery supply input (12V nom.)
TX
2
Transmit data input; low: transmitter passive; high: transmitter active
R/F
3
Rise/fall slew rate set input
RX
4
Receive data output; low: active bus condition detected; float/high: passive bus condition detected
BUS_IN
5
Bus line receive input
/LB
6
Loop-back test mode control input; low: loop-back mode; high: normal communication mode
BUS_OUT
7
Bus line transmit output
GND
8
Ground
again upon detection of activity, i.e., rising edge at the TX input. The
device is able to receive and transmit a valid J1850 message when
initially in low-power mode.
FUNCTIONAL DESCRIPTION
The AU5780 is an integrated line transceiver IC that interfaces an
SAE/J1850 protocol controller IC to the vehicle’s multiplexed bus
line. It is primarily intended for automotive “Class B” multiplexing
applications in passenger cars using VPW (Variable Pulse Width)
modulated signals with a nominal bit rate of 10.4 kbps. The AU5780
also receives messages in the so-called 4X mode where data is
transmitted with a typical bit rate of 41.6 kbps. The device provides
transmit and receive capability as well as protection to a J1850
electronic module.
The AU5780 features special robustness at its BATT and BUS_OUT
pins hence the device is well suited for applications in the
automotive environment. Specifically, the BATT input is protected
against 50V load dump, jump start and reverse battery condition.
The BUS_OUT output is protected against wiring fault conditions,
e.g., short circuit to battery voltage as well as typical automotive
transients (i.e., –200V / +200V). In addition, an overtemperature
shutdown function with hysteresis is incorporated which protects the
device under system fault conditions. The chip temperature is
sensed at the bus drive transistor in the output buffer. In case of the
chip temperature reaching the trip point, the AU5780 will latch-off
the transceiver function. The device is reset on the first rising edge
on the TX input after a small decrease of the chip temperature.
A J1850 link controller feeds the transmit data stream to the
transceiver’s TX input. The AU5780 transceiver waveshapes the TX
data input signal with controlled rise & fall slew rates and rounded
shape. The bus output signal is transmitted with both voltage and
current control. The BUS_IN input is connected to the physical bus
line via an external resistor. The external resistor and an internal
capacitance provides filtering against RF bus noise. The incoming
signal is output at the RX pin being connected to the J1850 link
controller.
The AU5780 also provides a loop-back mode for diagnostic
purpose. If the /LB pin is open circuit or pulled low, then TX signal is
internally looped back to the RX output independent of the signals
on the bus. In this mode the electronic module is disconnected from
the bus, i.e., the TX signal is not output to the physical bus line. In
this mode, it can be used, e.g., for self-test purpose.
If the TX input is idle for a certain time, then the AU5780 enters a
low-power mode. This mode is dedicated to help meet ignition-off
current draw requirements. The BUS_IN input comparator is kept
alive in the low-power mode. Normal power mode will be entered
1998 Jun 30
4
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
CONTROL INPUT SUMMARY
BUS_OUT
RX
(out)
TX passive (default state)
float
float (high)
Loop-back
TX active
float
low
1
Communication
Transmitter passive
float
bus state1
1
Communication
Transmitter active
high
low
TX
/LB
MODE
0
0
Loop-back
1
0
0
1
BIT VALUE
NOTE:
1. RX outputs the bus state. If the bus level is below the receiver threshold (i.e., all transmitters passive), then RX will be floating (i.e., high,
considering external pull-up resistance). Otherwise, if the bus level is above the receiver threshold (i.e., at least one transmitter is active),
then RX will be low.
ABSOLUTE MAXIMUM RATINGS
According to the IEC 134 Absolute Maximum System; operation is not guaranteed under these conditions; all voltages are referenced to pin 8
(GND); positive currents flow into the IC; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VBATT
supply voltage
VBATT.ld
short-term supply voltage
load dump; t < 1s
VBATT.tr1
transient supply voltage
SAE J1113 pulse 1
VBATT.tr2
transient supply voltage
SAE J1113 pulses 2
VBATT.tr3
transient supply voltage
SAE J1113 pulses 3A, 3B
MIN.
–20
MAX.
+24
V
+50
V
–100
1
VB
Bus voltage
Rf > 10 kΩ ; Rb >10Ω
VB.tr1
transient bus voltage
SAE J1113 pulse 1
VB.tr2
transient bus voltage
SAE J1113 pulses 2
VB.tr3
transient bus voltage
SAE J1113 pulses 3A, 3B
VI
DC voltage on pins TX, R/F, RX, /LB
ESDBATT
ESD capability of BATT pin
ESDbus
UNIT
V
+150
V
–200
+200
V
–20
+20
V
–50
V
+100
V
–200
+200
V
–0.3
7
V
Air gap discharge,
R=2kΩ, C=150pF
–9
+9
kV
ESD capability of BUS_OUT and BUS_IN pins
Air gap discharge,
R=2kΩ, C=150pF
–9
+9
kV
ESDlogic
ESD capability of TX, RX, R/F, and /LB pins
Human Body,
R=1.5kΩ, C=100pF
–2
+2
kV
Ptot
maximum power dissipation
at Tamb = +125 °C
164
mW
ΘJA
thermal impedance
in free air
152
°C/W
Tamb
operating ambient temperature
–40
+125
°C
Tstg
storage temperature
–40
+150
°C
Tvj
junction temperature
–40
+150
°C
NOTE:
1. For bus voltages –20V < Vbus < –17V and +17V < Vbus < +20V the current is limited by the external resistors Rb and Rf.
1998 Jun 30
5
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
CHARACTERISTICS
–40°C < Tamb < +125°C; 6V < VBATT< 16V; V/LB> 3V; 0 < VBUS< +8.5V;
RS= 56 k Rd= 10 k; Rf = 15 k; Rb= 10; 300 < RL< 1.6 k;
all voltages are referenced to pin 8 (GND); positive currents flow into the IC; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IBATT.id
supply current; bus idle
TX low; Note 1
200
µA
IBATT.p
supply current; passive state
TX low
1.5
mA
IBATT.oc
supply current; no load
TX high
8
mA
IBATT.sc
supply current; bus short to GND
TX high, VBO = 0V
50
mA
Tsd
Thermal shutdown
155
Thys
Thermal shutdown hysteresis
5
°C
15
°C
Pins TX and /LB
Vih
High level input voltage
3
V
Vil
Low level input voltage
Vh
Input hysteresis
Iih2
TX high level input current
Vi = 5V
12
50
µA
Iih6
/LB high level input current
Vi = 5V
3
10
µA
Vol
Low level output voltage
Io = 1.6 mA
0.4
V
Iih
High level output leakage
Vo = 5V
–10
+10
µA
Irx
RX output current
Vo = 5V
4
20
mA
Volb
BUS_OUT in loop-back mode; TX high or low
/LB low or floating;
0<VBATT < 24V; RL=1.6kΩ
0.1
V
Vol
BUS_OUT voltage; passive
TX low or floating;
0<VBATT < 24V; RL=1.6kΩ
0.1
V
Voh
BUS_OUT voltage; active
TX high; Note 2
9V<VBATT < 24V;
300Ω < RL<1.6kΩ;
7.3
8
V
Vohb
BUS_OUT voltage; low battery
TX high;
6V<VBATT <9V;
300Ω < RL< 1.6kΩ;
Note 2
VBATT – 1.7
8
V
– IBO.LIM
BUS_OUT source current; bus positive
TX high;
0V< Vbus <+8.5V
47
mA
– IBO.LIMn
BUS_OUT source current; bus negative
TX high;
–17V< Vbus < 0V
55
mA
– IBO.LK
BUS_OUT leakage current; TX low; bus positive
TX low; 0V<VBATT<24V;
0V< Vbus <+17V
–10
+10
µA
– IBO.N
BUS_OUT leakage current; TX low; bus negative
TX low; 0V<VBATT<24V;
–17V< Vbus < 0V
–10
+100
µA
– IBO.LOG
BUS_OUT leakage current with loss of ground
0V<VBATT<16V
–10
100
µA
0.9
0.4
V
V
Pin RX
Pin BUS_OUT
Pin BUS_IN
Vih
Input high voltage
Vil
Input low voltage
Vh
Input hysteresis
Vilk
Input leakage current
1998 Jun 30
4.1
V
3.65
100
–17V < Vbus < +17V
6
–5
V
mV
+5
µA
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
DYNAMIC CHARACTERISTICS
–40°C < Tamb < +125°C; 9V < VBATT< 16V; V/LB > 3V; 0V <VBUS < +8.5V;
RS = 56 kW; Rd= 10 kW; Rf= 15 kW; Rb= 10W; BUS_OUT: 300W < RL< 1.6 kW;
1.7 ms < (RL * CL) < 5.2 ms; 2.2 nF < CL < 16 nF; RX: CL < 40pF; unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pins TX, RX, /LB
16
25
µs
/LB low
16
25
µs
Delay TX to RX rising and falling edge
6V < VBATT< 9V
16
25
µs
tpI_lobatt
Delay TX to RX rising and falling edge in
loop-back mode
/LB low,
6V < VBATT< 9V
16
25
µs
tdIb
Delay /LB to BUS_OUT
TX high, toggle /LB
1
10
µs
tbo
Delay TX to BUS_OUT
measured at 3.875V
15
24
µs
tbo_lobatt
Delay TX to BUS_OUT
measured at 3.875V,
6V < VBATT< 9V
15
24
µs
Vsr
Bus output voltage slew rate
6V < VBATT< 16V;
measured at 1.5V and min
[6.25V, VBATT–2.75V]
0.238
0.365
Isr
Bus output current slew rate
6V < VBATT< 16V;
RL= 100W; measured at 30% and
70% of waveform
0.87
2.1
mA/µs
VdB_limit
Bus emissions voltage output
f > 500 kHz
–60
dBV
NR
Bus noise rejection from battery
30 Hz < f < 250kHz
20
dB
NI
Bus noise isolation from battery
250 kHz < f < 200 MHz
16
dB
tp
Delay TX to RX rising and falling edge
tpI
Delay TX to RX rising and falling edge in
loop-back mode
tp_lobatt
Pin BUS_OUT
V/µs
Pin Rs
Ksr
Slew rate relationship factor, Note 3
0.7
CBIN
Bus Input capacitance
tDRXON;
TDRXOFF
Bus line to RX propagation delay
With 8V / 0V square wave input,
Rf = 15kΩ
TDRX_∆
Bus line to RX propagation delay mismatch
tDRXOFF –tDRXON
time-out to low power state
TX low
1
1.3
–
10
20
pF
0.4
1.7
µs
1
µs
4
ms
Pin BUS_IN
Pin BATT
tlow_power
NOTES;
1. TX < 0.9V for more than 4 ms
2. For 6V < VBATT < 9V the bus output voltage is limited by the supply voltage.
For 16V < VBATT < 24V (jump start) the load is limited by the package power dissipation
ratings; the duration of this condition is recommended to be less than 90 seconds.
3. Vsr = (Ksr * Vsr.nom * Rs.nom) / Rs
with Vsr.nom = 0.3 V/µs; Rs.nom = 56 kΩ; 45 kΩ < Rs < 70 kΩ
1998 Jun 30
7
1
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
APPLICATION INFORMATION
J1850 LINKCONTROLLER
VPWO
VPWI
+5V
10NF
10k
2)
56k
TX
RX
R/F
/LB
+12V
BATT
AU5780
TRANSCEIVER
BUS_IN
15k
BUS_OUT
10
GND
RL
1)
CL
SAE/J1850 VPW BUS LINE
SL01197
NOTES:
1. Value depends, e.g., on type of bus node. Example: primary node RL=1.6k , secondary node RL=11k.
2. For connection of /LB there are different options, e.g., connect to VCC or to low-active reset or to a port pin.
1998 Jun 30
8
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
SO8: plastic small outline package; 8 leads; body width 3.9mm
1998 Jun 30
9
SOT96-1
Philips Semiconductors
Product specification
SAE/J1850/VPW transceiver
AU5780
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
1998 Jun 30
10
Date of release: 05-96
9397 750 04079