INTEGRATED CIRCUITS AU5780A SAE/J1850/VPW transceiver Product data Supersedes data of 1999 Jan 28 2001 Jun 19 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A FEATURES DESCRIPTION • Supports SAE/J1850 VPW standard for in-vehicle class B The AU5780A is a line transceiver being primarily intended for in-vehicle multiplex applications. It provides interfacing between a link controller and the physical bus wire. The device supports the SAE/J1850 VPWM standard with a nominal bus speed of 10.4 kbps. multiplexing • Bus speed 10.4 kbps nominal • Drive capability 32 bus nodes • Low RFI due to output waveshaping with adjustable slew rate • Direct battery operation with protection against +50V load dump, PIN CONFIGURATION jump start and reverse battery • Bus terminals proof against automotive transients up to –200V/+200V BATT 1 8 GND TX 2 7 BUS_OUT R/F 3 6 /LB RX 4 5 BUS_IN • Thermal overload protection • Very low bus idle power consumption • Diagnostic loop-back mode • 4X mode (41.6 kbps) reception capability • ESD protected to 9 KV on bus and battery pins • 8-pin SOIC AU5780A SO8 SL01207 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 6 12 24 V VBATT.op Operating supply voltage TA Operating ambient temperature +125 °C VBATT.ld Battery voltage load dump; 1s +50 V IBATT.lp Bus idle supply current VBATT=12V 220 µA VB Bus voltage 0 < VBATT < 24V –20 +20 V VBOH Bus output voltage 300Ω < RL < 1.6kΩ 7.3 8.0 V –IBO.LIM Bus output source current 0V < VBO < +6.0V 27 50 mA VBI Bus input threshold 3.65 4.1 V tbo Delay TX to BUS_OUT, normal battery Measured at 3.875V 13 21 µs tr, tf BUS_OUT transition times, rise and fall, normal battery Measured between 1.5 V and (VBATT – 2.75 V), 9 < VBATT < 16 V, tr tested at an additional bus load of RLOAD = 400 W and CLOAD = 22000 pF 11 18 µs –40 ORDERING INFORMATION DESCRIPTION SO8: 8-pin plastic small outline package 2001 Jun 19 2 TEMPERATURE RANGE ORDER CODE DWG # –40 to +125°C AU5780AD SOT96-1 853-2261 26558 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A BLOCK DIAGRAM BATTERY (+12V) BATT 1 LOW–POWER VOLTAGE TIMER REFERENCE TEMP. PROTECTION BUS_OUT TX 2 OUTPUT BUFFER TX– BUFFER 7 Rb Rs R/F 3 /LB 6 INPUT BUFFER Rf Vcc Rd 4 INPUT 5 BUS_IN FILTER RX VOLTAGE REFERENCE AU5780 8 GND SL01208 2001 Jun 19 3 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A PIN DESCRIPTION SYMBOL PIN DESCRIPTION BATT 1 Battery supply input (12V nom.) TX 2 Transmit data input; low: transmitter passive; high: transmitter active R/F 3 Rise/fall slew rate set input RX 4 Receive data output; low: active bus condition detected; float/high: passive bus condition detected BUS_IN 5 Bus line receive input /LB 6 Loop-back test mode control input; low: loop-back mode; high: normal communication mode BUS_OUT 7 Bus line transmit output GND 8 Ground the automotive environment. Specifically, the BATT input is protected against 50V load dump, jump start and reverse battery condition. The BUS_OUT output is protected against wiring fault conditions, e.g., short circuit to battery voltage as well as typical automotive transients (i.e., –200V / +200V). In addition, an overtemperature shutdown function with hysteresis is incorporated which protects the device under system fault conditions. The chip temperature is sensed at the bus drive transistor in the output buffer. In case of the chip temperature reaching the trip point, the AU5780A will latch-off the transceiver function. The device is reset on the first rising edge on the TX input after a small decrease of the chip temperature. FUNCTIONAL DESCRIPTION The AU5780A is an integrated line transceiver IC that interfaces an SAE/J1850 protocol controller IC to the vehicle’s multiplexed bus line. It is primarily intended for automotive “Class B” multiplexing applications in passenger cars using VPW (Variable Pulse Width) modulated signals with a nominal bit rate of 10.4 kbps. The AU5780A also receives messages in the so-called 4X mode where data is transmitted with a typical bit rate of 41.6 kbps. The device provides transmit and receive capability as well as protection to a J1850 electronic module. A J1850 link controller feeds the transmit data stream to the transceiver’s TX input. The AU5780A transceiver waveshapes the TX data input signal with controlled rise & fall slew rates and rounded shape. The bus output signal is transmitted with both voltage and current control. The BUS_IN input is connected to the physical bus line via an external resistor. The external resistor and an internal capacitance provides filtering against RF bus noise. The incoming signal is output at the RX pin being connected to the J1850 link controller. The AU5780A also provides a loop-back mode for diagnostic purpose. If the /LB pin is open circuit or pulled low, then TX signal is internally looped back to the RX output independent of the signals on the bus. In this mode the electronic module is disconnected from the bus, i.e., the TX signal is not output to the physical bus line. In this mode, it can be used, e.g., for self-test purpose. The AU5780A is an enhanced successor of the AU5780. The AU5780A provides improved wave shaping when exiting the low power standby mode for reduced EMI. Several parameters that were formerly only characterized to the maximum normal operating supply of 16 volts, have now been characterized to 24 volt supplies. These parameters which are tested and guaranteed to 24 volts are identified with appropriate test conditions in the “conditions” columns of the Characteristics tables, otherwise the conditions at the top of the characteristic table applies to all parameters. If the TX input is idle for a certain time, then the AU5780A enters a low-power mode. This mode is dedicated to help meet ignition-off current draw requirements. The BUS_IN input comparator is kept alive in the low-power mode. Normal power mode will be entered again upon detection of activity, i.e., rising edge at the TX input. The device is able to receive and transmit a valid J1850 message when initially in low-power mode. The AU5780A features special robustness at its BATT and BUS_OUT pins hence the device is well suited for applications in 2001 Jun 19 4 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A CONTROL INPUT SUMMARY BUS_OUT RX (out) TX passive (default state) float float (high) Loop-back TX active float low 1 Communication Transmitter passive float bus state1 1 Communication Transmitter active high low TX /LB MODE 0 0 Loop-back 1 0 0 1 BIT VALUE NOTE: 1. RX outputs the bus state. If the bus level is below the receiver threshold (i.e., all transmitters passive), then RX will be floating (i.e., high, considering external pull-up resistance). Otherwise, if the bus level is above the receiver threshold (i.e., at least one transmitter is active), then RX will be low. ABSOLUTE MAXIMUM RATINGS According to the IEC 134 Absolute Maximum System; operation is not guaranteed under these conditions; all voltages are referenced to pin 8 (GND); positive currents flow into the IC; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VBATT supply voltage VBATT.ld short-term supply voltage load dump; t < 1s VBATT.tr1 transient supply voltage SAE J1113 pulse 1 VBATT.tr2 transient supply voltage SAE J1113 pulses 2 VBATT.tr3 transient supply voltage SAE J1113 pulses 3A, 3B MIN. –20 MAX. +24 V +50 V –100 1 VB Bus voltage Rf > 10 kΩ ; Rb >10Ω VB.tr1 transient bus voltage SAE J1113 pulse 1 VB.tr2 transient bus voltage SAE J1113 pulses 2 VB.tr3 transient bus voltage SAE J1113 pulses 3A, 3B VI DC voltage on pins TX, R/F, RX, /LB ESDBATT ESD capability of BATT pin ESDbus UNIT V +150 V –200 +200 V –20 +20 V –50 V +100 V –200 +200 V –0.3 7 V Air gap discharge, R=2kΩ, C=150pF –9 +9 kV ESD capability of BUS_OUT and BUS_IN pins Air gap discharge, R=2kΩ, C=150pF, Rf > 10 kW –9 +9 kV ESDlogic ESD capability of TX, RX, R/F, and /LB pins Human Body, R=1.5kΩ, C=100pF –2 +2 kV Ptot maximum power dissipation at Tamb = +125 °C 164 mW ΘJA thermal impedance 152 °C/W Tamb operating ambient temperature –40 +125 °C Tstg storage temperature –40 +150 °C Tvj junction temperature –40 +150 °C TLEAD Lead temperature Soldering, 10 seconds maximum 265 °C ICL(BUS) Bus output clamp current No latch-up, |VBUS| = 25 V 100 mA ICL(BATT) Battery clamp current No latch-up or snap back, |VBATT| = 25 V 100 mA NOTE: 1. For bus voltages –20V < Vbus < –17V and +17V < Vbus < +20V the current is limited by the external resistors Rb and Rf. 2001 Jun 19 5 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A CHARACTERISTICS –40°C < Tamb < +125°C; 6V < VBATT< 16V; V/LB> 3V; 0 < VBUS< +8.5V; RS= 56.2 kW Rd= 10 kW; Rf = 15 kW; Rb= 10W; 300 W< RL< 1.6 kW; all voltages are referenced to pin 8 (GND); positive currents flow into the IC; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IBATT.id supply current; bus idle TX low; Note 1 220 µA IBATT.p supply current; passive state TX low 1.5 mA IBATT.oc supply current; no load TX high 8 mA IBATT(SB) supply current; bus output short to battery BUS to VBATT; no IBO current, VTX = high 10 mA IBATT.sc supply current; bus short to GND TX high, VBO = 0V 60 mA Tsd Thermal shutdown 155 170 °C Thys Thermal shutdown hysteresis 5 15 °C TDTYCY24 Thermal shutdown, transmit duty cycle, at 24 V Bus load, RLOAD = 300 W, CLOAD = 16.55 nF, VBATT = 24 V, T = 128 ms 33 % TDTYCY20 Thermal shutdown, transmit duty cycle, at 20 V Bus load, RLOAD = 300 W, CLOAD = 16.55 nF, VBATT = 20 V, T = 128 ms 45 % 3 V Pins TX and /LB Vih High level input voltage 6 V < VBATT < 24 V VILTX Low level input voltage, TX pin 6 V < VBATT < 24 V 0.9 V VilB Low level input voltage, LB pin 6V t VBATT t 24 V 0.8 V Vh Input hysteresis 0.4 V CTX TX input capacitance Intrinsic to part 5 pf Iih2 TX high level input current Vi = 5V 12 50 µA Iih6 /LB high level input current Vi = 5V 4 10 µA Vol Low level output voltage Io = 1.6 mA 0.4 V Iih High level output leakage Vo = 5V, BUS_IN = low –10 +10 µA Irx RX output current Vo = 5V 4 20 mA Volb BUS_OUT in loop-back mode; TX high or low /LB low or floating; 0<VBATT < 24V; RL=1.6kΩ 0.1 V Vol BUS_OUT voltage; passive TX low or floating; 0<VBATT < 24V; RL=1.6kΩ 0.075 V Voh BUS_OUT voltage; active TX high; Note 2 9V<VBATT < 24V; 300Ω < RL<1.6kΩ; 7.3 8 V VohLOWB BUS_OUT voltage; low battery TX high; 6V<VBATT <9V; 300Ω < RL< 1.6kΩ; Note 2 VBATT – 1.7 8 V – IBO.LIM BUS_OUT source current; bus positive TX high; 9V<VBATT<24V 0V< Vbus <+6.0V 27 50 mA – IBO.LIMn BUS_OUT source current; bus negative TX high; 9V<VBATT<24V –17V< Vbus < 0V 28 55 mA Pin RX Pin BUS_OUT 2001 Jun 19 6 Philips Semiconductors Product data SAE/J1850/VPW transceiver SYMBOL AU5780A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT – IBO.LK.HO BUS_OUT leakage current; TX high; bus low or operational –17 < VBUS < 8.5 V; TX = high; 0 V < VBATT < 24 V –10 IBO.LIM µA – IBO.LK.HH BUS_OUT leakage current; TX high; bus positive 8.5 V < VBUS < 17 V; TX = high; 0 V < VBATT < 24 V –10 10 µA – IBO.LK BUS_OUT leakage current; TX low; bus positive TX low; 0V<VBATT<24V; 0.1V< Vbus <+17V –10 +10 µA – IBO.N BUS_OUT leakage current; TX low; bus negative TX low; 0.1V<VBATT<24V; –17V< Vbus < 0V –10 +100 µA – IBO.LOG BUS_OUT leakage current with loss of ground –17 V < VBUS < 17 V; 0 V <VBATT < 1 V –10 100 µA CBUSOUT Bus output capacitance 20 pF Pin BUS_IN Vih Input high voltage Vil Input low voltage Vh Input hysteresis IBIN Input bias current –17V < Vbus < +17V –5 +5 µA IBIN(MAX) BUS_IN input current maximum with and without loss of ground –17 < VBUS < 17 V; 0 V < VBATT < 24 V; VTX high or low –100 100 µA CBUSIN, Bus input capacitance 10 20 pF TDRXON, tDRXOFF Bus line to RX propagation delay, normal and 4X modes 0.4 1.7 ms 2001 Jun 19 4.1 V 3.65 100 Measured at VBUSIN_HIGH or VBUSIN_LOW to RX; 6 < VBATT < 24 V; of RLOAD = 10 KW to 5 V 7 V mV Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A DYNAMIC CHARACTERISTICS –40°C < Tamb < +125°C; 9V < VBATT< 16V; V/LB > 3V; 0V <VBUS < +8.5V; RS = 56.2 kW; Rd= 10 kW; Rf= 15 kW; Rb= 10W; BUS_OUT: 300W < RL< 1.6 kW; 1.7 ms < (RL * CL) < 5.2 ms; 2.2 nF < CL < 16.55 nF; RX: CL < 40pF; unless otherwise specified. PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Pins TX, RX, /LB tpI Delay TX to RX rising and falling edge in loop-back mode /LB low 6 V < VBATT < 24 V 15 24 µs tdIb Delay /LB to BUS_OUT TX high, toggle /LB 1 10 µs tbo Delay TX to BUS_OUT, normal battery Measured at 3.875V, Note 3 13 21 µs tbo_hibatt Delay TX to BUS_OUT, high battery Measured at 3.875V, 16V < VBATT< 24V, Note 3 13 21 µs tbo_lobatt Delay TX to BUS_OUT, low battery Measured at 3.875V, 6V < VBATT< 9V, Note 3 13 22 µs tr, tf BUS_OUT transition times, rise and fall, normal battery Measured between 1.5 V and (VBATT – 2.75 V), 9 < VBATT < 16 V, tr tested at an additional bus load of RLOAD = 400 W and CLOAD = 22000 pF 11 18 µs tr_hibatt, tf_hibatt BUS_OUT transition times, rise and fall, high battery Measured between 1.5 V and 6.25 V, 16 < VBATT < 24 V, tr tested at an additional bus load of RLOAD = 400 W and CLOAD = 22000 pF 11 18 µs tr_lobatt, tf_lobatt BUS_OUT transition times, rise and fall, low battery Measured between 1.5 V and 6.25 V, 6 < VBATT < 9 V, tr tested at an additional bus load of RLOAD = 400 W and CLOAD = 22000 pF (VBATT – 4.25) / 0.43 (VBATT – 4.25) / 0.264 µs Isr Bus output current slew rate 6V < VBATT< 16V; RS = 56.2 kW RL= 100W; measured at 30% and 70% of waveform, DC offset 0 to –2V 0.90 2.4 mA/µs VdB_limit Bus emissions voltage output 0 V < DC_offset < 1 V, 9 V < VBATT < 24 V, RL = 500 W, CL = 6 nF –50 dBV VdB_limit–1 Bus emissions voltage output, negative bus offset –1 V < DC_offset < 0 V, 9 V < VBATT < 24 V, RL = 500 W, CL = 6 nF –50 dBV NR Bus noise rejection from battery 30 Hz < f < 250kHz 20 dB NI Bus noise isolation from battery 250 kHz < f < 200 MHz 17 dB Pin BUS_OUT 2001 Jun 19 8 Philips Semiconductors Product data SAE/J1850/VPW transceiver SYMBOL AU5780A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Pin BUS_IN CBIN Bus Input capacitance 10 20 pF TDRXON; tDRXOFF Bus line to RX propagation delay, normal and 4x modes Measured at VBUSIN_HIGH or VBUSIN_LOW to RX; 6 < VBATT < 24 V; of RLOAD = 10 kW to 5V 0.4 1.7 µs TDRX_∆ Bus line to RX propagation delay mismatch, normal and 4x modes tDRXOFF –tDRXON –1.3 +1.3 µs time-out to low power state TX low 1 4 ms Pin BATT tlow_power NOTES; 1. TX < 0.9V for more than 4 ms 2. For 6V < VBATT < 9V the bus output voltage is limited by the supply voltage. For 16V < VBATT < 24V (jump start) the load is limited by the package power dissipation ratings; the duration of this condition is recommended to be less than 90 seconds. 3. Tested with a bus load of RLOAD = 400 W and CLOAD = 22,000 pF. 2001 Jun 19 9 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A APPLICATION INFORMATION SAEJ1850 LINK CONTROLLER VPWO VPWI Rd +5V 10NF Cs 10k 2) Rs, 56.2 kW, 1% TX RX R/F /LB +12V BATT AU5780A TRANSCEIVER BUS_IN 15k Rf BUS_OUT GND 10W RL NOTE 1 CL SAE/J1850 VPW BUS LINE SL01209 NOTES: 1. Value depends, e.g., on type of bus node. Example: primary node RL=1.5kW , secondary node RL=10.7kW. 2. For connection of /LB there are different options, e.g., connect to VCC or to low-active reset or to a port pin. 3. The value of CL is suggested to be in the range 330 pF < CL < 470 pF. 2001 Jun 19 10 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A SO8: plastic small outline package; 8 leads; body width 3.9 mm 2001 Jun 19 11 SOT96-1 Philips Semiconductors Product data SAE/J1850/VPW transceiver AU5780A Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-01 Document order number: 2001 Jun 19 12 9397 750 08501