UBA2037 Full bridge control IC for HID general lighting Rev. 01 — 30 October 2008 Product data sheet 1. General description The UBA2037 is a high voltage monolithic Integrated Circuit (IC) manufactured in a High Voltage Silicon On Insulator (HVSOI) process. This circuit is designed for driving MOSFETs in a full bridge configuration. In addition, it features a disable function, an internal adjustable oscillator and an external clock input function with a high-voltage level shifter for driving the bridge. To guarantee an accurate 50 % duty cycle, the oscillator signal can be passed through a divider before being fed to the output drivers. The UBA2037 is especially suitable for High Intensity Discharge (HID) lamp drivers for projectors and general lighting applications. 2. Features n n n n n n n n n n n Full bridge driver circuit Integrated bootstrap diodes 464 V integrated high voltage level shift function to drive HID lamps below ground level 550 V series regulator input to make the internal supply 550 V maximum bridge voltage Accurate bridge disable function Input for start-up delay Adjustable oscillator frequency Selectable frequency divider Predefined bridge position during start-up Adaptive non-overlap 3. Applications n The UBA2037 can drive (via the power MOSFETs) any kind of load in a full bridge configuration. n The circuit is especially designed as a commutator controller for HID lamps in projectors and general lighting applications. UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 4. Ordering information Table 1. Ordering information Type number Package Name Description Version UBA2037T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 UBA2037TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 5. Block diagram VSS(CLK) CLK 1 VDD(CLK) 3 2 16 FSL HIGHER LEFT DRIVER 15 GHL 6 HV 17 14 STABILIZER SGND VDD RC 27 LOGIC SIGNAL GENERATOR 9 13 HIGH VOLTAGE LEVEL SHIFTER HIGHER RIGHT DRIVER 28 26 UBA2037TS OSCILLATOR LOWER RIGHT DRIVER ÷2 23 21 SU BD 10 12 LOW VOLTAGE LEVEL SHIFTER LOGIC LOWER LEFT DRIVER 20 SHL FSR GHR SHR GLR PGND GLL 1.29 V bridge disable 11 DD Fig 1. 4, 5, 7, 8, 18, 19, 22, 24, 25 n.c. 014aaa635 Block diagram UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 2 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 6. Pinning information 6.1 Pinning VSS(CLK) 1 28 GHR CLK 2 27 FSR VSS(CLK) 1 24 GHR VDD(CLK) 3 26 SHR CLK 2 23 FSR n.c. 4 25 n.c. VDD(CLK) 3 22 SHR n.c. 5 24 n.c. n.c. 4 21 n.c. HV 6 23 GLR HV 5 20 GLR n.c. 7 n.c. 6 19 n.c. n.c. 8 VDD 7 VDD 9 20 GLL SU 8 17 GLL SU 10 19 n.c. DD 9 16 n.c. DD 11 18 n.c. BD 10 15 SHL BD 12 17 SHL RC 11 14 FSL RC 13 16 FSL SGND 12 13 GHL SGND 14 15 GHL UBA2037T 18 PGND 014aaa636 Fig 2. 22 n.c. UBA2037TS 21 PGND 014aaa637 SO24 package Fig 3. SSOP28 package 6.2 Pin description Table 2. Pin description Symbol Pin Pin Description UBA2037T UBA2037TS VSS(CLK) 1 1 negative supply voltage for logic oscillator input CLK 2 2 oscillator input VDD(CLK) 3 3 positive supply voltage for logic oscillator input n.c. 4 4 not connected 5 not connected n.c. HV 5 6 high voltage supply input for internal series regulator n.c. 6 7 not connected 8 not connected n.c. VDD 7 9 internal low voltage supply SU 8 10 input for start-up delay DD 9 11 input for divider disable BD 10 12 input for bridge disable RC 11 13 RC input for internal oscillator SGND 12 14 signal ground GHL 13 15 gate driver output for upper left MOSFET FSL 14 16 floating supply left SHL 15 17 source upper left MOSFET n.c. 16 18 not connected UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 3 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting Table 2. Symbol Pin description …continued Pin Pin Description UBA2037T UBA2037TS n.c. 19 not connected GLL 17 20 gate driver output for lower left MOSFET PGND 18 21 power ground n.c. 19 22 not connected GLR 20 23 gate driver output for lower right MOSFET n.c. 21 24 not connected 25 not connected SHR 22 26 source upper right MOSFET FSR 23 27 floating supply right GHR 24 28 gate driver upper right MOSFET n.c. 7. Functional description 7.1 Supply voltage The UBA2037 is powered by a supply voltage applied to pin HV, e.g. the supply voltage of the full bridge. The IC generates its own low supply voltage for its internal circuitry. Therefore an additional low voltage supply is not required. A capacitor has to be connected to pin VDD to obtain a ripple-free internal supply voltage. The circuit can also be powered by a low voltage supply directly applied to pin VDD. In this case pin HV should be connected to pin VDD or pin SGND. The maximum current that the internal series regulator can deliver, is temperature dependent. This is shown in Figure 4. 7.2 Start-up With an increasing supply voltage the IC enters the start-up state i.e. the upper power transistors are set in off-state and the lower power transistors are switched on. During the start-up state the bootstrap capacitors are charged. The start-up state is defined until VVDD = Vstartup(VDD) or VHV = Vstartup(HV). The state of the outputs during the start-up phase is overruled by the bridge disable function. 7.3 Oscillation state At the moment the supply voltage on pin VDD exceeds Vstartup(VDD) or the supply voltage on pin VHV exceeds Vstartup(HV), the output voltage of the full bridge depends on the control signals on pins CLK, SU, DD and BD. This is listed in Table 3. As soon as the supply voltage on pin VDD becomes lower than VUVLO(VDD) or the supply voltage on pin VHV becomes lower than VUVLO(HV), the IC enters the start-up state again. UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 4 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting Table 3. Driver Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK. Device state BD SU DD CLK GHL GHR GLL GLR Start-up state 1 - - - 0 (= VSHL) 0 (= VSHR) 0 (= VPGND) 0 (= VPGND) 0 - - - 0 (= VSHL) 0 (= VSHR) 1 (= VVDD) 1 (= VVDD) 1 - - - 0 (= VSHL) 0 (= VSHR) 0 (= VPGND) 0 (= VPGND) 0 0 - - 0 (= VSHL) 0 (= VSHR) 1 (= VVDD) 1 (= VVDD) 0 1 1 1 0 (= VSHL) 1 (= VFSR) 1 (= VVDD) 0 (= VPGND) 0 1 1 0 1 (= VFSL) 0 (= VSHR) 0 (= VPGND) 1 (= VVDD) 1 0[1] 1→ GHL GHR GLL Oscillation state 0 0[2] GLR [1] If pin DD = 0 the bridge enters the state (oscillation state and pin BD = 0 and pin SU = 1) in the predefined position: VGHL = VFSL, VGLR = VVDD, VGLL = VPGND, and VGHR = VSHR. [2] Only if the level of pin CLK changes from logical 1 to 0, the level of outputs GHL, GHR, GLL and GLR changes. If there is no external clock available, the internal oscillator can be used. The design equation for the bridge oscillator frequency is shown in Equation 1. 1 f bridge = --------------------------------------------K osc × R osc × C osc (1) Rosc and Cosc are external components connected to the RC pin (Rosc connected to pin VDD and Cosc connected to pin SGND). In this situation the pins VDD(CLK), CLK and VSS(CLK) can be connected to SGND. The clock signal, coming from either pin RC or pin CLK, can be divided by two in order to obtain a 50 % duty-cycle gate drive signal. This can be achieved by applying a voltage to the DD input lower than VIL(DD) (e.g. connect pin DD to pin SGND). 7.4 Non-overlap time In the full bridge configuration the non-overlap time is defined as the time between turning off the two conducting MOSFETs and turning on the two other MOSFETs. The non-overlap time is realized by means of an adaptive non overlap circuit. With an adaptive non-overlap, the application determines the duration of the non overlap and makes the non-overlap time optimal for each frequency. The non-overlap time is determined by the duration of the falling slope of the relevant half bridge voltage. The occurrence of a slope is sensed internally. The minimum non-overlap time is internally fixed. 7.5 Start-up delay A simple RC filter (R between pin VDD and pin SU; C between pin SU and pin SGND) or a control signal from a processor can be used to make a start-up delay. This can be beneficial for those applications in which building up the high voltage takes a larger amount of time: A start-up delay will ensure that the HID system will not start up before this high voltage has been reached. UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 5 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 7.6 Bridge disable The bridge disable function can be used to switch off all the MOSFETs as soon as the voltage on pin BD exceeds the bridge disable voltage VBD. The bridge disable function overrules all the other states. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to signal ground (pin 14); positive currents flow into the chip. The voltage ratings are valid provided other ratings are not violated. Symbol Parameter Conditions Min Max Unit General Tamb ambient temperature −40 +125 °C Tj junction temperature −40 +150 °C Tstg storage temperature −55 +150 °C DC 0 14 V maximum pulse time = 100 ns 0 17 V 0 550 V with respect to PGND and SGND −3 550 V with respect to SGND; maximum pulse time = 1 µs −14 550 V with respect to PGND and SGND −3 550 V with respect to SGND; maximum_pulse_time = 1 µs −14 550 V Voltages VVDD voltage on pin VDD VHV voltage on pin HV VSHL voltage on pin SHL VSHR voltage on pin SHR VFSL voltage on pin FSL with respect SHL 0 14 V VFSR voltage on pin FSR with respect SHR 0 14 V VGHL voltage on pin GHL VSHL VFSL V VGHR voltage on pin GHR VSHR VFSR V VGLL voltage on pin GLL VPGND VVDD V VGLR voltage on pin GLR VPGND VVDD V VPGND voltage on pin PGND 0 5 V VSS(CLK) CLK ground supply voltage t<1s 0 464 V VDD(CLK) CLK supply voltage t<1s 0 464 V DC 0 14 V maximum pulse time = 100 ns 0 17 V with respect to VSS(CLK): VI input voltage pins CLK, SU, BD, and DD; with respect to VSS(CLK): DC 0 VVDD V maximum pulse time t = 100 ns 0 17 V 0 17 V pins SHL and SHR - 6 V/ns pin VSS(CLK) - 0.5 V/µs pin RC: maximum pulse time = 100 ns SR slew rate UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 6 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to signal ground (pin 14); positive currents flow into the chip. The voltage ratings are valid provided other ratings are not violated. Symbol Parameter Conditions Min Max Unit oscillator resistance connected between pins VDD and RC 100 - kΩ electrostatic discharge voltage human body model: HV, VSS(CLK), VDD(CLK),CLK, FSL, FSR, GHL, GHR, SHL, SHR - 900 V other pins - 2 kV machine model: all pins - 200 V charged device model: all pins - 500 V Currents Rosc ESD VESD 9. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 100 K/W 10. Characteristics Table 6. Characteristics Tj = 25 °C; all voltages are measured with respect to signal ground (pin 14); currents are positive when flowing into the IC, Unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit leakage current pin HV; IHV (VHV = 565 V) − IHV (VHV = 500 V) - 0 10 µA High voltage Ileak pin FSL; VFSL = VSHL = VGHL = 564 V - 0 5 µA pin FSR; VFSR = VSHR = VGHR = 564 V - 0 5 µA pin VSS(CLK); VSS(CLK)= VCLK = 450 V - 0 10 µA pin VDD(CLK); VDD(CLK) = VCLK = 464 V - 0 10 µA VHV = 80 V - 590 825 µA Start-up via HV pin II(HV) input current on pin HV Vstartup(HV) start-up voltage on pin HV 11.3 13.2 14.7 V VUVLO(HV) undervoltage lockout voltage on pin HV 8.6 10.7 12.2 V Vhys hysteresis voltage 2 2.5 3 V VVDD voltage on pin VDD VHV = 20 V 10.5 12 13.5 V VVDD = 8.25 V - 500 800 µA 8.25 9.0 9.75 V Start-up via VDD pin II(VDD) input current on pin VDD Vstartup(VDD) start-up voltage on pin VDD UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 7 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting Table 6. Characteristics …continued Tj = 25 °C; all voltages are measured with respect to signal ground (pin 14); currents are positive when flowing into the IC, Unless otherwise specified. Symbol Parameter VUVLO(VDD) undervoltage lockout voltage on pin VDD Vhys hysteresis voltage on-state resistance Conditions Min Typ Max Unit 5.75 6.5 7.25 V VFSL = VFSR = 12 V 2 2.5 3 V GHR and GHL drivers; VFSL = VFSR = 12 V; VSHL = VSHR = 0 V; IGHL = IGHR = −50 mA - 20 42 Ω GLR and GHL drivers; VVDD = 12 V; VPGND = 0 V; IGLL = IGLR = −50 mA - 20 42 Ω GHR and GHL drivers; VFSL = VFSR = 12 V; VSHL = VSHR = 0 V; IGHL = IGHR = 50 mA - 12 26 Ω GLR and GLL drivers; VVDD = 12 V; VPGND = 0 V; IGLL = IGLR = 50 mA - 12 26 Ω gate drivers Ron Roff off-state resistance IO(source) output source current VFSL = VFSR = VVDD = 12 V; VSHL = VSHR = 0 V; VGHL = VGHR = VGLL = VGLR = 8 V - 200 - mA IO(sink) output sink current VFSL = VFSR = VVDD = 12 V; VSHL = VSHR = 0 V; VGHL = VGHR = VGLL = VGLR = 8 V - 200 - mA Vd(bs) bootstrap diode voltage current on diode = 1 mA 0.8 1.0 1.2 V dV/dt rate of change of voltage absolute values 5 15 25 V/µs tno non-overlap time 600 900 1300 ns VUVLO undervoltage lockout voltage high side driver - 4.0 5.5 V IFS current on pin FS VFSL = VFSR = 12 V; VSHL = VSHR = 0 V 1 4 7 µA IFSL/IFSR current on pin FSL to current on pin FSR ratio 0.8 - 1.2 DD input VIH(DD) HIGH-level input voltage on pin DD VVDD = 12 V 6 4.5 - V VIL(DD) LOW-level input voltage on VVDD = 12 V pin DD - - 3 V II input current VVDD = 12 V - 0 1 µA Vstartup start-up voltage VVDD = 12 V 1 1.3 1.5 V Vhys hysteresis voltage VVDD = 12 V - 100 - µV II input current VVDD = 12 V - 0 1 µA HIGH-level input voltage on pin CLK VSS(CLK) = 0 V; VDD(CLK) = 12 V 0.9 1.6 2.7 V SU input CLK input VIH(CLK) UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 8 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting Table 6. Characteristics …continued Tj = 25 °C; all voltages are measured with respect to signal ground (pin 14); currents are positive when flowing into the IC, Unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Vhys hysteresis voltage VSS(CLK) = 0 V; VDD(CLK) = 12 V - 100 - mV II input current - 0 1 µA fbridge bridge frequency VRC= 0 V - - 200 kHz IDD(CLK) CLK supply current VSS(CLK) = 0 V; VDD(CLK) = 14 V - 420 625 µA VDD(CLK) CLK supply voltage VSS(CLK) = 0 V 5.75 - 14 V supply for CLK BD input VBD voltage on pin BD 1.23 1.29 1.35 V II input current - 0 1 µA kHz Internal oscillator fosc(int) internal oscillator frequency VCLK = 0 V; VSS(CLK) = 0 V - - 100 Kosc oscillator constant fbridge = 500 Hz 0.89 0.97 1.05 014aaa638 12 II (pin HV) (µA) 8 (1) (2) 4 (3) 0 0 200 400 600 VHV (V) (1) Temperature = −25 °C (2) Temperature = 25 °C (3) Temperature = 125 °C Fig 4. Typical II (pin HV) when VDD connected to SGND, as function of VHV and temperature UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 9 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 11. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 5. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SO24 (SOT137-1) UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 10 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 Fig 6. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Package outline SSOP28 (SOT341-1) UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 11 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 12. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes UBA2037_1 20081030 Product data sheet - - UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 12 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] UBA2037_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 13 of 14 UBA2037 NXP Semiconductors Full bridge control IC for HID general lighting 15. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Oscillation state . . . . . . . . . . . . . . . . . . . . . . . . 4 Non-overlap time . . . . . . . . . . . . . . . . . . . . . . . 5 Start-up delay . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bridge disable . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 October 2008 Document identifier: UBA2037_1