BUK95/9606-40B TrenchMOS™ logic level FET Rev. 01 — 14 May 2003 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS™ technology. Product availability: BUK9506-40B in SOT78 (TO-220AB) BUK9606-40B in SOT404 (D2-PAK). 1.2 Features ■ Very low on-state resistance ■ 175 °C rated ■ Q101 compliant ■ Logic level compatible. 1.3 Applications ■ Automotive systems ■ Motors, lamps and solenoids ■ 12 V loads ■ General purpose power switching. 1.4 Quick reference data ■ EDS(AL)S ≤ 494 mJ ■ ID ≤ 75 A ■ RDSon = 5.7 mΩ (typ) ■ Ptot ≤ 203 W. 2. Pinning information Table 1: Pinning - SOT78 and SOT404, simplified outlines and symbol Pin Description 1 gate (g) 2 drain (d) 3 source (s) mb mounting base, connected to drain (d) Simplified outline Symbol mb [1] mb d g MBB076 2 MBK106 1 2 3 SOT78 (TO-220AB) [1] It is not possible to make connection to pin 2 of the SOT404 package. 1 SOT404 3 MBK116 (D2-PAK) s BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS drain-source voltage (DC) VDGR drain-gate voltage (DC) VGS gate-source voltage (DC) ID drain current (DC) Conditions RGS = 20 kΩ Min Max Unit - 40 V - 40 V - ±15 V Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 [1] - 129 A [2] - 75 A Tmb = 100 °C; VGS = 5 V; Figure 2 [2] - 75 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 516 A Ptot total power dissipation Tmb = 25 °C; Figure 1 - 203 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C [1] - 129 A [2] - 75 A Tmb = 25 °C; pulsed; tp ≤ 10 µs - 516 A unclamped inductive load; ID = 75 A; VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω; starting Tmb = 25 °C - 494 mJ Source-drain diode reverse drain current (DC) IDR IDRM peak reverse drain current Tmb = 25 °C Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy [1] [2] Current is limited by power dissipation chip rating. Continuous current is limited by package. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 2 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 03na19 120 03nm23 150 Pder ID (A) (%) 80 100 40 50 Capped at 75 A due to package 0 0 0 50 100 150 200 Tmb (°C) 0 50 100 150 200 Tmb (°C) VGS ≥ 5 V P tot P der = ----------------------- × 100% P ° tot ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Continuous drain current as a function of mounting base temperature. 03nm21 103 Limit RDSon = VDS/ID ID (A) tp = 10 µ s 102 100 µ s Capped at 75 A due to package 1 ms DC 10 10 ms 100 ms 1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 3 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 4. Thermal characteristics Table 3: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Figure 4 - - 0.74 K/W SOT78 (TO-220AB) vertical in still air - 60 - K/W SOT404 (D2-PAK) minimum footprint; mounted on a PCB - 50 - K/W Rth(j-mb) thermal resistance from junction to mounting base Rth(j-a) thermal resistance from junction to ambient 4.1 Transient thermal impedance 03nm22 1 Zth(j-mb) (K/W) δ = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 δ= P tp T single shot t tp T 10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 4 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 5. Characteristics Table 4: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) IDSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 °C 40 - - V Tj = −55 °C 36 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 drain-source leakage current Tj = 25 °C 1.1 1.5 2 V Tj = 175 °C 0.5 - - V Tj = −55 °C - - 2.3 V Tj = 25 °C - 0.02 1 µA Tj = 175 °C - - 500 µA - 2 100 nA Tj = 25 °C - 5.7 6.4 mΩ Tj = 175 °C - - 12.2 mΩ VGS = 4.5 V; ID = 25 A - - 7.1 mΩ VGS = 10 V; ID = 25 A - 4.1 5 mΩ VGS = 5 V; VDD = 32 V; ID = 25 A; Figure 14 - 44 - nC - 11 - nC - 17 - nC - 3967 4901 pF - 634 760 pF - 278 380 pF - 43 - ns VDS = 40 V; VGS = 0 V IGSS gate-source leakage current VGS = ±15 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 5 V; ID = 25 A; Figure 7 and 8 Dynamic characteristics Qg(tot) total gate charge Qgs gate-source charge Qgd gate-drain (Miller) charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time - 145 - ns td(off) turn-off delay time - 132 - ns tf fall time - 92 - ns Ld internal drain inductance from drain lead 6 mm from package to center of die - 4.5 - nH from contact screw on mounting base to center of die SOT78 - 3.5 - nH from upper edge of drain mounting base to center of die SOT404 - 2.5 - nH from source lead to source bond pad - 7.5 - nH Ls internal source inductance VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 12 VDD = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 5 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET Table 4: Characteristics…continued Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - 0.85 1.2 V Source-drain diode VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 15 trr reverse recovery time Qr recovered charge IS = 20 A; dIS/dt = −100 A/µs VGS = −10 V; VDS = 30 V 61 - ns 57 - nC © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data - Rev. 01 — 14 May 2003 6 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 03nm18 300 10 7 6 5 ID (A) 4.8 200 03nm17 12 Label is VGS (V) 4.6 RDSon (mΩ) 4.4 10 4.2 4 8 3.8 3.6 100 3.4 6 3.2 3 2.8 2.6 0 0 2 4 4 6 8 10 VDS (V) Tj = 25 °C; tp = 300 µs 3 15 VGS (V) Fig 6. Drain-source on-state resistance as a function of gate-source voltage; typical values. 03nm19 16 3 11 Tj = 25 °C; ID = 25 A Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. RDSon (mΩ) 7 03aa27 2 Label is VGS (V) 3.2 3.4 3.6 a 3.8 1.5 4 12 1 5 8 0.5 10 4 0 0 100 200 ID (A) 300 Tj = 25 °C -60 60 120 Tj (°C) 180 R DSon a = ---------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data 0 Rev. 01 — 14 May 2003 7 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 10-1 03ng52 2.5 VGS(th) 03ng53 ID (A) (V) max 10-2 2.0 min 1.0 min -3 10 typ 1.5 typ max 10-4 10-5 0.5 10-6 0.0 -60 0 60 120 Tj (°C) 180 0 0.5 1 1.5 2 2.5 3 VGS (V) Tj = 25 °C; VDS = VGS ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. 03nm15 140 Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03nm20 7000 gfs (S) C (pF) 105 Ciss 5250 Coss 70 3500 Crss 35 1750 0 0 20 40 ID (A) 60 0 10-2 1 102 10 VDS (V) Tj = 25 °C; VDS = 25 V VGS = 0 V; f = 1 MHz Fig 11. Forward transconductance as a function of drain current; typical values. Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data 10-1 Rev. 01 — 14 May 2003 8 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 03nm16 100 03nm14 5 VGS (V) ID (A) 4 VDD = 14 V 75 VDD = 32 V 3 50 2 25 Tj = 175 °C Tj = 25 °C 1 0 0 0 1 2 3 4 0 10 VGS (V) 20 30 40 50 QG (nC) Tj = 25 °C; ID = 25 A VDS = 25 V Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Fig 14. Gate-source voltage as a function of gate charge; typical values. 03nm13 100 IS (A) 75 50 25 Tj = 175 °C Tj = 25 °C 0 0.0 0.3 0.6 0.9 1.2 VSD (V) VGS = 0 V Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 9 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 6. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB E SOT78 A A1 p q mounting base D1 D L2 L1(1) Q b1 L 1 2 3 b c e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E e L L1(1) L2 max. p q Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION REFERENCES IEC SOT78 JEDEC EIAJ 3-lead TO-220AB SC-46 EUROPEAN PROJECTION ISSUE DATE 00-09-07 01-02-16 Fig 16. SOT78 (TO-220AB). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 10 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 SOT404 Fig 17. SOT404 (D2-PAK). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 11 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 7. Soldering 10.85 10.60 10.50 handbook, full pagewidth 1.50 7.50 7.40 1.70 2.25 2.15 8.15 8.275 8.35 1.50 4.60 0.30 4.85 5.40 7.95 8.075 3.00 0.20 1.20 1.30 1.55 solder lands solder resist 5.08 MSD057 occupied area solder paste Dimensions in mm. Fig 18. Reflow soldering footprint for SOT404. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 12 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 8. Revision history Table 5: Revision history Rev Date 01 20030514 CPCN Description - Product data (9397 750 11241) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Product data Rev. 01 — 14 May 2003 13 of 15 BUK95/9606-40B Philips Semiconductors TrenchMOS™ logic level FET 9. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11241 Rev. 01 — 14 May 2003 14 of 15 Philips Semiconductors BUK95/9606-40B TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 4.1 5 6 7 8 9 10 11 12 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 May 2003 Document order number: 9397 750 11241