® SP507 +5V, Single Chip WAN Multi-Mode Serial Transceiver ■ Interface Modes Supported: ✓ RS-232 (V.28) ✓ X.21/RS-422 (V.11) ✓ EIA-530 (V.10 & V.11) ✓ EIA-530A (V.10 & V.11) ✓ RS-449 (V.10 & V.11) ✓ V.35 (V.35 & V.28) ■ Software Selectable Protocols ■ Highest Differential Transmission Rates available at over 20Mbps ■ +5V Only Operation ■ Seven (7) Drivers and Seven (7) Receivers ■ Driver and Receiver Tri-state Control ■ Internal Transceiver Termination Resistors for V.11 and V.35 Protocols ■ Improved ESD Tolerance for Analog I/Os ■ Compliant to NET1/2 and TBR2 Physical Layer Requirements ■ Used in WAN Serial Ports in Routers Switches, DSU/CSU's and other Access Devices ■ Available in 132-Lead Small Scale Ball Grid Array and 80-Lead MQFP DESCRIPTION The SP507 is a monolithic IC that supports seven (7) popular serial interface standards for DTE/DCE connectivity. The seven (7) drivers and seven (7) receivers transmit and receive signals at over 20Mbps. The SP507 requires no additional external components for compliant operation for all seven (7) modes of operation. All necessary termination is integrated within the SP507 and is switchable when V.35 drivers, V.35 receivers, and V.11 receivers are used. The SP507 can operate as either a DTE or DCE. Additional features include a latch enable pin with the driver and receiver address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 3-bit word into the address decoder. Four (4) drivers and four (4) receivers in the SP507 include separate enable pins for added convenience. V.35 EIA-530 WAN Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 1 © Copyright 2004 Sipex Corporation ABSOLUTE MAXIMUM RATINGS STORAGE CONSIDERATIONS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order remove moisture prior to soldering. Sipex ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. VCC............................................................................+7V Input Voltages: Logic...............................-0.3V to (VCC+0.5V) Drivers............................-0.3V to (VCC+0.5V) Receivers........................................±15.5V Output Voltages: Logic................................-0.3V to (VCC+0.5V) Drivers................................................±15V Receivers........................-0.3V to (VCC+0.5V) Storage Temperature..........................-65˚C to +150˚C Power Dissipation per package 80-pin QFP (derate 18.3mW/˚C above +70˚C)...1500mW SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS 0.8 Volts Volts 0.4 Volts Volts IOUT= –3.2mA IOUT= 1.0mA ±15 ±15 ±100 Volts Volts mA Ω per Figure 1 per Figure 2 per Figure 4 per Figure 5 VCC = +5V for AC parameters 1.5 30 µs V/µs per Figure 6; +3V to -3V per Figure 3 5 5 µs µs kbps 7 +2.0 3.0 kΩ Volts Volts Volts LOGIC INPUTS VIL VIH 2.0 LOGIC OUTPUTS VOL VOH 2.4 V.28 DRIVER DC Parameters Outputs Open Circuit Voltage Loaded Voltage Short-Circuit Current Power-Off Impedance AC Parameters Outputs Transition Time Instantaneous Slew Rate Propagation Delay tPHL tPLH Max.Transmission Rate ±5.0 300 0.5 0.5 120 1 1 230 V.28 RECEIVER DC Parameters Inputs Input Impedance Open-Circuit Bias HIGH Threshold LOW Threshold AC Parameters Propagation Delay tPHL tPLH Rev: A Date:1/27/04 3 0.8 1.7 1.2 per Figure 7 per Figure 8 VCC = +5V for AC parameters 50 50 100 100 500 500 ns ns SP507 Multi–Mode Serial Transceiver 2 © Copyright 2004 Sipex Corporation SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER (continued) AC Parameters (cont.) Max.Transmission Rate 120 230 kbps V.10 DRIVER DC Parameters Outputs Open Circuit Voltage Test-Terminated Voltage Short-Circuit Current Power-Off Current AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Max.Transmission Rate ±4.0 0.9VOC 50 50 120 ±150 ±100 Volts Volts mA µA 200 ns 500 500 ns ns kbps +3.25 mA kΩ Volts ±6.0 100 100 per Figure 9 per Figure 10 per Figure 11 per Figure 12 VCC = +5V for AC parameters per Figure 13; 10% to 90% V.10 RECEIVER DC Parameters Inputs Input Current Input Impedance Sensitivity AC Parameters Propagation Delay tPHL tPLH Max.Transmission Rate –3.25 4 ±0.3 per Figures 14 and 15 VCC = +5V for AC parameters 50 50 120 120 120 250 250 ns ns kbps ±5.0 0.67VOC ±0.4 +3.0 ±150 ±100 Volts Volts Volts Volts Volts mA µA 20 ns 85 85 20 ns ns ns Mbps +7 ±0.3 Volts Volts V.11 DRIVER DC Parameters Outputs Open Circuit Voltage Test Terminated Voltage Balance Offset Short-Circuit Current Power-Off Current AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate ±2.0 0.5VOC 50 50 65 65 10 20 per Figure 16 per Figure 17 per Figure 17 per Figure 17 per Figure 18 per Figure 19 VCC = +5V for AC parameters per Figures 21 and 36; 10% to 90% per Figures 33 and 36, CL = 50pF per Figures 33 and 36, CL = 50pF per Figures 33 and 36, CL = 50pF per Figure 33, CL = 50pF fIN = 10MHz V.11 RECEIVER DC Parameters Inputs Common Mode Range Sensitivity Rev: A Date:1/27/04 –7 SP507 Multi–Mode Serial Transceiver 3 © Copyright 2004 Sipex Corporation SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS ±3.25 ±60.75 mA mA kΩ CONDITIONS V.11 RECEIVER (continued) DC Parameters (cont.) Input Current Current w/ 100Ω Termination Input Impedance AC Parameters Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate –3.25 4 per Figure 20 and 22 per Figure 23 and 24 VCC = +5V for AC parameters 30 30 65 65 10 85 85 ns ns ns Mbps per Figures 33 and 38; CL = 50pF per Figures 33 and 38; CL = 50pF per Figure 33; CL = 50pF per Figure 33; CL = 50pF fIN = 10MHz ±1.20 ±0.66 ±0.6 150 165 Volts Volts Volts Ω Ω per Figure 16 per Figure 25 per Figure 25 per Figure 27; ZS = V2/V1 x 50Ω per Figure 28 VCC = +5V for AC parameters 30 40 ns 70 70 7 90 90 10 ns ns ns Mbps 20 V.35 DRIVER DC Parameters Outputs Open Circuit Voltage Test Terminated Voltage Offset Source Impedance Short-Circuit Impedance AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate ±0.44 50 135 50 50 20 per Figure 29; 10% to 90% per Figures 33 and 36; CL = 20pF per Figures 33 and 36; CL = 20pF per Figures 33 and 36; CL = 20pF per Figure 33; CL = 20pF fIN = 10MHz V.35 RECEIVER DC Parameters Inputs Sensitivity Source Impedance Short-Circuit Impedance AC Parameters Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate ±80 90 135 30 30 110 165 75 75 10 90 90 20 mV Ω Ω ns ns ns Mbps per Figure 30; ZS = V2/V1 x 50Ω per Figure 31 VCC = +5V for AC parameters per Figures 33 and 38; CL = 20pF per Figures 33 and 38; CL = 20pF per Figure 33; CL = 20pF per Figure 33; CL = 20pF fIN = 10MHz TRANSCEIVER LEAKAGE CURRENTS Driver Output 3-State Current Rcvr Output 3-State Current Rev: A Date:1/27/04 500 1 10 µA µA SP507 Multi–Mode Serial Transceiver 4 per Figure 32; Drivers disabled Mx = 111, 0.4V ≤ VO ≤ 2.4V © Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS TA = +25°C and VCC = +5.0V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.70 5.0 µs tPZH; Tri-state to Output HIGH 0.40 2.0 µs tPLZ; Output LOW to Tri-state 0.20 2.0 µs tPHZ; Output HIGH to Tri-state 0.40 2.0 µs RS-423/V.10 tPZL; Tri-state to Output LOW 0.15 2.0 µs tPZH; Tri-state to Output HIGH 0.20 2.0 µs tPLZ; Output LOW to Tri-state 0.20 2.0 µs tPHZ; Output HIGH to Tri-state 0.15 2.0 µs RS-422/V.11 tPZL; Tri-state to Output LOW 2.80 10.0 µs tPZH; Tri-state to Output HIGH 0.10 2.0 µs tPLZ; Output LOW to Tri-state 0.10 2.0 µs tPHZ; Output HIGH to Tri-state 0.10 2.0 µs V.35 tPZL; Tri-state to Output LOW 2.60 10.0 µs tPZH; Tri-state to Output HIGH 0.10 2.0 µs tPLZ; Output LOW to Tri-state 0.10 2.0 µs tPHZ; Output HIGH to Tri-state 0.15 2.0 µs CONDITIONS CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 15pF, Fig. 34 & 37; S1 closed CL = 15pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 15pF, Fig. 34 & 37; S1 closed CL = 15pF, Fig. 34 & 37; S2 closed RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.12 2.0 µs CL = 100pF, Fig. 35 & 38; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µs CL = 100pF, Fig. 35 & 38; S2 closed Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 5 © Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS (Continued) TA = +25°C and VCC = +5.0V unless otherwise noted. PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW MIN. TYP. MAX. UNITS 0.10 2.0 µs tPZH; Tri-state to Output HIGH 0.10 2.0 µs tPLZ; Output LOW to Tri-state 0.10 2.0 µs tPHZ; Output HIGH to Tri-state 0.10 2.0 µs V.35 tPZL; Tri-state to Output LOW 0.10 2.0 µs tPZH; Tri-state to Output HIGH 0.10 2.0 µs tPLZ; Output LOW to Tri-state 0.10 2.0 µs tPHZ; Output HIGH to Tri-state 0.10 2.0 µs CONDITIONS CL = 100pF, Fig. 35 & 39; S1 closed CL = 100pF, Fig. 35 & 39; S2 closed CL = 15pF, Fig. 35 & 39; S1 closed CL = 15pF, Fig. 35 & 39; S2 closed CL = 100pF, Fig. 35 & 39; S1 closed CL = 100pF, Fig. 35 & 39; S2 closed CL = 15pF, Fig. 35 & 39; S1 closed CL = 15pF, Fig. 35 & 39; S2 closed TRANSCEIVER TO TRANSCEIVER SKEW V.28 Driver 100 100 V.28 Receiver 20 20 V.11 Driver 2 2 V.11 Receiver 3 3 V.10 Driver 5 5 V.10 Receiver 5 5 (per Figures 33, 36, 38) ns [ (tphl )Tx1 – (tphl )Tx6,7 ] ns [ (tplh )Tx1 – (tplh )Tx6,7 ] ns [ (tphl )Rx1 – (tphl )Rx2,7 ] ns [ (tplh )Rx1 – (tphl )Rx2,7 ] ns [ (tphl )Tx1 – (tphl )Tx6,7 ] ns [ (tplh )Tx1 – (tplh )Tx6,7 ] ns [ (tphl )Rx1 – (tphl )Rx2,7 ] ns [ (tplh )Rx1 – (tphl )Rx2,7 ] ns [ (tphl )Tx2 – (tphl )Tx3,4,5 ] ns [ (tplh )Tx2 – (tplh )Tx3,4,5 ] ns [ (tphl )Rx2 – (tphl )Rx3,4,5 ] ns [ (tplh )Rx2 – (tphl )Rx3,4,5 ] V.35 Driver ns ns ns ns 4 4 6 6 V.35 Receiver [ (tphl )Tx1 – (tphl )Tx6,7 ] [ (tplh )Tx1 – (tplh )Tx6,7 ] [ (tphl )Rx1 – (tphl )Rx2,7 ] [ (tplh )Rx1 – (tphl )Rx2,7 ] POWER REQUIREMENTS PARAMETER VCC ICC (No Mode Selected) (V.28/RS-232) (V.11/X.21) (EIA-530 & RS-449) (V.35) Rev: A Date:1/27/04 MIN. TYP. MAX. UNITS 4.75 5.00 5.25 Volts 30 65 175 250 100 mA mA mA mA mA SP507 Multi–Mode Serial Transceiver 6 CONDITIONS All ICC values are with VCC = +5V fIN = 120kbps; Drivers active & loaded. fIN = 10Mbps; Drivers active & loaded. fIN = 10Mbps; Drivers active & loaded. V.35 @ fIN = 10Mbps, V.28 @ 120kbps; Drivers active & loaded. © Copyright 2004 Sipex Corporation TEST CIRCUITS A A VOC VT 3kΩ C C Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A VT 7kΩ Isc Oscilloscope C C Scope used for slew rate measurement. Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current VCC = 0V A A Ix 3kΩ 2500pF Oscilloscope ±2V C C Figure 6. V.28 Driver Output Rise/Fall Times Figure 5. V.28 Driver Output Power-Off Impedance Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 7 © Copyright 2004 Sipex Corporation A A Iia ±15V Voc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3.9kΩ VOC Vt 450Ω C C Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage VCC = 0V A A Ix ±0.25V Isc C C Figure 11. V.10 Driver Output Short-Circuit Current Rev: A Date:1/27/04 Figure 12. V.10 Driver Output Power-Off Current SP507 Multi–Mode Serial Transceiver 8 © Copyright 2004 Sipex Corporation A A Iia ±10V Oscilloscope 450Ω C C Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current V.10 RECEIVER A +3.25mA VOCA 3.9kΩ –10V VOC VOCB –3V B +3V +10V Maximum Input Current versus Voltage C –3.25mA Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 and V.35 Driver Output Open-Circuit Voltage A Isa A 50Ω VT 50Ω Isb B B VOS C C Figure 17. V.11 Driver Output Test Terminated Voltage Rev: A Date:1/27/04 Figure 18. V.11 Driver Output Short-Circuit Current SP507 Multi–Mode Serial Transceiver 9 © Copyright 2004 Sipex Corporation VCC = 0V A Iia A Ixa ±10V ±0.25V B B C C VCC = 0V A A ±0.25V ±10V Ixb Iib B B C C Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current V.11 RECEIVER +3.25mA A 50Ω Oscilloscope 50Ω B –10V 50Ω –3V VE +3V C +10V Maximum Input Current versus Voltage –3.25mA Figure 22. V.11 Receiver Input IV Graph Figure 21. V.11 Driver Output Rise/Fall Time Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 10 © Copyright 2004 Sipex Corporation V.11 RECEIVER w/ Optional Cable Termination (100Ω to 150Ω) i [mA] = V [V] / 0.1 A Iia i [mA] = (V [V] – 3) / 4.0 ±6V 100Ω to 150Ω –6V –3V +3V B +6V i [mA] = (V [V] – 3) / 4.0 C Maximum Input Current versus Voltage i [mA] = V [V] / 0.1 Figure 24. V.11 Receiver Input Graph w/ Termination A A ±6V 50Ω 100Ω to 150Ω VT 50Ω Iib B VOS B C C Figure 23. V.11 Receiver Input Current w/ Termination Figure 25. V.35 Driver Output Test Terminated Voltage V1 A A 50Ω 24kHz, 550mVp-p Sine Wave 50Ω V2 VT 50Ω B VOS B C C Figure 26. V.35 Driver Output Offset Voltage Rev: A Date:1/27/04 Figure 27. V.35 Driver Output Source Impedance SP507 Multi–Mode Serial Transceiver 11 © Copyright 2004 Sipex Corporation A A 50Ω Oscilloscope 50Ω ISC B B 50Ω ±2V C C Figure 29. V.35 Driver Output Rise/Fall Time Figure 28. V.35 Driver Output Short-Circuit Impedance A V1 A 50Ω 24kHz, 550mVp-p Sine Wave V2 Isc B B ±2V C C Figure 30. V.35 Receiver Input Source Impedance Figure 31. V.35 Receiver Input Short-Circuit Impedance Any one of the three conditions for disabling the driver. VCC = 0V 1 1 1 M2 M1 M0 CL1 A VCC IZSC TIN ±15V A A B B ROUT CL2 15pF fIN (50% Duty Cycle, 2.5VP-P) Logic “0” B Figure 33. Driver/Receiver Timing Test Circuit Figure 32. Driver Output Leakage Current Test Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 12 © Copyright 2004 Sipex Corporation Output Under Test VCC S1 500Ω VCC S1 CRL CL 1KΩ Test Point Receiver Output 1KΩ S2 S2 Figure 35. Receiver Timing Test Load Circuit Figure 34. Driver Timing Test Load Circuit f > 10MHz; tR < 10ns; tF < 10ns DRIVER INPUT DRIVER OUTPUT +3V 1.5V 0V A 1.5V tPLH VO 1/2VO 1/2VO B tDPLH DIFFERENTIAL OUTPUT VA – VB tPHL VO+ 0V VO– tDPHL tR tF tSKEW = | tDPLH - tDPHL | Figure 36. Driver Propagation Delays +3V 1.5V Mx or Tx_Enable 0V 1.5V tZL tLZ 5V 2.3V A, B VOL VOH A, B 2.3V 0V Output normally LOW 0.5V Output normally HIGH 0.5V tZH tHZ Figure 37. Driver Enable and Disable Times f > 10MHz; tR < 10ns; tF < 10ns V0D2+ 0V A–B 0V INPUT V0D2– OUTPUT VOH (VOH - VOL)/2 (VOH - VOL)/2 RECEIVER OUT VOL tPLH tPHL tSKEW = | tPHL - tPLH | Figure 38. Receiver Propagation Delays Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 13 © Copyright 2004 Sipex Corporation +3V 1.5V Mx or RCVR Enable 0V 1.5V tZL tLZ 5V 50% RECEIVER OUT VIL Output normally LOW 0.5V Output normally HIGH 0.5V VIH RECEIVER OUT 50% 0V tZH tHZ Figure 39. Receiver Enable and Disable Times +3V 1.5V 1.5V Mx or Tx_Enable 0V tLZ tZL 0V TOUT VOL Output LOW 0.5V 0.5V +3V 1.5V 1.5V Mx or Tx_Enable 0V tZH VOH TOUT 0V tHZ Output HIGH 0.5V 0.5V Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 14 © Copyright 2004 Sipex Corporation Figure 41. Typical V.28 Driver Output Waveform Figure 42. Typical V.10 Driver Output Waveform Figure 43. Typical V.11 Driver Output Waveforms Figure 44. Typical V.35 Driver Output Waveforms Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 15 © Copyright 2004 Sipex Corporation Pin 61 — SD(a) — Analog Out — Send data, inverted; sourced from TxD. Pin 63 — TT(a) — Analog Out — Terminal Timing, inverted; sourced from TxCE. 61 SD(a) 62 VCC 63 TT(a) 64 GND 65 TT(b) 66 CS(a) 67 CS(b) 68 DM(a) 69 DM(b) 70 RD(a) 71 RD(b) 72 GND 73 VCC 74 VCC 75 GND 76 SCT(a) 77 SCT(b) 78 DSR 79 DTE_ST 80 CTS PINOUT (QFP) RxD 1 Pin 65 — TT(b) — Analog Out — Terminal Timing, non–inverted; sourced from TxCE. 60 GND RTEN 2 59 SD(b) RREN 3 58 TR(a) TMEN 4 57 GND LLEN 5 56 TR(b) TTEN 6 55 VCC SCTEN 7 54 RS(a) LATCH 8 53 GND TERM_OFF 9 Pin 70 — RD(a) — Receive Data, analog input; inverted; source for RxD. 52 RS(b) M2 10 Pin 71 — RD(b) — Receive Data; analog input; non-inverted; source for RxD. 51 LL(a) SP507 M1 11 M0 12 DTR 13 50 GND 49 LL(b) 48 VCC Pin 76 — SCT(a) — Serial Clock Transmit; analog input, inverted; source for DCE_ST. Pin 77 — SCT(b) — Serial Clock Transmit: analog input, non–inverted; source for DCE_ST. TM(b) 40 TM(a) 39 RT(b) 38 RT(a) 37 RR(b) 36 RR(a) 35 GND 34 VCC 33 41 VCC VSS 32 42 ST(a) RxC 20 GND 29 C1– 30 C2– 31 DCD 19 VDD 27 C2+ 28 43 GND VCC 25 C1+ 26 44 ST(b) LL 24 45 RL(b) RLEN 18 TM 21 46 GND RL 17 STEN 23 47 RL(a) RTS 16 DCE_ST 22 TxD 14 TxCE 15 Pin 79 — DTE_ST — Serial Clock Transmit; TTL output; sources from SCT(a) and SCT(b) inputs. PIN ASSIGNMENTS CLOCK AND DATA GROUP Pin 1 — RxD — Receive Data; TTL output, sourced from RD(a) and RD(b) inputs. CONTROL LINE GROUP Pin 13 — DTR — Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs. Pin 14 — TxD — TTL input ; transmit data source for SD(a) and SD(b) outputs. Pin 16 — RTS — Ready To Send; TTL input; source for RS(a) and RS(b) outputs. Pin 15 — TxCE — Transmit Clock; TTL input for TT driver outputs. Pin 17 — RL — Remote Loopback; TTL input; source for RL(a) and RL(b) outputs. Pin 20 — RxC — Receive Clock; TTL output sourced from RT(a) and RT(b) inputs. Pin 19 — DCD— Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs. Pin 22 — DCE_ST — Send Timing; TTL input; source for ST(a) and ST(b) outputs. Pin 21 — TM — Ring In; TTL output; sourced from TM(a) and TM(b) inputs. Pin 37 — RT(a) — Receive Timing; analog input, inverted; source for RxC. Pin 24 — LL — Local Loopback; TTL input; source for LL(a) and LL(b) outputs. Pin 38 — RT(b) — Receive Timing; analog input, non-inverted; source for RxC. Pin 35 — RR(a)— Receiver Ready; analog input, inverted; source for DCD. Pin 42 — ST(a) — Send Timing; analog output, inverted; sourced from DCE_ST. Pin 36 — RR(b)— Receiver Ready; analog input, non-inverted; source for DCD. Pin 44 — ST(b) — Send Timing; analog output, non-inverted; sourced from DCE_ST. Pin 39 — TM(a)— Incoming Call; analog input, inverted; source for TM. Pin 59 — SD(b) — Analog Out — Send data, non-inverted; sourced from TxD. Pin 40 — TM(b)— Incoming Call; analog input, non-inverted; source for TM. Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 16 © Copyright 2004 Sipex Corporation Pin 45 — RL(b) — Remote Loopback; analog output, non-inverted; sourced from RL. Pin 7 — SCTEN — Enables DTE_ST receiver; active low; TTL input. Pin 47 — RL(a) — Remote Loopback; analog output inverted; sourced from RL. Pin 8 — LATCH — Latch control for decoder bits (pins 10-12), active low. Logic high input will make decoder transparent. Pin 49— LL(b) — Local Loopback; analog output, non-inverted; sourced from LL. Pin 9 — TERM_OFF — Disables receiver termination networks for RxD, RxC, and DTE_ST; TTL input. Pin 51 — LL(a) — Local Loopback; analog output, inverted; sourced from LL. Pin 52 — RS(b) — Ready To Send; analog output, non-inverted; sourced from RTS. Pins 10,11, 12 — M2, M1, M0 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs. Pin 54 — RS(a) — Ready To Send; analog output, inverted; sourced from RTS. Pin 18 — RLEN — Enables RL driver; active high; TTL input. Pin 56 — TR(b) — Terminal Ready; analog output, non-inverted; sourced from DTR. Pin 23 — STEN — Enables DTE_ST driver; active high; TTL input. Pin 58 — TR(a) — Terminal Ready; analog output, inverted; sourced from DTR. Pin 66 — CS(a)— Clear To Send; analog input, inverted; source for CTS. POWER SUPPLIES Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC — +5V input. Pin 67 — CS(b)— Clear To Send; analog input, non-inverted; source for CTS. Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 — GND — Ground. Pin 68 — DM(a)— Data Mode; analog input, inverted; source for DSR. Pin 27 — VDD +10V Charge Pump Capacitor — Connects from V DD to V CC . Suggested capacitor size is 22µF, 16V. Pin 69 — DM(b)— Data Mode; analog input, non-inverted; source for DSR Pin 32 — VSS –10V Charge Pump Capacitor — Connects from ground to V SS. Suggested capacitor size is 22µF, 16V. Pin 78 — DSR— Data Set Ready; TTL output; sourced from DM(a) and DM(b) inputs. Pins 26 and 30 — C1+ and C1– — Charge Pump Capacitor — Connects from C1+ to C1–. Suggested capacitor size is 22µF, 16V. Pin 80 — CTS— Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs. Pins 28 and 31 — C2+ and C2– — Charge Pump Capacitor — Connects from C2+ to C2–. Suggested capacitor size is 22µF, 16V. CONTROL REGISTERS Pin 2 — RTEN — Enables RxC receiver, active low; TTL input. Pin 3 — RREN — Enables DCD receiver, active low; TTL input. Pin 4 — TMEN — Enables TM receiver, active high; TTL input. Pin 5 — LLEN — Enables LL driver, active low; TTL input. Pin 6 — TTEN — Enables TxCE driver, active high; TTL input. Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 17 © Copyright 2004 Sipex Corporation 1N5819 22µF (SEE PINOUT FOR VCC PINS) 22µF 22µF +5V 25 10µF VCC 27 26 30 28 VDD C1+ C1- C2+ Charge Pump 31 C2VSS 32 22µF 14 TxD RD(a) 70 61 SD(a) A RxD 1 B RD(b) 71 RT(a) 37 59 SD(b) 13 DTR RxC 20 58 TR(a) A 56 TR(b) RTEN 2 RT(b) 38 16 RTS CS(a) 66 54 RS(a) CTS 80 52 RS(b) CS(b) 67 17 RL DM(a) 68 47 RL(a) DSR 78 45 RL(b) DM(b) 69 18 RLEN RR(a) 35 24 LL 51 LL(a) DCD 19 49 LL(b) RREN 3 RR(b) 36 5 LLEN 22 DCE_ST TM(a) 39 42 ST(a) B TM 21 23 STEN TMEN 4 TM(b) 40 15 TxCE SCT(a) 76 63 TT(a) DTE_ST 79 B A M0 12 LATCH 8 65 TT(b) 6 TTEN 9 TERM_OFF X A — Receiver Tri-State circuitry, V.11, & V.35 termination resistor circuitry (RxD, RxC & DTE_ST). MODE M1 11 DECODER LATCH SCTEN 7 SCT(b) 77 M2 10 44 ST(b) SP507 B — Driver Tri-State circuitry & V.35 termination circuitry (TxD, TxCE & DCE_ST). (SEE PINOUT ASSIGNMENTS FOR GROUND PINS) Figure 45. Typical Operating Circuit Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 18 © Copyright 2004 Sipex Corporation SP507 Driver Mode Selection Mode V.11 EIA-530A EIA-530 X.21 V.35 RS-449 RS-232 M2 - M0 111 000 001 010 011 100 101 110 SD(a) 3-state V.11- V.11- V.11- V.11- V.35- SD(b) 3-state V.11+ V.11+ V.11+ V.11+ V.35+ TR(a) 3-state V.11- V.10 V.11- V.11- V.28 V.11- V.28 TR(b) 3-state V.11+ 3-state V.11+ V.11+ 3-state V.11+ 3-state RS(a) 3-state V.11- V.11- V.11- V.11- V.28 V.11- V.28 RS(b) 3-state V.11+ V.11+ V.11+ V.11+ 3-state V.11+ 3-state RL(a) 3-state V.11- V.11- V.11- V.11- V.28 V.11- V.28 RL(b) 3-state V.11+ V.11+ V.11+ V.11+ 3-state V.11+ 3-state LL(a) 3-state V.10 V.10 V.10 V.10 V.28 V.10 V.28 LL(b) 3-state 3-state 3-state 3-state 3-state 3-state 3-state 3-state ST(a) 3-state V.11- V.11- V.11- V.11- V.35- ST(b) 3-state V.11+ V.11+ V.11+ V.11+ V.35+ TT(a) 3-state V.11- V.11- V.11- V.11- V.35- TT(b) 3-state V.11+ V.11+ V.11+ V.11+ V.35+ V.35 V.35 V.35 Pin Label V.11- V.28 V.11+ 3-state V.11- V.28 V.11+ 3-state V.11- V.28 V.11+ 3-state Table 1. SP507 Driver Decoder Table SP507 Receiver Mode Selection RS-232 X.21 V.35 RS-449 001 010 011 100 101 RD(a) >10kΩ to GND V.11- RD(b) >10kΩ to GND V.11+ RT(a) >10kΩ to GND V.11- RT(b) >10kΩ to GND V.11+ CS(a) >10kΩ to GND V.11- V.11- V.11- V.11- V.28 V.11- V.28 CS(b) >10kΩ to GND V.11+ V.11+ V.11+ V.11+ >10kΩ to GND V.11+ >10kΩ to GND DM(a) >10kΩ to GND V.11- V.10 V.11- V.11- V.28 V.11- V.28 DM(b) >10kΩ to GND V.11+ >10kΩ to GND V.11+ V.11+ >10kΩ to GND V.11+ >10kΩ to GND RR(a) >10kΩ to GND V.11- V.11- V.11- V.11- V.28 V.11- V.28 RR(b) >10kΩ to GND V.11+ V.11+ V.11+ V.11+ >10kΩ to GND V.11+ >10kΩ to GND V.10 V.10 >10kΩ to GND V.11V.11+ >10kΩ to GND >10kΩ to GND V.11V.11+ V.11V.11+ V.35V.35+ V.11V.11+ 120Ω V.11+ 110 120Ω V.35+ V.35 V.11+ 120Ω 120Ω 120Ω V.11+ V.11- V.11+ V.11- V.28 >10kΩ to GND V.28 >10kΩ to GND V.10 V.28 V.10 V.28 >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND V.11- V.35- V.11+ V.35+ V.11V.11+ 120Ω >10kΩ to GND SCT(b) V.11- V.35- V.35 SCT(a) V.11+ V.11+ V.11- 120Ω >10kΩ to GND V.11- V.11- 120Ω V.10 >10kΩ to GND V.11+ 120Ω 120Ω >10kΩ to GND 120Ω TM(a) TM(b) V.11- V.35 EIA-530 000 120Ω EIA-530A 111 120Ω V.11 M2 - M0 120Ω Mode 120Ω Pin Label V.28 >10kΩ to GND Table 2. SP507 Receiver Decoder Table Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 19 © Copyright 2004 Sipex Corporation MODE: V.11 DRIVER/RECEIVER M2 M1 M0 0 0 0 14 TxD RD(a) 70 61 SD(a) 120Ω RxD 1 59 SD(b) RD(b) 71 RT(a) 37 120Ω RxC 20 13 DTR 58 TR(a) 56 TR(b) RTEN 2 RT(b) 38 16 RTS CS(a) 66 54 RS(a) CTS 80 52 RS(b) CS(b) 67 17 RL DM(a) 68 47 RL(a) DSR 78 45 RL(b) DM(b) 69 RR(a) 35 18 RLEN 24 LL DCD 19 51 LL(a) RREN 3 RR(b) 36 TM(a) 39 5 LLEN 22 DCE_ST 42 ST(a) TM 21 44 ST(b) TMEN 4 23 STEN SCT(a) 76 63 TT(a) 120Ω DTE_ST 79 15 TxCE 65 TT(b) SCTEN 7 SCT(b) 77 6 TTEN RECEIVERS DRIVERS Figure 46. Mode Diagram – V.11 Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 20 © Copyright 2004 Sipex Corporation MODE: EIA-530A DRIVER/RECEIVER M2 M1 M0 0 0 1 14 TxD RD(a) 70 61 SD(a) 120Ω RxD 1 59 SD(b) RD(b) 71 RT(a) 37 120Ω RxC 20 13 DTR 58 TR(a) RTEN 2 RT(b) 38 16 RTS CS(a) 66 54 RS(a) CTS 80 52 RS(b) CS(b) 67 17 RL DM(a) 68 47 RL(a) DSR 78 45 RL(b) 18 RLEN RR(a) 35 24 LL DCD 19 51 LL(a) RREN 3 RR(b) 36 TM(a) 39 5 LLEN 22 DCE_ST 42 ST(a) TM 21 44 ST(b) TMEN 4 23 STEN SCT(a) 76 63 TT(a) 120Ω DTE_ST 79 15 TxCE 65 TT(b) SCTEN 7 SCT(b) 77 6 TTEN RECEIVERS DRIVERS Figure 47. Mode Diagram – EIA-530A Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 21 © Copyright 2004 Sipex Corporation MODE: EIA-530 DRIVER/RECEIVER M2 M1 M0 0 1 0 14 TxD RD(a) 70 61 SD(a) 120Ω RxD 1 59 SD(b) RD(b) 71 RT(a) 37 120Ω RxC 20 13 DTR 58 TR(a) 56 TR(b) RTEN 2 RT(b) 38 16 RTS CS(a) 66 54 RS(a) CTS 80 52 RS(b) CS(b) 67 17 RL DM(a) 68 47 RL(a) DSR 78 45 RL(b) DM(b) 69 RR(a) 35 18 RLEN 24 LL DCD 19 51 LL(a) RREN 3 RR(b) 36 TM(a) 39 5 LLEN 22 DCE_ST 42 ST(a) TM 21 44 ST(b) TMEN 4 23 STEN SCT(a) 76 63 TT(a) 120Ω DTE_ST 79 15 TxCE 65 TT(b) SCTEN 7 SCT(b) 77 6 TTEN RECEIVERS DRIVERS Figure 48. Mode Diagram – EIA-530 Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 22 © Copyright 2004 Sipex Corporation MODE: X.21 DRIVER/RECEIVER M2 M1 M0 0 1 1 14 TxD RD(a) 70 61 SD(a) 120Ω RxD 1 59 SD(b) RD(b) 71 RT(a) 37 120Ω RxC 20 13 DTR 58 TR(a) 56 TR(b) RTEN 2 RT(b) 38 16 RTS CS(a) 66 54 RS(a) CTS 80 52 RS(b) CS(b) 67 17 RL DM(a) 68 47 RL(a) DSR 78 45 RL(b) DM(b) 69 RR(a) 35 18 RLEN 24 LL DCD 19 51 LL(a) RREN 3 RR(b) 36 TM(a) 39 5 LLEN 22 DCE_ST 42 ST(a) TM 21 44 ST(b) TMEN 4 23 STEN SCT(a) 76 63 TT(a) 120Ω DTE_ST 79 15 TxCE 65 TT(b) SCTEN 7 SCT(b) 77 6 TTEN RECEIVERS DRIVERS Figure 49. Mode Diagram – X.21 Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 23 © Copyright 2004 Sipex Corporation MODE: V.35 DRIVER/RECEIVER M2 M1 M0 1 0 0 V.35 Ntwk RxD 1 14 TxD V.35 Ntwk RD(a) 70 RD(b) 71 RT(a) 37 59 SD(b) 13 DTR V.35 Ntwk RxC 20 61 SD(a) 58 TR(a) RTEN 2 RT(b) 38 16 RTS CS(a) 66 CTS 80 54 RS(a) 17 RL DM(a) 68 47 RL(a) DSR 78 18 RLEN RR(a) 35 24 LL DCD 19 51 LL(a) RREN 3 5 LLEN TM(a) 39 V.35 Ntwk 22 DCE_ST TM 21 TMEN 4 44 ST(b) 23 STEN SCT(a) 76 15 TxCE V.35 Ntwk V.35 Ntwk DTE_ST 79 42 ST(a) SCTEN 7 SCT(b) 77 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 50. Mode Diagram – V.35 Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 24 © Copyright 2004 Sipex Corporation MODE: RS-449 DRIVER/RECEIVER M2 M1 M0 1 0 1 14 TxD RD(a) 70 61 SD(a) 120Ω RxD 1 59 SD(b) RD(b) 71 RT(a) 37 120Ω RxC 20 13 DTR 58 TR(a) 56 TR(b) RTEN 2 RT(b) 38 16 RTS CS(a) 66 54 RS(a) CTS 80 52 RS(b) CS(b) 67 17 RL DM(a) 68 47 RL(a) DSR 78 45 RL(b) DM(b) 69 RR(a) 35 18 RLEN 24 LL DCD 19 51 LL(a) RREN 3 RR(b) 36 TM(a) 39 5 LLEN 22 DCE_ST 42 ST(a) TM 21 44 ST(b) TMEN 4 23 STEN SCT(a) 76 63 TT(a) 120Ω DTE_ST 79 15 TxCE 65 TT(b) SCTEN 7 SCT(b) 77 6 TTEN RECEIVERS DRIVERS Figure 51. Mode Diagram – RS-449 Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 25 © Copyright 2004 Sipex Corporation MODE: RS-232 (V.28) DRIVER/RECEIVER M2 M1 M0 1 1 0 14 TxD RD(a) 70 RxD 1 61 SD(a) RT(a) 37 13 DTR RxC 20 58 TR(a) RTEN 2 16 RTS CS(a) 66 CTS 80 54 RS(a) 17 RL DM(a) 68 47 RL(a) DSR 78 18 RLEN RR(a) 35 24 LL DCD 19 51 LL(a) RREN 3 5 LLEN 22 DCE_ST TM(a) 39 TM 21 42 ST(a) TMEN 4 23 STEN SCT(a) 76 15 TxCE DTE_ST 79 63 TT(a) SCTEN 7 6 TTEN RECEIVERS DRIVERS Figure 52. Mode Diagram – RS-232 Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 26 © Copyright 2004 Sipex Corporation PACKAGE: 80 PIN MQFP D D1 D2 0.30" RAD. TYP. PIN 1 c 0.20" RAD. TYP. E1 E E2 CL 5°-16° 0° MIN. 0°–7° 5°-16° CL L L1 A2 A b A1 e DIMENSIONS Minimum/Maximum (mm) SYMBOL Seating Plane 80–PIN MQFP JEDEC MS-22 (BEC) Variation MIN NOM A COMMON DIMENTIONS MAX SYMBL MIN 2.45 A1 0.00 A2 1.80 b 0.22 2.00 c 0.11 0.25 L 0.73 2.20 L1 NOM MAX 23.00 0.88 1.03 1.60 BASIC 0.40 D 17.20 BSC D1 14.00 BSC D2 12.35 REF E 17.20 BSC E1 14.00 BSC E2 12.35 REF e 0.65 BSC N 80 80 PIN MQFP (MS-022 BC) Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 27 © Copyright 2004 Sipex Corporation ORDERING INFORMATION Model Temperature Range Package Types SP507CF ........................................................................... 0°C to +70°C ...................................................... 80–pin JEDEC (BE-2 Outline) MQFP Please consult the factory for pricing and availability on a Tape-On-Reel option. REVISION HISTORY DATE 1/27/04 REVISION A DESCRIPTION Implemented tracking revision. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Rev: A Date:1/27/04 SP507 Multi–Mode Serial Transceiver 28 © Copyright 2004 Sipex Corporation