PCA2125 SPI Real time clock / calendar Rev. 00.11 — 30 January 2007 Preliminary data sheet 1. Product profile 1.1 General description The PCA2125 is a CMOS real time clock/calendar optimized for low power consumption and 125 °C operation. Data is transferred serially via an SPI bus with a maximum data rate of 8.0 Mbits/s. An alarm and timer function are also available with possibility to generate a wake-up signal on an interrupt pin. 1.2 Features Provides year, month, day, weekday, hours, minutes and seconds based on 32.768 kHz quartz crystal Resolution: seconds - years Clock operating voltage: 1.2 to 5.5 V Low backup current; typical 0.55 μA at VDD = 3.0 V and Tamb = 25 °C 3 line SPI with separate combinable data input and output Serial interface (at VDD = 1.8 to 5.5 V) 1 second or 1 minute interrupt output Freely programmable timer with interrupt capability Freely programmable alarm function with interrupt capability Integrated oscillator capacitor Internal power-on reset Open-drain interrupt pin 1.3 Applications Automotive time keeping application Metering 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage SPI bus inactive; Tamb = 25 °C 1.2 - 5.5 V SPI bus active; Tamb = −40 to +125 °C 1.6 - 5.5 V PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit IDD supply current fSCL = 7.0 MHz - - 800 μA fSCL = 1.0 MHz - - 200 μA VDD = 5 V - 550 725 nA VDD = 2 V - 550 725 nA operating −40 - +125 °C −65 - +150 °C SPI bus inactive and CLKOUT disabled; fSCL = 0 kHz; Tamb = 25 °C Tamb ambient temperature Tstg storage temperature 2. Pinning information 2.1 Pinning OSCI 1 14 VDD OSCO 2 13 CLKOUT n.c. 3 n.c. 4 INT 5 10 SCL CE 6 9 SDI VSS 7 8 SDO 12 n.c. PCA2125 11 n.c. 001aaf892 Fig 1. Pin configuration TSSOP14 2.2 Pin description Table 2. Pin description PCA2125 Symbol Pin Description OSCI 1 oscillator input OSCO 2 oscillator output nc 3 Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. nc 4 Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. INT 5 interrupt output (open-drain; active LOW). When not used, must be connected to VSS or pulled high via a resistor. CE 6 chip enable input (active HIGH) with 200 kΩ pull down. VSS 7 ground SDO 8 serial data output, push-pull SDI 9 serial data input. May float when CE inactive. SCL 10 serial clock input. May float when CE inactive. nc 11 Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 2 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 2. Pin description PCA2125 Symbol Pin Description nc 12 Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. CLKOUT 13 clock output (open drain) VDD 14 positive supply voltage 3. Ordering information Table 3. Ordering information Type number Topside mark Package PCA2125TS TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4mm PCA2125 Name Description PCA2125_00 Preliminary data sheet Version SOT402-1 © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 3 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 4. Block diagram INT 5 OSCI OSCO CLKOUT VSS VDD CONTROL 1 0 CONTROL 2 1 SECONDS 2 MINUTES 3 13 HOURS 4 7 DAYS 5 WEEKDAYS 6 MONTHS 7 YEARS 8 MINUTE ALARM 9 HOUR ALARM A DAY ALARM B WEEKDAY ALARM C CLOCKOUT CONTROL D TIMER CONTROL E COUNTDOWN TIMER F 1 2 DIVIDER AND TIMER OSCILLATOR 32.768 kHz 14 OSCILLATOR MONITOR SCL SDO SDI CE 1 Hz POR CONTROL LOGIC 10 8 9 SERIAL BUS INTERFACE ADDRESS REGISTER 6 200 kΩ 001aaf894 Fig 2. Block diagram of PCA2125 5. Device protection diagram VDD OSCI CLKOUT OSCO SCL INT SDI CE SDO VSS PCA2125 001aaf895 Fig 3. Device diode protection diagram PCA2125 PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 4 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6. Functional description The PCA2125 contains sixteen 8-bit registers with an auto-incrementing address register, and on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, and an 8 MHz SPI. All sixteen registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00H and 01H) are used as control registers. The memory addresses 02H through 08H are used as counters for the clock function (seconds up to years). Addresses 09H through 0CH define the alarm condition, whilst address 0DH defines the clock out mode. The seconds, minutes, hours, days, weekdays, months and years registers are all coded in BCD format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented. Address registers 0EH and 0FH are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1ms to more than 4hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute, but these are defined at address 01H. Table 4: Countdown timer durations Timer source clock minimum timer duration maximum timer duration 4096 Hz 244 μs 62.256 ms 64 Hz 15.625 ms 3.984 s 1 Hz 1s 255 s 1⁄60 Hz 60 s 4 hrs 15 minutes PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 5 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.1 Register overview 16 registers are available. The time registers are encoded in the binary coded decimal format (BCD) to simplify application use. Other registers are either bit-wise or standard binary. Table 5: Registers overview Bit positions labelled as x are not implemented and will return a 0 when read. Bit positions labelled with 0 should always be written with logic 0. Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00HEX control 1 ext test 0 stop 0 POR ovrd 12/24 0 0 01HEX control 2 MI SI MSF TI/TP AF TF AIE TIE 02HEX seconds RF 10 seconds seconds 03HEX minutes x 10 minutes minutes 04HEX hours x x AMPM / 10 hours hours 05HEX days x x 10 days days 06HEX weekdays x x x x 07HEX months x x x 10months 08HEX years 09HEX minute alarm AEn 0AHEX hour alarm AEn x AMPM / 10 hour alarm hour alarm 0BHEX day alarm AEn x 10 day alarm day alarm 0CHEX weekday alarm AEn x x x x 0DHEX CLKOUT control x x x x x COF2 COF1 COF0 0EHEX timer control TE x x x x x CTD1 CTD0 0FHEX countdown timer weekdays months 10 years years 10 minute alarm minute alarm weekday alarm countdown timer value, n PCA2125_00 Preliminary data sheet x © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 6 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.2 Reset The PCA2125 includes an internal reset circuit (see Figure 4) which is active whenever the oscillator is stopped. The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-up and stable crystal resonance. This time may be in the range of 200ms to 2s depending on crystal type, temperature and supply voltage. Whenever an internal reset occurs, the RF flag is set. chip in reset chip not in reset VDD oscillation internal reset t 001aaf897 Fig 4. Power on reset The SPI interface is initialized whenever the chip enable line CE is inactive. Table 6: Register reset value Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00HEX control 1 0 0 0 - 1 0 0 0 01HEX control 2 0 0 0 0 0 0 0 0 02HEX seconds 1 x x x x x x x 03HEX minutes - x x x x x x x 04HEX hours - - x x x x x x 05HEX days - - x x x x x x 06HEX weekdays - - - - - x x x 07HEX months - - - x x x x x 08HEX years x x x x x x x x 09HEX minute alarm 1 x x x x x x x 0AHEX hour alarm 1 - x x x x x x 0BHEX day alarm 1 - x x x x x x 0CHEX weekday alarm 1 - - - - x x x 0DHEX CLKOUT control - - - - - 0 0 0 0EHEX timer control 0 - - - - - 1 1 0FHEX countdown timer x x x x x x x x [1] registers marked ‘x’ are undefined at power up and unchanged by subsequent resets. [2] registers marked ‘-’ are not implemented. After reset, the following mode is entered: 32768Hz CLKOUT active PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 7 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Power on reset override available to be set 24 hour mode is selected 6.2.1 Power-On Reset (POR) override The power on reset duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device (see Figure 5). OSCILLATOR SDI CE osc stopped 0 = stopped, 1 = running POR OVERRIDE reset 0 = override inactive 1 = override active CLEAR POR_OVRD REGISTER 0 = clear override mode 1 = override possible 001aaf898 Fig 5. Reset system. The setting of this mode requires that the ‘POR ovrd’ register be set to ‘1’ and that the SPI bus pins, SDI and CE, be toggled in a specific order as shown in Figure 6. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and set-up operation may commence i.e. entry into the external clock test mode via the SPI bus access. The override mode may be cleared by writing a logic 0 to ‘POR ovrd’. ‘POR ovrd’ must be set to logic 1 before re-entry into the override mode is possible. Setting ‘POR ovrd’ to logic 0 during normal operation has no effect except to prevent accidental entry into the POR override mode. This is the recommended setting. minimum 500 ns SDI CE reset override minimum 500 ns minimum 2000 ns POR override set at this time 001aaf900 Fig 6. POR override sequence. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 8 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.3 Control registers 6.3.1 Control 1 register Table 7. Control 1 (address 00HEX) bits description Bit Symbol Value Description Section 7 ext test 0 normal mode Section 6.9 1 external clock test mode 0 Reserved for future use. 0 RTC source clock runs 1 RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768, 16.384 or 8.192 kHz is still available) 0 Reserved for future use. 0 Power-on reset override facility is disabled; set to logic 0 for normal operation 1 Power-on reset override may be enabled 0 24 hour mode is selected 1 12 hour mode is selected 0 0 Reserved for future use. 6 5 stop 4 3 POR ovrd 2 12/24 1 to 0 Section 6.10 Section 6.2.1 Table 15 6.3.2 Control 2 register Table 8. Control 2 (address 01HEX) bits description Bit Symbol Value Description Section 7 MI 0 Minute interrupt is disabled Section 6.6.1 1 Minute interrupt is enabled 6 SI 0 Second interrupt is disabled 1 Second interrupt is enabled 0 No minute or second interrupt generated 1 Flag set when minute or second interrupt generated. Flag must be cleared to clear interrupt. 0 No countdown timer interrupt generated 1 Flag set when countdown timer interrupt generated. Flag must be cleared to clear interrupt. 0 Interrupt pin follows timer flags 1 Interrupt pin generates a pulse 0 No alarm interrupt generated 1 Flag set when alarm triggered. Flag must be cleared to clear interrupt. 0 No interrupt generated from the alarm flag 1 Interrupt generated when alarm flag set 0 No interrupt generated from the countdown timer flag 1 Interrupt generated when countdown timer flag set 5 2 4 3 1 0 MSF TF TI/TP AF AIE TIE PCA2125_00 Preliminary data sheet Section 6.6 Section 6.7.2 Section 6.5.1 Section 6.7.3 Section 6.7 © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 9 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.4 Time and date function The majority of these registers are coded in the Binary Coded Decimal format. BCD is used to simplify application use. An example is shown for the minutes register: Table 9: BCD example Minutes value in decimal Bit 7 23 Bit 6 22 Bit 5 21 Bit 4 20 Bit 3 23 Bit 2 22 Bit 1 21 Bit 0 20 00 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 1 02 0 0 0 0 0 0 1 0 09 0 0 0 0 1 0 0 1 10 0 0 0 1 0 0 0 0 58 0 1 0 1 1 0 0 0 59 0 1 0 1 1 0 0 1 : : Table 10. Seconds / RF (address 02HEX) bits description Bit Symbol Value Description 7 RF 0 clock integrity is guaranteed 1 clock integrity is not guaranteed. Chip reset has occurred since flag was last cleared 00 to 59 this register holds the current seconds coded in BCD format; 6 to 0 Table 11. seconds Minutes (address 03HEX) bits description Bit Symbol Value Description 6 to 0 minutes 00 to 59 this register holds the current minutes coded in BCD format Table 12. Bit Hours (address 04HEX) bits description Symbol Value 12 hour mode 5 AMPM 4 to 0 hours 0 Indicates AM 1 Indicates PM 00 to012 this register holds the current hours coded in BCD format for 12 hour mode [1] 24 hour mode 5 to 0 [1] hours Description [1] 00 to 23 this register holds the current hours coded in BCD format for 24 hour mode Hour mode is set by the 12 / 24 bit in control register 2. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 10 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 13. Days (address 05HEX) bits description Bit Symbol 5 to 0 [1] days 01 to 31 Description [1] this register holds the current day coded in BCD format The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. Table 14. Weekdays (address 06HEX) bits description Bit Symbol 2 to 0 [1] Value weekdays Value 0 to 6 Description [1] this register holds the current weekday, see Table 15 These bits may be re-assigned by the user. Although the association of the weekdays counter to the actual weekday is arbitrary, the PCA2125 will assume ‘Sunday’ is 000 and ‘Monday’ is 001 for the purposes of determining the increment for calendar weeks. Table 15: Weekday assignments Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sunday x x x x x 0 0 0 Monday x x x x x 0 0 1 Tuesday x x x x x 0 1 0 Wednesday x x x x x 0 1 1 Thursday x x x x x 1 0 0 Friday x x x x x 1 0 1 Saturday x x x x x 1 1 0 Table 16. Months (address 07HEX) bits description Bit Symbol Value Description 4 to 0 month 01 to 12 this register holds the current month coded in BCD format, see Table 17 Table 17: Month assignments Month Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January x x x 0 0 0 0 1 February x x x 0 0 0 1 0 March x x x 0 0 0 1 1 April x x x 0 0 1 0 0 May x x x 0 0 1 0 1 June x x x 0 0 1 1 0 July x x x 0 0 1 1 1 August x x x 0 1 0 0 0 September x x x 0 1 0 0 1 October x x x 1 0 0 0 0 November x x x 1 0 0 0 1 December x x x 1 0 0 1 0 PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 11 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 18. Years (address 08HEX) bits description Bit Symbol Value Description 7 to 0 years 00 to 99 this register holds the current year coded in BCD format 6.4.1 Data flow Figure 7 shows the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES 12/24 hour mode HOURS DAYS WEEK DAY MONTHS YEARS 001aaf901 Fig 7. Data flow for the time function 6.5 Alarm function When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable not (AEn) is logic 0, then that information will be compared with the current minute, hour, day and weekday. Table 19. Minute alarm (address 09HEX) bits description Bit Symbol Value Description 7 AEn 0 minute alarm is enabled 1 minute alarm is disabled 00 to 59 this register holds the minute alarm information coded in BCD format 6 to 0 Table 20. minute alarm Hour alarm (address 0AHEX) bits description Bit Symbol Value Description 7 AEn 0 hour alarm is enabled 1 hour alarm is disabled 24 hour mode PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 12 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 20. Hour alarm (address 0AHEX) bits description Bit Symbol Value Description 5 to 0 hour alarm 00 to 23 this register holds the hour alarm information coded in BCD format when in 24 hour mode. this register holds the hour alarm information coded in BCD format when in 12 hour mode 12 hour mode 5 am/pm alarm 0 to 1 4 to 0 hour alarm 00 to 11 Table 21. Day alarm (address 0BHEX) bits description Bit Symbol 7 AEn 5 to 0 Table 22. day alarm Value Description 0 day alarm is enabled 1 day alarm is disabled 01 to 31 this register holds the day alarm information coded in BCD format Weekday alarm (address 0CHEX) bits description Bit Symbol Value Description 7 AEn 0 weekday alarm is enabled 1 weekday alarm is disabled 2 to 0 weekday 0 to 6 alarm this register holds the weekday alarm information check now signal MINUTE AEN E.G. MINUTE AEN1 MINUTE ALARM = 1 0 MINUTE TIME HOUR AEN HOUR ALARM = HOUR TIME set alarm flag, AF DAY AEN DAY ALARM = DAY TIME WEEKDAY AEN WEEKDAY ALARM = 001aaf902 WEEKDAY TIME Fig 8. Alarm function block diagram PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 13 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Generation of interrupts from the alarm function is described under the interrupt section, Section 6.7.3. 6.5.1 Alarm flag When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AEn at logic 1 are ignored. Figure 9 shows an example for clearing AF but leaving MSF and TF unaffected. Clearing the flags is made by a write command, therefore bits 7,6,4,1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. minutes counter 44 minute alarm 45 46 45 AF INT when AIE = 1 001aaf903 Example where only the minute alarm is used and no other interrupts are enabled. Fig 9. AF timing To prevent the timer flags being overwritten while clearing AF, a logic AND is performed during a write access. Writing a ‘1’ will cause the flag to maintain it’s value, whilst writing a ‘0’ will cause the flag to be reset. Table 23: Flag location in control 2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control 2 - - MSF - AF TF - - The following tables show what instruction must be sent to clear the AF. In this example, MSF and TF are unaffected. Table 24: Example to clear only TF (bit 2) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control 2 - - 1 - 0 1 - - PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 14 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.6 Timer functions The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1ms to more than 4hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. Address registers 01HEX, 0EHEX and 0FHEX are used to control the timer function and output. Table 25. Control 2 (address 01HEX) bits description Bit Symbol Value Description 7 MI 0 Minute interrupt is disabled 1 Minute interrupt is enabled 0 Second interrupt is disabled 1 Second interrupt is enabled 0 No minute or second interrupt generated 1 Flag set when minute or second interrupt generated. Flag must be cleared to release INT. 6 5 4 2 0 SI MSF TI/TP TF TIE 0 Interrupt pin follows timer flags 1 Interrupt pin generates a pulse 0 No countdown timer interrupt generated 1 Flag set when countdown timer interrupt generated. Flag must be cleared to release INT. 0 No interrupt generated from the countdown timer flag 1 Interrupt generated when countdown timer flag set 3 AF See Table 8. 1 AIE See Table 8. Table 26. Timer control (address 0EHEX) bits description Bit Symbol 6:2 0 7 TE 1 to 0 Value Description Section Reserved for future use. CDT 0 Countdown timer is disabled 1 Countdown timer is enabled 0 0 4096 Hz countdown timer source clock 0 1 64 Hz countdown timer source clock 1 0 1 Hz countdown timer source clock 1 1 1⁄60 Hz countdown timer source clock Section 6.6.2 Table 27. Countdown timer (address 0AHEX) bits description Bit Symbol Value Description Section 7 to 0 n 00 to FF countdown value = n; Section 6.6.2 n CountdownPeriod = --------------------------------------------------------------SourceClockFrequency PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 15 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.6.1 Second and minute interrupt; SI, MI The minute and second interrupt are pre-defined timers for generating periodic interrupts. The timers can be enabled independently from one another, however a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Figure 10. seconds counter 58 59 minutes counter 59 00 11 12 00 01 INT when SI enabled MSF when SI enabled INT when only MI enabled MSF when only MI enabled 001aaf905 In this example, TI/TP is set to 1 resulting in 1/64 Hz wide interrupt pulse and the MSF flag is not cleared after an interrupt. Fig 10. INT example for SI and MI Table 28. Effect of MI and SI on INT generation Minute interrupt, MI Second interrupt, SI Result disabled disabled No interrupt generated enabled disabled An interrupt once per minute disabled enabled An interrupt once per second enabled enabled An interrupt once per second The minute/second flag, MSF, is set to ‘1’ when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface. The status of the MSF does not affect INT pulse generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT pulse will still be generated. The purpose of the flag is to allow the controlling system to interrogate the PCA2125 and identify the source of the interrupt i.e. minute/second or countdown timer. Table 29: Effect of MI and SI on MSF Minute interrupt, MI Second interrupt, SI Result disabled disabled MSF never set. enabled disabled MSF set when minutes counter increments disabled enabled MSF set when seconds counter increments enabled enabled MSF set when seconds counter increments PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 16 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.6.2 Countdown timer function The 8-bit countdown timer at address 0FHEX is controlled by the timer control register at address 0EHEX. The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1⁄60 Hz), and enables or disables the timer. Table 30. CDT1 and CDTD: Timer frequency selection CDT1 CDT0 TIMER Source clock frequency 0 0 0 1 [1] delay for n=1 delay for n = 255 4096 Hz 244 μs 62.256 ms 64 Hz 15.625 ms 3.984 s 1 0 1 Hz 1s 255 s 1 1 1⁄60 Hz 60 s 4 hrs 15 min [1] When not in use, CDT must be set to 1⁄60 Hz for power saving. Remark: Note that all timings which are generated from the 32.768kHz oscillator are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency will result in deviation in timings. This is not applicable to interface timing. The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter with 0 effectively stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the countdown Timer Flag (TF) will be set and the counter automatically re-loads and starts the next timer period. Reading the timer will return the current value of the countdown counter (see Figure 11).. countdown value, n xx 03 xx 03 timer source clock countdown counter 02 01 03 02 01 03 02 01 03 TE TF INT n duration of first timer period after enable may range from n − 1 to n + 1 n 001aaf906 In the example it is assumed that the timer flag is cleared before the next countdown period expires and that the INT is set to pulsed mode. Fig 11. General countdown timer behavior If a new value of n is written before the end of the current timer period, then this value will take immediate effect. NXP does not recommend to changing n without first disabling the counter (by setting TE = 0). The update of n is asynchronous to the timer clock, therefore changing it without setting TE = 0 will result in a corrupted value loaded into the PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 17 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar countdown counter which results an undetermined countdown period for the first period. The countdown value n will however be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated provided that this mode is enabled. See Section 6.7.2 for details on how the interrupt can be controlled. When starting the timer for the first time, the first period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous from the timer source clock. Subsequent timer periods will have no such delay. The amount of delay for the first timer period will depend on the chosen source clock, see Table 31. Table 31: First period delay for timer counter value, n. Timer source clock minimum timer period maximum timer period 4096 Hz n n+1 64 Hz n n+1 1 Hz (n-1) + 1/64Hz n + 1/64Hz 1/60 Hz (n-1) + 1/64Hz n + 1/64Hz At the end of every countdown, the timer sets the countdown Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI/TP is used to control this mode selection and the interrupt output may be disabled with the TIE bit, see Table 25. When reading the timer, the current countdown value is returned and not the initial value, n. For accurate read back of the countdown value, the SPI bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. 6.6.3 Timer flags When a minute or second interrupt occurs, MSF is set to 1. Similarly, at the end of a timer countdown, TF is set to 1. These bits maintain their value until overwritten by software. If both countdown timer and minute/second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another a logic AND is performed during a write access. Writing a ‘1’ will cause the flag to maintain it’s value, whilst writing a ‘0’ will cause the flag to be reset. Three examples are given for clearing the flags. Clearing the flags is made by a write command, therefore bits 7,6,4,1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. Table 32: Flag location in control 2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control 2 - - MSF - AF TF - - PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 18 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar The following tables show what instruction must be sent to clear the appropriate flag. Table 33: Example to clear only TF (bit 2) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control 2 - - 1 - 1 0 - - Table 34: Example to clear only MSF (bit 5) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control 2 - - 0 - 1 1 - - Table 35: Example to clear both TF and MSF Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control 2 - - 0 - 1 0 - - Clearing the alarm flag (AF) operates in exactly the same way, but is described in Section 6.5.1. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 19 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.7 Interrupt output, INT An active low interrupt signal is available at pin INT. Operation is controlled via the bits of control register 2. Interrupts may be sourced from three places; Second/minute timer, countdown timer or alarm function. With the TI/TP bit, the timer generated interrupts can be configured to either generate a pulse or to follow the status of the interrupt flags; TF and MSF. Remark: Note that the interrupts from the three groups are wire-OR’d, meaning they will mask one another (see Figure 12). SI MSF: MINUTE SECOND FLAG SET SECONDS COUNTER MINUTES COUNTER CLEAR MI to interface: read MSF SI MI 0 PULSE GENERATOR 1 TRIGGER 1 CLEAR from interface: clear MSF TE TF: TIMER to interface: read TF SET COUNTDOWN COUNTER INT TI/TP TIE 0 CLEAR PULSE GENERATOR 2 TRIGGER 1 CLEAR from interface: clear TF set alarm flag, AF AF: ALARM FLAG SET to interface: read AF CLEAR AIE 001aaf907 from interface: clear AF When SI, MI, TIE and AIE are all disabled, INT will remain high impedance. Fig 12. Interrupt scheme 6.7.1 Minute/Second interrupts The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of 1⁄64 seconds in duration. If the MSF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 13. Instructions for clearing MSF can be found in Section 6.6.3. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 20 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar seconds counter 58 59 MSF INT (1) SCL 8th clock CLEAR INSTRUCTION instruction 001aaf908 Fig 13. Example of shortening the INT pulse by clearing the MSF flag. The timing shown for clearing MSF in Figure 13 is also valid for the non-pulsed interrupt mode i.e. when TI/TP = 0, where the pulse may be shortened by setting both MI and SI to ‘0’. 6.7.2 Countdown timer interrupts Generation of interrupts from the countdown timer is controlled via the TIE bit (see Table 25). The pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value, n. As a consequence, the width of the interrupt pulse varies (see Table 36). Table 36. INT operation (bit TI / TP = 1) Source clock (Hz) INT period (s) n=1 [1] n>1 4096 1⁄8192 1⁄4096 64 1⁄128 1⁄64 1 1⁄64 1⁄64 1⁄60 1⁄64 1⁄64 [1] n = loaded countdown value. Timer stopped when n = 0. If the TF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing (see Figure 14). Instructions for clearing MSF can be found in Section 6.6.3. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 21 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar countdown counter 01 n TF INT (1) SCL 8th clock CLEAR INSTRUCTION instruction 001aaf909 Fig 14. Example of shortening the INT pulse by clearing the TF flag. The timing shown for clearing TF in Figure 14 is also valid for the non-pulsed interrupt mode i.e. when TI/TP = 0, where the pulse may be shortened by setting TIE to ‘0’. 6.7.3 Alarm interrupts Generation of interrupts from the alarm function is controlled via the AIE bit (see Table 8). If AIE is enabled, the INT pin follows the status of AF. Clearing AF will immediately clear INT. No pulse generation is possible for alarm interrupts (see Figure 15). minute counter 44 minute alarm 45 45 AF INT SCL 8th clock instruction CLEAR INSTRUCTION 001aaf910 Example where only the minute alarm is used and no other interrupts are enabled. Fig 15. AF timing PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 22 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.8 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF control bits in the control register. Frequencies of 32.768 kHz (default) down to 1Hz can be generated for use as a system clock, micro-controller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open drain output and enabled at power-on. When disabled the output is high impedance (Hi-Z). The duty cycle of the selected clock is not controlled however, due to the nature of the clock generation, all but the 32.768kHz frequencies will be 50:50. The ‘stop’ function can also affect the CLKOUT signal, depending on the selected frequency. When ‘stop’ is active, the CLKOUT pin will generate a continuous 0 for those frequencies that can be stopped. For more details see Section 6.10. Table 37: CLKOUT frequency selection COF[2:0] CLKOUT FREQUENCY, Hz Typical duty cycle High% : Low% Effect of ‘stop’ 0 0 0 32768 60:40 to 40:60 No effect 0 0 1 16384 50:50 No effect 0 1 0 8192 50:50 No effect 0 1 1 4096 50:50 CLKOUT = 0 1 0 0 2048 50:50 CLKOUT = 0 1 0 1 1024 50:50 CLKOUT = 0 1 1 0 1 50:50 CLKOUT = 0 1 1 1 CLKOUT = 0 PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 23 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.9 External clock test mode A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit ‘ext test’ in control/status1 register. Then pin CLKOUT becomes an input. The test mode replaces the internal signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generates an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit ‘stop’. When bit ‘stop’ is set, the pre-scaler is reset to 0 (stop must be cleared before the pre-scaler can operate again). From a stop condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the pre-scaler can be made. Operation example: 1. Set ‘ext test’ test mode (control/status 1, bit ‘ext test’ = 1) 2. Set stop (control/status 1, bit stop = 1) 3. Clear stop (control/status 1, bit stop = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to CLKOUT 6. Read time registers to see the first change 7. Apply 64 clock pulses to CLKOUT 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 24 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.10 ’stop’ bit function The function of the stop bit is to allow for accurate starting of the time circuits. The stop function will cause the upper part of the pre-scaler, F2 to F14, to be held in reset and thus no 1Hz ticks will be generated. The time circuits can then be set and will not increment until the stop is released. (see Figure 16). Stop will not affect the output of 32768 Hz, 16384 Hz or 8192 Hz (see Section 6.8). F2 RES F13 RES 2 Hz F1 reset 4096 Hz F0 8192 Hz OSC 16384 Hz 32768 Hz OSC STOP DETECTOR F14 1 Hz tick RES stop 512 Hz CLKOUT source 8192 Hz 16384 Hz 001aaf911 Fig 16. stop bit The lower two stages of the pre-scaler, F0 and F1, are not reset and because the SPI interface is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8192Hz cycle (see Figure 17). 8192 Hz stop released 0-122 μs 001aaf912 Fig 17. stop bit release timing The first increment of the time circuits is between 0.499888 s and 0.500000 s after stop is released. The uncertainty is caused by the pre-scaler bits F0 and F1 not being reset (see Table 38). Table 38. Stop First increment of time circuits after stop release Pre-scaler F0F1, F2 to F14 [1] 1Hz tick Time Comment HH:MM:SS Clock is running normally. 0 Pre-scaler counting normally 01-0000111010100 Stop is activated by user. F0F1 are not reset and values can not be predicted externally. 1 xx-0000000000000 12:45:12 PCA2125_00 Preliminary data sheet Pre-scaler is reset. Time circuits are frozen. © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 25 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 38. Stop First increment of time circuits after stop release Pre-scaler F0F1, F2 to F14 [1] 1Hz tick Time Comment HH:MM:SS New time is set by user. 1 xx-0000000000000 08:00:00 Pre-scaler is reset. Time circuits are frozen. Pre-scaler is now running. Stop is released by user. xx-0000000000000 08:00:00 0 xx-1000000000000 08:00:00 0 xx-0100000000000 0 xx-1100000000000 08:00:00 : : : 0 11-1111111111110 08:00:00 0 00-0000000000001 0 10-0000000000001 08:00:01 : : : 0 11-1111111111111 08:00:01 0 00-0000000000000 : : 0 11-1111111111110 0 00-0000000000001 [1] 0.499888 - 0.500000 s 1s 001aaf913 0 08:00:00 08:00:01 08:00:01 : 08:00:01 08:00:02 0 to 1 transition of F14 increments the time circuits. F0 is clocked at 32768 Hz. PCA2125_00 Preliminary data sheet 0 to 1 transition of F14 increments the time circuits. © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 26 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 6.11 3-line Serial Interface Data transfer to and from the device is made via a 3 wire SPI interface. The data lines for input and output are split to allow for alternative system wiring. The data input and output line can be connected together to facilitate a bi-directional databus. The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the MSB sent first (see Figure 18). Table 39. Serial interface Symbol Function Description [1] When inactive, the interface is reset. Pull-down resistor included. Input may be higher than VDD. CE chip enable input; active high SCL serial clock input When CE is inactive, input may float. Input may be higher than VDD. SDI serial data input When CE is inactive, input may float. Input may be higher than VDD. Input data is sampled on the rising edge of SCL. SDO serial data output Push-pull output. Drives from VSS to VDD. Output data is changed on the falling edge of SCL. [1] Chip enable may not be wired permanently high. The transmission is controlled by the active high chip enable signal CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read. Date is captured on the rising edge of the clock and transferred internally on the falling edge. data bus COMMAND DATA DATA DATA chip enable 001aaf914 Fig 18. Data transfer overview The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information. Table 40: Command byte definition Bit Symbol Value Description 7 R/W 0 Data will be write data 1 Data will be read data 001 Other codes will cause the device to ignore data transfer. 6..4 Sub Address, SA 3..0 Register Address, RA 00HEX to 0FHEX Valid address range. In the following example, the seconds register is set to 45 seconds and the minutes register to 10 minutes (see Figure 19). PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 27 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar R/W b7 0 seconds data 45BCD addr 02HEX b6 0 b5 0 b4 1 b3 0 b2 0 b1 1 b0 0 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 minutes data 10BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDI CE address counter 02 xx 03 04 001aaf915 Fig 19. Serial bus write example In the following example, the months and years registers are read (see Figure 20). In this example, SDI and SDO are not connected together. In this configuration, it is important that SDI is never left floating, it must always be driven either high or low. If SDI is left open, high IDD currents may result. R/W b7 1 months data 11BCD addr 07HEX b6 0 b5 0 b4 1 b3 0 b2 1 b1 1 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 years data 06BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 SCL SDI SDO CE address counter xx 07 08 09 001aaf916 Fig 20. Serial bus read example PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 28 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 7. Limiting values Table 41: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDD supply voltage −0.5 +6.5 V IDD supply current −50 +50 mA VI input voltage −0.5 +6.5 V VO output voltage −0.5 +6.5 V II input current −10 +10 mA IO output current −10 +10 mA Ptot total power dissipation - 300 mW Tamb ambient temperature −40 +125 °C Tstg storage temperature −65 +150 °C 7.1 ESD values • Electrostatic Discharge (ESD) protection exceeds 2000 V Human Body model (HBM) per JESD22-A114, 200 V Machine Model (MM) per JESD22-A115 and 2000 V CHarged Device Model (CDM) per JESD22-C101. • Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA. 8. Static characteristics Table 42. Static characteristics VDD = 1.2 to 5.5 V; VSS = 0 V; Tamb = −40 to +125°C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 12 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit supply voltage SPI bus inactive; Tamb = 25 °C [1] SPI bus active; Tamb = −40 to 125 °C 1.2 - 5.5 V [1] 1.6 - 5.5 V - 1.1 - V fSCL = 7.0 MHz - - 800 μA fSCL = 1.0 MHz - - 200 μA Supplies VDD VDDminclock minimum supply voltage for clock data integrity Tamb = 25 °C IDD1 supply current 1 SPI bus active PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 29 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar Table 42. Static characteristics VDD = 1.2 to 5.5 V; VSS = 0 V; Tamb = −40 to +125°C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 12 pF; unless otherwise specified. Symbol IDD2 Parameter supply current 2 Conditions Min Typ Max Unit VDD = 5.0 V - 550 725 nA VDD = 3.0 V - 550 725 nA - 550 725 nA SPI bus inactive; CLKOUT disabled; (fSCL = 0 Hz); Tamb = 25 °C [2] VDD = 2.0 V SPI bus inactive (fSCL = 0 Hz); CLKOUT disabled; Tamb = −40 to +125 °C IDD3 supply current 3 [2] VDD = 5.0 V - - - nA VDD = 3.0 V - 680 1000 nA VDD = 2.0 V - - - nA VDD = 5.0 V - - - nA VDD = 3.0 V - - - nA VDD = 2.0 V - - - nA SPI bus inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = 25 °C SPI bus inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = −40 to +125 °C VDD = 5.0 V - - - nA VDD = 3.0 V - - - nA VDD = 2.0 V - - - nA Inputs VIL LOW-level input voltage VSS - 0.3VDD V VI Input voltage for OSCI pin -0.5 - VDD+0.5 V VI Input voltage for pins CE, SDI, SCL -0.5 - 5.5 V VIH HIGH-level input voltage 0.7VDD - VDD V ILI input leakage current Ci input capacitance VI = VDD or VSS [3] −1 0 +1 μA - - 7 pF Outputs VO Output voltage for pins OSCO and SDO 0.7VDD - VDD+0.5 V VO Output voltage for CLKOUT and INT (refers to external pull-up voltage) 0.7VDD - 5.5 V IOH HIGH-level output current VOH = 4.6 V; VDD = 5 V - - 1.5 mA IOL LOW-level output current VOL = 0.4 V; VDD = 5 V (INT and CLKOUT) −1.5 - - mA IOL LOW-level output current VOL = 0.4 V; VDD = 5 V −1 - - mA ILO output leakage current VO = VDD or VSS −1 0 +1 μA COSCO Capacitance on OSCO - 25 - pF [1] For reliable oscillator start at power-up: VDD = VDD(min) + 0.3 V. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 30 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar [2] Timer source clock = 1⁄60 Hz, level of pins SCE, SDI and SCL is VDD or VSS. [3] Tested on sample basis. 9. Dynamic characteristics Table 43. Dynamic characteristics VDD1 = 1.6 to 5.5V; VSS = 0 V; Tamb = −40 to +125 °C, fCLKOUT = 32.768 kHz unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.6V VDD = 2.7V VDD = 4.5V VDD = 5.5V Min Min Min Max Min Max Max Max Unit Serial interface timing characteristics (SPI and serial interface, see Figure 21) fSCLK SCL clock frequency - 1.89 - 4.76 - 6.25 - 8.0 MHz tSCLK SCLK time 530 - 210 - 160 - 125 - ns tw(SCLKH) SCLK HIGH pulse width 200 - 100 - 100 - 62.5 - ns tw(SCLKL) SCLK LOW pulse width 200 - 100 - 100 - 62.5 - ns tRF SCLK rise and fall time - 100 - 100 - 100 - 100 ns tCES CE setup time 30 - 30 - 30 - 30 - ns tCEH CE hold time 100 - 60 - 40 - 30 - ns tCER CE recovery time 100 - 100 - 100 - 100 - ns tWCE Pulse width CE - 0.99 - 0.99 - 0.99 - 0.99 s tDS SDI setup time 20 - 10 - 10 - 5 - ns tDH SDI hold time 100 - 60 - 40 - 30 - ns tRD SDO read delay time - 216 - 100 - 75 - 60 ns tRZ SDO disable time - 50 - 30 - 30 - 25 ns tZZ Bus conflict avoidance time 0 - 0 - 0 - 0 - ns No load value. Bus will be help up by bus capacitance. Use RC time constant with application values. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 31 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar tWCE CE tCES tCYC tRF tWH tCER tWL tRF tCEH 80% SCL 20% WRITE tDS tDH SDI SDO R/W SA2 RA0 b6 b0 b7 b6 b0 Hi Z READ SDI b7 tRD tZZ SDO tRZ Hi Z b7 b6 b0 001aaf917 Fig 21. SPI interface timing 10. Application information 1F supercap OSCI VDD CLKOUT CE SCL OSCO PCA2125 SDI SDO INT VSS 001aaf918 The 1 Farad capacitor is used as a standby/back-up supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks. Fig 22. Application diagram. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 32 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 10.1 Quartz frequency adjustment 10.1.1 Method 1: fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used (see Figure 22). The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ±5 × 10−6). Average deviations of ±5 minutes per year can be easily achieved. 10.1.2 Method 2: OSCI trimmer Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible. 10.1.3 Method 3: OSCO output Direct measurement of OSCO out (accounting for test probe capacitance). PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 33 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 11. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. A1 A2 1.1 0.15 0.05 0.95 0.80 A3 bp c D (1) E (2) 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 e HE 0.65 6.6 6.2 L Lp Q 1 0.75 0.50 0.4 0.3 v 0.2 w 0.13 y Z (1) θ 0.1 0.72 0.38 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT402-1 JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 23. Package outline SOT402-1 PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 34 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 12. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5. 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 13.3 Wave soldering Key characteristics in wave soldering are: PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 35 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 24) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 44 and 45 Table 44. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 45. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 36 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 37 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 14. Revision history Table 46. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA2125_1 tbd Product data sheet - PCA2125_00.11 Modifications: PC212x_08 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Figure 11 and Figure 13: update SPI diagrams for readout data, last bit during read. Figure 4: POR ovrd diagram corrected. Section 6.6: update SPI timing. 20061218 Objective data sheet - PCA2125_00 Preliminary data sheet - © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 38 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PCA2125_00 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.11 — 30 January 2007 39 of 40 PCA2125 NXP Semiconductors SPI Real time clock / calendar 17. Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 4 5 6 6.1 6.2 6.2.1 6.3 6.3.1 6.3.2 6.4 6.4.1 6.5 6.5.1 6.6 6.6.1 6.6.2 6.6.3 6.7 6.7.1 6.7.2 6.7.3 6.8 6.9 6.10 6.11 7 7.1 8 9 10 10.1 10.1.1 10.1.2 10.1.3 11 12 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device protection diagram . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-On Reset (POR) override . . . . . . . . . . . 8 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 Control 1 register . . . . . . . . . . . . . . . . . . . . . . . 9 Control 2 register . . . . . . . . . . . . . . . . . . . . . . . 9 Time and date function . . . . . . . . . . . . . . . . . . 10 Data flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 12 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 15 Second and minute interrupt; SI, MI . . . . . . . . 16 Countdown timer function . . . . . . . . . . . . . . . . 17 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt output, INT . . . . . . . . . . . . . . . . . . . . 20 Minute/Second interrupts . . . . . . . . . . . . . . . . 20 Countdown timer interrupts. . . . . . . . . . . . . . . 21 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 22 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External clock test mode . . . . . . . . . . . . . . . . 24 ’stop’ bit function . . . . . . . . . . . . . . . . . . . . . . . 25 3-line Serial Interface . . . . . . . . . . . . . . . . . . . 27 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 ESD values . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Static characteristics. . . . . . . . . . . . . . . . . . . . 29 Dynamic characteristics . . . . . . . . . . . . . . . . . 31 Application information. . . . . . . . . . . . . . . . . . 32 Quartz frequency adjustment . . . . . . . . . . . . . 33 Method 1: fixed OSCI capacitor . . . . . . . . . . . 33 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 33 Method 3: OSCO output . . . . . . . . . . . . . . . . . 33 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 Handling information. . . . . . . . . . . . . . . . . . . . 35 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 35 36 38 39 39 39 39 39 39 40 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 January 2007 Document identifier: PCA2125_00