P89CV51RB2/RC2/RD2 8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals Rev. 03 — 25 August 2009 Product data sheet 1. General description The P89CV51RB2/RC2/RD2 are three types of 80C51 microcontroller with respectively 16 kB/32 kB/64 kB flash and 1 kB of data RAM. These devices are designed to be drop-in and software-compatible replacements for the popular P89C51RB2/RC2/RD2 devices. Both the In-System Programming (ISP) and In-Application Programming (IAP) boot codes are upward compatible. Additional features of the P89CV51RB2/RC2/RD2 devices compared to the P89C51RB2/RC2/RD2 are the inclusion of an SPI interface, larger RAM size, and the ability to erase code memory in 128-B page blocks. The IAP capability combined with the 128-B page size allows for efficient use of the code memory for non-volatile data storage. 2. Features 2.1 Principal features n Supports 12-clock (default) or 6-clock mode selection via ISP or parallel programmer n 6-clock/12-clock mode programmable “on-the-fly” by an SFR bit n Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the CPU is in 6-clock mode n 128-B page erase for efficient use of code memory as non-volatile data storage n 0 MHz to 40 MHz operating frequency in 12× mode, 20 MHz in 6× mode n 16/32/64 kB of on-chip flash user-code memory with ISP and IAP n 1 kB RAM n SPI (Serial Peripheral Interface) and enhanced UART n PCA (Programmable Counter Array) with PWM and capture/compare functions n Three 16-bit timers/counters 2.2 Additional features n n n n n n n Four 8-bit I/O ports WatchDog Timer (WDT) 30 ms page erase, 150 ms block erase PLCC44 and TQFP44 packages Ten interrupt sources with four priority levels Second DPTR register Low EMI mode (ALE inhibit) P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI n Power-down mode with external interrupt wake-up n Idle mode 2.3 Comparison to P89C51RB2/RC2/RD2 devices n SPI: The P89CV51RB2/RC2/RD2 devices have an SPI interface that was not present on the P89C51RB2/RC2/RD2 devices. n Smaller block size: The page size decreased from 4 kB to 128 B. These smaller pages can be erased and reprogrammed using IAP function calls, which makes practical use of code memory for non-volatile data storage. A page is erased in 30 ms or less. IAP and ISP code both support 128-B page operations. The IAP and ISP code uses multiple page-erase operations to emulate the erasing of larger block sizes (8 kB and 16 kB) to maintain firmware compatibility. n Status bit replaces Status byte: Automatic entry into ISP mode following a reset is now controlled by one status bit. Its operation is almost identical to that used by the previous devices, which was based on the zero/non-zero value of the status byte. n Faster block erase: The erase time for the entire user-code memory of the P89CV51RB2/RC2/RD2 devices is 150 ms, which is a significant improvement. n Larger RAM size: RAM size increased from 512 B to 1 kB. 3. Ordering information Table 1. Ordering information Type number Package Name Description Version P89CV51RB2FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 P89CV51RB2FBC TQFP44 plastic thin quad flat package; 44 leads; body 10 × 10 × 1.0 mm SOT376-1 P89CV51RC2FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 P89CV51RC2FBC TQFP44 plastic thin quad flat package; 44 leads; body 10 × 10 × 1.0 mm SOT376-1 P89CV51RD2FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 P89CV51RD2FBC TQFP44 plastic thin quad flat package; 44 leads; body 10 × 10 × 1.0 mm SOT376-1 3.1 Ordering options Table 2. Ordering options Type number Flash memory RAM Temperature range Frequency P89CV51RB2FA 16 kB 1 kB −40 °C to +85 °C 0 MHz to 40 MHz 32 kB 1 kB 64 kB 1 kB P89CV51RB2FBC P89CV51RC2FA P89CV51RC2FBC P89CV51RD2FA P89CV51RD2FBC P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 2 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 4. Block diagram P89CV51RB2/RC2/RD2 16 kB/32 kB/64 kB CODE FLASH HIGH PERFORMANCE 80C51 CPU TXD RXD UART internal bus SPICLK MOSI MISO SS 1 kB DATA RAM SPI P3[7:0] PORT 3 TIMER 0 TIMER 1 T0 T1 P2[7:0] PORT 2 TIMER 2 T2 T2EX P1[7:0] PORT 1 PCA PROGRAMMABLE COUNTER ARRAY P0[7:0] PORT 0 WATCHDOG TIMER CRYSTAL OR RESONATOR CEX[4:0] XTAL1 OSCILLATOR XTAL2 002aac960 Fig 1. Block diagram P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 3 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 5. Pinning information 40 P0[3]/AD3 41 P0[2]/AD2 42 P0[1]/AD1 43 P0[0]/AD0 n.c. 1 44 VDD P1[1]/T2EX P1[0]/T2 P1[2]/ECI 4 2 P1[3]/CEX0 5 3 P1[4]/CEX1/SS 6 5.1 Pinning P1[5]/CEX2/MOSI 7 39 P0[4]/AD4 P1[6]/CEX3/MISO 8 38 P0[5]/AD5 P1[7]/CEX4/SPICLK 9 37 P0[6]/AD6 RST 10 36 P0[7]/AD7 P3[0]/RXD 11 35 EA P89CV51RB2/RC2/RD2 n.c. 12 P2[4]/A12 28 P2[3]/A11 27 P2[1]/A9 25 P2[2]/A10 26 n.c. 23 002aac962 PLCC44 pin configuration P89CV51RB2_RC2_RD2_3 Product data sheet P2[0]/A8 24 29 P2[5]/A13 VSS 22 30 P2[6]/A14 P3[5]/T1 17 XTAL1 21 31 P2[7]/A15 P3[4]/T0 16 XTAL2 20 32 PSEN P3[3]/INT1 15 P3[7]/RD 19 33 ALE P3[2]/INT0 14 P3[6]/WR 18 Fig 2. 34 n.c. P3[1]/TXD 13 © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 4 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 34 P0[3]/AD3 35 P0[2]/AD2 36 P0[1]/AD1 37 P0[0]/AD0 38 VDD 39 n.c. 40 P1[0]/T2 41 P1[1]/T2EX 42 P1[2]/ECI P1[5]/CEX2/MOSI 1 33 P0[4]/AD4 P1[6]/CEX3/MISO 2 32 P0[5]/AD5 P1[7]/CEX4/SPICLK 3 31 P0[6]/AD6 RST 4 30 P0[7]/AD7 P3[0]/RXD 5 n.c. 6 P3[1]/TXD 7 27 ALE P3[2]/INT0 8 26 PSEN P3[3]/INT1 9 25 P2[7]/A15 P3[4]/T0 10 24 P2[6]/A14 P3[5]/T1 11 23 P2[5]/A13 29 EA P2[4]/A12 22 28 n.c. P2[3]/A11 21 P2[2]/A10 20 P2[1]/A9 19 P2[0]/A8 18 n.c. 17 VSS 16 XTAL1 15 XTAL2 14 P3[7]/RD 13 P89CV51RB2/RC2/RD2 P3[6]/WR 12 Fig 3. 43 P1[3]/CEX0 44 P1[4]/CEX1/SS 80C51 with 1 kB RAM, SPI 002aac961 TQFP44 pin configuration 5.2 Pin description Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 P0[0] to P0[7] P0[0]/AD0 P0[1]/AD1 P0[2]/AD2 P0[3]/AD3 P0[4]/AD4 P0[5]/AD5 43 42 41 40 39 38 Type Description I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when transitioning to 1s. External pull-ups are required when used as a general purpose I/O port. TQFP44 37 36 35 34 33 32 I/O P0[0] — Port 0 bit 0. I/O AD0 — Address/data bit 0. I/O P0[1] — Port 0 bit 1. I/O AD1 — Address/data bit 1. I/O P0[2] — Port 0 bit 2. I/O AD2 — Address/data bit 2. I/O P0[3] — Port 0 bit 3. I/O AD3 — Address/data bit 3. I/O P0[4] — Port 0 bit 4. I/O AD4 — Address/data bit 4. I/O P0[5] — Port 0 bit 5. I/O AD5 — Address/data bit 5. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 5 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 3. P89CV51RB2/RC2/RD2 Pin description …continued Symbol P0[6]/AD6 P0[7]/AD7 Pin PLCC44 TQFP44 37 31 36 30 P1[0] to P1[7] P1[0]/T2 P1[1]/T2EX P1[2]/ECI P1[3]/CEX0 P1[4]/CEX1/ SS 2 3 4 5 6 P1[5]/CEX2/ MOSI 7 P1[6]/CEX3/ MISO 8 P1[7]/CEX4/ SPICLK 9 40 41 42 43 44 1 2 3 P2[0] to P2[7] P2[0]/A8 24 18 Type Description I/O P0[6] — Port 0 bit 6. I/O AD6 — Address/data bit 6. I/O P0[7] — Port 0 bit 7. I/O AD7 — Address/data bit 7. I/O with internal pull-up Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 pins are pulled HIGH by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. P1[5], P1[6], P1[7] have high current drive of 16 mA. I/O P1[0] — Port 1 bit 0. I/O T2 — External count input to timer/counter 2 or clock-out from timer/counter 2. I/O P1[1] — Port 1 bit 1. I T2EX: Timer/counter 2 capture/reload trigger and direction control. I/O P1[2] — Port 1 bit 2. I ECI — External clock input. This signal is the external clock input for the PCA. I/O P1[3] — Port 1 bit 3. I/O CEX0 — Capture/compare external I/O for PCA Module 0. Each capture/compare module connects to a Port 1 pin for external I/O. When not used by the PCA, this pin can handle standard I/O. I/O P1[4] — Port 1 bit 4. I/O CEX1 — Capture/compare external I/O for PCA Module 1. I SS — Slave Select input for SPI. I/O P1[5] — Port 1 bit 5. I/O CEX2 — Capture/compare external I/O for PCA Module 2. I/O MOSI — Master output/slave input for SPI. I/O P1[6] — Port 1 bit 6. I/O CEX3 — Capture/compare external I/O for PCA Module 3. I/O MISO — Master input/slave output for SPI. I/O P1[7] — Port 1 bit 7. I/O CEX4 — Capture/compare external I/O for PCA Module 4. I/O SPICLK — Serial clock input/output for SPI. I/O with internal pull-up Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins are pulled HIGH by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (MOVX @DPTR). In this application, it uses strong internal pull-ups when transitioning to 1s. I/O P2[0] — Port 2 bit 0. O A8 — Address bit 8. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 6 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 3. P89CV51RB2/RC2/RD2 Pin description …continued Symbol P2[1]/A9 P2[2]/A10 P2[3]/A11 P2[4]/A12 P2[5]/A13 P2[6]/A14 P2[7]/A15 Pin PLCC44 TQFP44 25 19 26 27 28 29 30 31 20 21 22 23 24 25 P3[0] to P3[7] P3[0]/RXD 11 5 P3[1]/TXD 13 7 P3[2]/INT0 14 8 P3[3]/INT1 15 9 P3[4]/T0 16 10 Type Description I/O P2[1] — Port 2 bit 1. O A9 — Address bit 9. I/O P2[2] — Port 2 bit 2. O A10 — Address bit 10. I/O P2[3] — Port 2 bit 3. O A11 — Address bit 11. I/O P2[4] — Port 2 bit 4. O A12 — Address bit 12. I/O P2[5] — Port 2 bit 5. O A13 — Address bit 13. I/O P2[6] — Port 2 bit 6. O A14 — Address bit 14. I/O P2[7] — Port 2 bit 7. O A15 — Address bit 15. I/O with internal pull-up Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins are pulled HIGH by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. I/O P3[0] — Port 3 bit 0. I RXD — Serial input port. I/O P3[1] — Port 3 bit 1. O TXD — Serial output port. I/O P3[2] — Port 3 bit 2. I INT0 — External interrupt 0 input. I/O P3[3] — Port 3 bit 3. I INT1 — External interrupt 1 input. I/O P3[4] — Port 3 bit 4. I T0 — External count input to timer/counter 0. P3[5]/T1 17 11 I/O P3[5] — Port 3 bit 5. I T1 — External count input to timer/counter 1. P3[6]/WR 18 12 I/O P3[6] — Port 3 bit 6. O WR — External data memory write strobe. I/O P3[7] — Port 3 bit 7. P3[7]/RD 19 13 PSEN 32 26 O RD — External data memory read strobe. O Program Store Enable: PSEN is the read strobe for external program memory. When the device is executing from internal program memory, PSEN is inactive (HIGH). When the device is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 7 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 3. P89CV51RB2/RC2/RD2 Pin description …continued Symbol Pin Type Description 4 I Reset: While the oscillator is running, a HIGH logic state on this pin for two machine cycles will reset the device. 35 29 I External Access Enable: EA must be connected to VSS in order to enable the device to fetch code from the external program memory. EA must be strapped to VDD for internal program execution. ALE 33 27 I/O Address Latch Enable: ALE is the output signal for latching the low byte of the address during an access to external memory. Normally the ALE[1] is emitted at a constant rate of 1⁄6 the crystal frequency[2] and can be used for external timing and clocking. One ALE pulse is skipped during each access to external data memory. However, if bit AO is set to 1, ALE is disabled. XTAL1 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 20 14 O Crystal 2: Output from the inverting oscillator amplifier. VDD 44 38 supply Power supply VSS 22 16 supply Ground PLCC44 TQFP44 RST 10 EA [1] ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor from 3 kΩ to 50 kΩ between e.g., ALE pin and VDD. [2] For 6-clock mode, ALE is emitted at 1⁄3 of crystal frequency. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 8 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6. Functional description 6.1 Special function registers Remark: SFR accesses are restricted in the following ways: • Do not attempt to access any SFR locations that are undefined. • Access to defined SFR locations must be strictly for the functions of the SFRs. • SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: – ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 9 of 76 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89CV51RB2_RC2_RD2_3 Product data sheet Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR address Bit address Bit functions and addresses[1] MSB LSB E7 E6 E5 E4 E3 E2 E1 E0 - - - - - - ACC* Accumulator E0H - - AUXR Auxiliary function Register 8EH - - - - - - EXTRAM AO AUXR1 Auxiliary function Register 1 A2H - - ENBOOT - GF2 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 F0H - - - - - - - - Bit address CCAP0H Module 0 Capture High FAH - - - - - - - - CCAP1H Module 1 Capture High FBH - - - - - - - - CCAP2H Module 2 Capture High FCH - - - - - - - - CCAP3H Module 3 Capture High FDH - - - - - - - - CCAP4H Module 4 Capture High FEH - - - - - - - - CCAP0L Module 0 Capture Low EAH - - - - - - - - CCAP1L Module 1 Capture Low EBH - - - - - - - - CCAP2L Module 2 Capture Low ECH - - - - - - - - CCAP3L Module 3 Capture Low EDH - - - - - - - - CCAP4L Module 4 Capture Low EEH - - - - - - - - CCAPM0 Module 0 mode DAH - ECOM_0 CAPP_0 CAPN_0 MAT_0 TOG_0 PWM_0 ECCF_0 CCAPM1 Module 1 mode DBH - ECOM_1 CAPP_1 CAPN_1 MAT_1 TOG_1 PWM_1 ECCF_1 CCAPM2 Module 2 mode DCH - ECOM_2 CAPP_2 CAPN_2 MAT_2 TOG_2 PWM_2 ECCF_2 CCAPM3 Module 3 mode DDH - ECOM_3 CAPP_3 CAPN_3 MAT_3 TOG_3 PWM_3 ECCF_3 CCAPM4 Module 4 mode DEH - ECOM_4 CAPP_4 CAPN_4 MAT_4 TOG_4 PWM_4 ECCF_4 DF DE DD DC DB DA D9 D8 Bit address 10 of 76 © NXP B.V. 2009. All rights reserved. CCON* PCA Counter Control D8H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CH PCA Counter High F9H - - - - - - - - CL PCA Counter Low E9H - - - - - - - - CMOD PCA Counter Mode D9H CIDL WDTE - - - CPS1 CPS0 ECF CKCON Clock Control 8FH SPIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 80C51 with 1 kB RAM, SPI B register P89CV51RB2/RC2/RD2 Rev. 03 — 25 August 2009 B* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name DPTR Description Bit functions and addresses[1] SFR address MSB LSB Data Pointer (2 B) DPH Data Pointer High 83H - - - - - - - - DPL Data Pointer Low 82H - - - - - - - - AF AE AD AC AB AA A9 A8 EA EC ET2 ES ET1 EX1 ET0 EX0 BF BE BD BC BB BA B9 B8 Bit address IE* Interrupt Enable A8H Bit address IP* Interrupt Priority Low B8H - PPC PT2 PS PT1 PX1 PT0 PX0 IPH Interrupt Priority High B7H - PPCH PT2H PSH PT1H PX1H PT0H PX0H P0* Port 0 Bit address Port 1 90H Bit address P2* Port 2 A0H Bit address 87 86 85 84 83 82 81 80 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 CEX4/ SPICLK CEX3/ MISO CEX2/ MOSI CEX1/SS CEX0 ECI T2EX T2 A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD PCON Power Control 87H SMOD1 SMOD0 - POF GF1 GF0 PD IDL D7 D6 D5 D4 D3 D2 D1 D0 Bit address Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P RCAP2H Timer 2 Capture High CBH - - - - - - - - RCAP2L Timer 2 Capture Low CAH - - - - - - - - 9F 9E 9D 9C 9B 9A 99 98 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI Bit address 11 of 76 © NXP B.V. 2009. All rights reserved. SCON* Serial port Control SBUF Serial port data Buffer 99H - - - - - - - - SADDR Serial port Address A9H - - - - - - - - SADEN Serial port Address Enable B9H - - - - - - - - 80C51 with 1 kB RAM, SPI PSW* P89CV51RB2/RC2/RD2 Rev. 03 — 25 August 2009 80H Bit address P1* NXP Semiconductors P89CV51RB2_RC2_RD2_3 Product data sheet Table 4. Special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR address Bit address Bit functions and addresses[1] MSB LSB 87 86 85 84 83 82 81 80 SPCR SPI Control Register D5H SPIE SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SPSR SPI Status Register AAH SPIF WCOL - - - - - - SPDAT SPI Data 86H - - - - - - - - SP Stack Pointer 81H Bit address TCON* Timer/counter Control 88H Bit address - - - - - - - - 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 CF CE CD CC CB CA C9 C8 Timer/counter 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Timer 2 Mode control C9H - - - - - - T2OE DCEN TH0 Timer 0 High 8CH - - - - - - - - TH1 Timer 1 High 8DH - - - - - - - - TH2 Timer 2 High CDH - - - - - - - - TL0 Timer 0 Low 8AH - - - - - - - - TL1 Timer 1 Low 8BH - - - - - - - - TL2 Timer 2 Low CCH - - - - - - - - TMOD Timer/counter 0 and 1 Mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 WDTRST WatchDog Timer Reset A6H - - - - - - - - Unimplemented bits in SFRs (labeled ‘-’) are ‘X’ (unknown) at all times. Unless otherwise specified, 1s should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are 0s although they are unknown when read. 80C51 with 1 kB RAM, SPI 12 of 76 © NXP B.V. 2009. All rights reserved. P89CV51RB2/RC2/RD2 Rev. 03 — 25 August 2009 T2CON* T2MOD [1] NXP Semiconductors P89CV51RB2_RC2_RD2_3 Product data sheet Table 4. Special function registers …continued * indicates SFRs that are bit addressable. P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.2 Memory organization The various P89CV51RB2/RC2/RD2 memory spaces are as follows: • DATA 128 B of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the stack may be in this area. • IDATA Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the stack may be in this area. This area includes the DATA area and the 128 B immediately above it. • SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. • XDATA ‘External’ Data or auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. The P89CV51RB2/RC2/RD2 have 768 B of on-chip XDATA memory. • CODE 64 kB of code memory space, accessed as part of program execution and via the MOVC instruction. The P89CV51RB2/RC2/RD2 have 16/32/64 kB of on-chip code memory. 6.2.1 Expanded data RAM addressing The P89CV51RB2/RC2/RD2 have 1 kB of data RAM; see Figure 4. To access the expanded RAM (XRAM), the EXTRAM bit must be set and MOVX instructions must be used. The expanded memory is physically located on the chip and logically occupies the first bytes of external memory (addresses 000H to 2FFH). Table 5. AUXR - Auxiliary function register (address 8EH) bit allocation Not bit addressable; reset value 00H. Bit 7 6 5 4 3 2 1 0 Symbol - - - - - - EXTRAM AO When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does not affect ports P0, P3[6] (WR), P3[7] (RD), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the following example. Expanded RAM access (indirect addressing only): MOVX @DPTR, A; DPTR contains 0A0H P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 13 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI The DPTR points to location 0A0H and the data in the accumulator is written to address 0A0H of the expanded RAM rather than off-chip external memory. Access to EXTRAM addresses that are not present on the device (above 2FFH) will access external off-chip memory and will perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and P3[6] and P3[7] as write and read timing signals. Table 6. AUXR - Auxiliary function register (address 8EH) bit description Bit Symbol Description 7 to 2 - Reserved for future use. Should be set to 0 by user programs. 1 EXTRAM Internal/external RAM access using MOVX @Ri/@DPTR. When 0, accesses internal XRAM with address specified in MOVX instruction. If address supplied with this instruction exceeds on-chip available XRAM, off-chip RAM is accessed. When 1, every MOVX instruction targets external data memory by default. 0 AO ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a constant rate of 1⁄2 the oscillator frequency. In case of AO = 1, ALE is active only during a MOVX or MOVC. When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output port pins can be used to output higher order address bits. This provides external paging capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external addressing up to 64 kB. Port 2 provides the high-order eight address bits (DPH), and Port 0 multiplexes the low-order eight address bits (DPL) with data. Both MOVX @Ri and MOVX @DPTR generates the necessary read and write signals (P3[6] - WR and P3[7] RD) for external memory use. Table 7 shows external data memory RD, WR operation with EXTRAM bit. The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower 128 B and upper 128 B). The stack pointer may not be located in any part of the expanded RAM. Table 7. External data memory RD, WR with EXTRAM bit AUXR MOVX @DPTR, A or MOVX A, @DPTR ADDR < 0300H ADDR ≥ 0300H ADDR = any EXTRAM = 1 RD/WR asserted RD/WR asserted RD/WR asserted EXTRAM = 0 RD/WR not asserted RD/WR asserted RD/WR not asserted P89CV51RB2_RC2_RD2_3 Product data sheet MOVX @Ri, A or MOVX A, @Ri © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 14 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 2FFH EXPANDED RAM 768 B FFH 80H 7FH 000H (INDIRECT ADDRESSING) 00H FFFFH (INDIRECT ADDRESSING) UPPER 128 B INTERNAL RAM FFH 80H (DIRECT ADDRESSING) SPECIAL FUNCTION REGISTERS (SFRs) LOWER 128 B INTERNAL RAM (INDIRECT AND DIRECT ADDRESSING) (INDIRECT ADDRESSING) FFFFH (INDIRECT ADDRESSING) EXTERNAL DATA MEMORY EXTERNAL DATA MEMORY 0300H 2FFH EXPANDED RAM 0000H 000H EXTRAM = 0 EXTRAM = 1 002aaa517 Fig 4. Internal and external data memory structure 6.2.2 Dual data pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1; see Figure 5. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 15 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI AUXR1 / bit0 DPS DPTR1 DPTR0 DPS = 0 → DPTR0 DPS = 1 → DPTR1 DPL 82H DPH 83H external data memory 002aaa518 Fig 5. Dual data pointer organization Table 8. AUXR1 - Auxiliary function register 1 (address A2H) bit allocation Not bit addressable; reset value 00H. Bit 7 6 5 4 3 2 1 0 Symbol - - ENBOOT - GF2 0 - DPS Table 9. AUXR1 - Auxiliary function register 1 (address A2H) bit description Bit Symbol Description 7, 6, 4 - Reserved for future use. Should be set to 0 by user programs. 5 ENBOOT Enable BOOTROM 3 GF2 General purpose user-defined Flag. 2 0 This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. 1 - Reserved for future use. Should be set to 0 by user programs. 0 DPS Data Pointer Select. Chooses one of two data pointers for use by the program. See text for details. 6.2.3 Reset At initial power-up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash. A system reset will not affect the on-chip RAM while the device is running, however, the contents of the on-chip RAM during power-up are indeterminate. When power is applied to the device, the RST pin must be held HIGH long enough for the oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement an RC circuit by connecting the RST pin to VDD through a 10 µF capacitor and to VSS through an 8.2 kΩ resistor as shown in Figure 6. During initial power-up the POF flag in the PCON register is set to indicate an initial power-up condition. The POF flag will remain active until cleared by software. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 16 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Following a reset condition, under normal conditions, the MCU will start executing code from address 0000H in the user’s code memory. However if either the PSEN pin was LOW when reset was exited, or the status bit = 1, the MCU will start executing code from the boot address. The boot address is formed using the value of the boot vector as the high byte of the address and 00H as the low byte. VDD 10 µF VDD RST 8.2 kΩ C2 XTAL2 XTAL1 C1 002aaa543 Fig 6. Power-on reset circuit 6.3 Flash memory 6.3.1 Flash organization The P89CV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block for user code. The flash can be read or written in bytes and can be erased in 128-B pages. A chip erase function will erase the entire user code memory and its associated security bits. There are three methods for erasing or programming the flash memory that may be used. First, the flash may be programmed or erased in the end-user application by calling LOW-state routines through a common IAP entry point. Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call LOW-state routines through the same common entry point that can be used by the end-user application. Third, the flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer which supports this device. 6.3.2 Features • Flash internal program memory with 128-B page erase. • Internal boot block, containing LOW-state IAP routines available to user code. • Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. • Default loader providing ISP via the serial port, located in upper-end of program memory. • Programming and erase over the full operating voltage range. • Read/Programming/Erase using ISP/IAP. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 17 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI • Programming with industry-standard commercial programmers. • 10000 typical erase/program cycles for each byte. • 100 year minimum data retention. 6.3.3 Boot block When the microcontroller programs its own flash memory, all of the low-level details are handled by code (bootloader) that is contained in a boot block. A user program calls the common entry point in the boot block with appropriate parameters to accomplish the desired operation. Boot block operations include erase user code, program user code, program security bits, chip erase, etc. The boot block logically overlays the program memory space from FC00H to FFFFH, when it is enabled. The boot block may be disabled on-the-fly so that the upper 1 kB of user code is available to the user’s program. 6.3.4 Power-on reset code execution The P89CV51RB2/RC2/RD2 contains two special flash elements: the boot vector and the boot status bit. Following reset, the P89CV51RB2/RC2/RD2 examines the contents of the boot status bit. If the boot status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the boot status bit is set to a value other than zero, the contents of the boot vector are used as the high byte of the execution address and the low byte is set to 00H. Table 10 shows the factory default boot vector setting for this device. A factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions. Table 10. Default boot vector values and ISP entry points Device Default boot vector Default bootloader entry point Default bootloader code range P89CV51RB2/RC2/RD2 FCH FC00H FC00H to FFFFH 6.3.5 Hardware activation of the bootloader The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence. This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. This occurs by holding PSEN LOW at the falling edge of reset. If the factory default setting for the boot vector (FCH) is changed, it will no longer point to the factory pre-programmed ISP bootloader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H. 6.3.6 ISP ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89CV51RB2/RC2/RD2 through the serial port. This firmware is provided by NXP and embedded within each P89CV51RB2/RC2/RD2 device. The NXP ISP facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 18 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.3.7 Using ISP The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89CV51RB2/RC2/RD2 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below: :NNAAAARRDD..DDCC<crlf> In the Intel Hex record, the ‘NN’ represents the number of data bytes in the record. The P89CV51RB2/RC2/RD2 will accept up to 32 data bytes. The ‘AAAA’ string represents the address of the first byte in the record. If there are zero bytes in the record, this field is often set to 0000. The ‘RR’ string indicates the record type. A record type of ‘00’ is a data record. A record type of ‘01’ indicates the end-of-file mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 32 (decimal). ISP commands are summarized in Table 11. As a record is received by the P89CV51RB2/RC2/RD2, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89CV51RB2/RC2/RD2 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a ‘.’ character out the serial port. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 19 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 11. ISP Hex record formats Record type Command/data function 00 Program user code memory :nnaaaa00dd..ddcc Where: nn = number of bytes to program aaaa = address dd..dd = data bytes cc = checksum Example: :09000000010203040506070809CA 01 End of File (EOF), no operation :xxxxxx01cc Where: xxxxxx = required field but value is a don’t care cc = checksum Example: :00000001FF 02 not used P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 20 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 11. ISP Hex record formats …continued Record type Command/data function 03 Miscellaneous write functions :nnxxxx03ffssddcc Where: nn = number of bytes in the record xxxx = required field but value is a don’t care ff = subfunction code ss = selection code dd = data (if needed) cc = checksum Subfunction code = 0C (erase 4 kB blocks) ff = 0C ss = block code, as shown below: block 0, 0 kB to 4 kB, 00H block 1, 4 kB to 8 kB, 10H block 2, 8 kB to 12 kB, 20H block 3, 12 kB to 16 kB, 30H block 4, 16 kB to 20 kB, 40H (only available on P89CV51RC2/RD2) block 5, 20 kB to 24 kB, 50H (only available on P89CV51RC2/RD2) block 6, 24 kB to 28 kB, 60H (only available on P89CV51RC2/RD2) block 7, 28 kB to 32 kB, 70H (only available on P89CV51RC2/RD2) block 8, 32 kB to 36 kB, 80H (only available on P89CV51RD2) block 9, 36 kB to 40 kB, 90H (only available on P89CV51RD2) block 10, 40 kB to 44 kB, A0H (only available on P89CV51RD2) block 11, 44 kB to 48 kB, B0H (only available on P89CV51RD2) block 12, 48 kB to 52 kB, C0H (only available on P89CV51RD2) block 13, 52 kB to 56 kB, D0H (only available on P89CV51RD2) block 14, 56 kB to 60 kB, E0H (only available on P89CV51RD2) block 15, 60 kB to 64 kB, F0H (only available on P89CV51RD2) Example: :020000030C20CF (erase 4 kB block #2) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 21 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 11. ISP Hex record formats …continued Record type Command/data function 03 (continued) Subfunction code = 01 (erase blocks) ff = 01 ss = block code, as shown below block 0, 0 kB to 8 kB, 00H block 1, 8 kB to 16 kB, 20H block 2, 16 kB to 32 kB, 40H block 3, 32 kB to 48 kB, 80H block 4, 48 kB to 64 kB, C0H Subfunction code = 04 (erase boot vector and status bit) ff = 04 ss = don’t care Subfunction code = 05 (program security bits) ff = 05 ss = 00 program security bit 1 ss = 01 program security bit 2 ss = 02 program security bit 3 Subfunction code = 06 (program status bit, boot vector, 6×/12× bit) ff = 06 dd = data (for boot vector) ss = 00 program status bit ss = 01 program boot vector ss = 02 program 6×/12× bit Subfunction code = 07 (chip erase) Erases code memory and security bits, programs default boot vector and status bit ff = 07 Subfunction code = 08 (erase page, 128 B) ff = 08 ss = high byte of page address (A[15:8]) dd = low byte of page address (A[7:0]) Example: :0300000308E000F2 (erase page at E000H) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 22 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 11. ISP Hex record formats …continued Record type Command/data function 04 Display device data or blank check :05xxxx04sssseeeeffcc Where 05 = number of bytes in the record xxxx = required field but value is a don’t care 04 = function code for display or blank check ssss = starting address, MSB first eeee = ending address, MSB first ff = subfunction 00 = display data 01 = blank check cc = checksum Subfunction codes: Example: :0500000400001FFF00D9 (display from 0000H to 1FFFH) 05 Miscellaneous read functions :02xxxx05ffsscc Where: 02 = number of bytes in the record xxxx = required field but value is a don’t care 05 = function code for miscellaneous read ffss = subfunction and selection code 0000 = read manufacturer ID 0001 = read device ID 1 0002 = read device ID 2 0003 = read 6×/12× bit (bit 7 = 1 is 6×, bit 7 = 0 is 12×) 0080 = read boot code version 0700 = read security bits 0701 = read status bit 0702 = read boot vector cc = checksum Example: :020000050000F9 (display manufacturer ID) 06 Direct load of baud rate :02xxxx06HHLLcc Where: 02 = number of bytes in the record xxxx = required field but value is a don’t care HH = high byte of timer T2 LL = low byte of timer T2 cc = checksum Example: :02000006FFFFcc (load T2 = FFFF) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 23 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.3.8 IAP method Several IAP calls are available for use by an application program to permit selective erasing, reading and programming of flash pages, security bits, status bit, and device ID. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0H. The IAP calls are shown in Table 12. Table 12. IAP function calls IAP function IAP call parameters Read ID Input parameters: R1 = 00H or 80H (WDT feed) DPH = 00H DPL = 00H = manufacturer ID DPL = 01H = device ID 1 DPL = 02H = device ID 2 DPL = 03H = 6×/12× bit (if bit 7 = 1: 6×) DPL = 80H = ISP version number Return parameter(s): ACC = requested parameter Erase 4 kB code block (new function) Input parameters: R0 = oscillator frequency (integer) R1 = 0CH or 8CH (WDT feed) DPH = address of 4 kB code block DPH = 00H, 4 kB block 0, 0 kB to 4 kB DPH = 10H, 4 kB block 1, 4 kB to 8 kB DPH = 20H, 4 kB block 2, 8 kB to 12 kB DPH = 30H, 4 kB block 3, 12 kB to 16 kB DPH = 40H, 4 kB block 4, 16 kB to 20 kB DPH = 50H, 4 kB block 5, 20 kB to 24 kB DPH = 60H, 4 kB block 6, 24 kB to 28 kB DPH = 70H, 4 kB block 7, 28 kB to 32 kB DPH = 80H, 4 kB block 8, 32 kB to 36 kB DPH = 90H, 4 kB block 9, 36 kB to 40 kB DPH = A0H, 4 kB block 10, 40 kB to 44 kB DPH = B0H, 4 kB block 11, 44 kB to 48 kB DPH = C0H, 4 kB block 12, 48 kB to 52 kB DPH = D0H, 4 kB block 13, 52 kB to 56 kB DPH = E0H, 4 kB block 14, 56 kB to 60 kB DPH = F0H, 4 kB block 15, 60 kB to 64 kB DPL = 00H Return parameter(s): ACC = 00: pass ACC is not 00: fail P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 24 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 12. IAP function calls …continued IAP function IAP call parameters Erase 8 kB/16 kB code block Input parameters: R1 = 01H or 81H (WDT feed) DPH = 00H, block 0, 0 kB to 8 kB DPH = 20H, block 1, 8 kB to 16 kB DPH = 40H, block 2, 16 kB to 32 kB DPH = 80H, block 3, 32 kB to 48 kB DPH = C0H, block 4, 48 kB to 64 kB Return parameter(s): ACC = 00: pass ACC is not 00: fail Program user code Input parameters: R1 = 02H or 82H (WDT feed) DPH = memory address MSB DPL = memory address LSB ACC = byte to program Return parameter(s): ACC = 00: pass ACC is not 00: fail Read user code Input parameters: R1 = 03H or 83H (WDT feed) DPH = memory address MSB DPL = memory address LSB Return parameter(s): ACC = device data Erase status bit and boot vector Input parameters: R1 = 04H or 84H (WDT feed) DPL = don’t care DPH = don’t care Return parameter(s): ACC = 00: pass ACC is not 00: fail Program security bits Input parameters: R1 = 05H or 85H (WDT feed) DPL = 00H = security bit 1 DPL = 01H = security bit 2 DPL = 02H = security bit 3 Return parameter(s): ACC = 00: pass ACC is not 00: fail P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 25 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 12. IAP function calls …continued IAP function IAP call parameters Program status bit, boot vector, 6×/12× bit Input parameters: R1 = 06H or 86H (WDT feed) DPL = 00H = program status bit DPL = 01H = program boot vector DPL = 02H = 6×/12× bit ACC = boot vector value to program Return parameter(s): ACC = 00: pass ACC is not 00: fail Read security bits, status bit, boot vector Input parameters: ACC = 07H or 87H (WDT feed) DPL = 00H = security bits DPL = 01H = status bit DPL = 02H = boot vector Return parameter(s): ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK Erase page Input parameters: R1 = 08H or 88H (WDT feed) DPH = page address high byte DPL = page address low byte Return parameter(s): ACC = 00: pass ACC is not 00: fail 6.4 Timers/counters 0 and 1 The two 16-bit timer/counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters (see Table 13 and Table 14). In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of six oscillator periods, the count rate is 1⁄6 of the oscillator frequency. In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the count is incremented. The new count value appears in the register in the machine cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) for a 1-to-0 transition to be recognized, the maximum count rate is 1⁄ of the oscillator frequency. There are no restrictions on the duty cycle of the external 12 input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’ selection, Timer 0 and Timer 1 have four selectable operating modes. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 26 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the special function register TMOD. These two timers/counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timers/counters. Mode 3 is different. The four operating modes are described in the following text. Table 13. TMOD - Timer/Counter mode control register (address 89H) bit allocation Not bit addressable; reset value: 0000 0000B; reset source(s): any source. Bit Symbol 7 6 5 4 3 2 1 0 T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 Table 14. TMOD - Timer/Counter mode control register (address 89H) bit description Bit Symbol Description 7 T1GATE Gating control for Timer 1. When set, timer/counter is enabled only while the INT1 pin is HIGH and the TR1 control bit is set. When cleared, Timer 1 is enabled when the TR1 control bit is set. 6 T1C/T Timer or counter select for Timer 1. Cleared for timer operation. Set for counter operation (input from T1 input pin). 5 T1M1 Mode select for Timer 1. 4 T1M0 3 T0GATE Gating control for Timer 0. When set, timer/counter is enabled only while the INT0 pin is HIGH and the TR0 control bit is set. When cleared, Timer 0 is enabled when the TR0 control bit is set. 2 T0C/T Timer or counter select for Timer 0. Cleared for timer operation. Set for counter operation (input from T0 input pin). 1 T0M1 Mode select for Timer 0. 0 T0M0 Table 15. TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating mode M1 M0 Operating mode 0 0 0 8048 timer ‘TLx’ serves as 5-bit prescaler. 0 1 1 16-bit timer/counter ‘THx’ and ‘TLx' are cascaded; there is no prescaler. 1 0 2 8-bit auto-reload timer/counter ‘THx’ holds a value which is to be reloaded into ‘TLx’ each time it overflows. 1 1 3 (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. 1 1 3 (Timer 1) timer/counter 1 stopped. Table 16. TCON - Timer/Counter control register (address 88H) bit allocation Bit addressable; reset value: 0000 0000B; reset source(s): any reset. Bit Symbol 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 27 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 17. TCON - Timer/Counter control register (address 88H) bit description Bit Symbol Description 7 TF1 Timer 1 overflow Flag. Set by hardware on timer/counter overflow. Cleared by hardware when the processor vectors to Timer 1 interrupt routine, or by software. 6 TR1 Timer 1 Run control bit. Set/cleared by software to turn timer/counter 1 on/off. 5 TF0 Timer 0 overflow Flag. Set by hardware on timer/counter overflow. Cleared by hardware when the processor vectors to Timer 0 interrupt routine, or by software. 4 TR0 Timer 0 Run control bit. Set/cleared by software to turn timer/counter 0 on/off. 3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge/LOW-state is detected. Cleared by hardware when the interrupt is processed, or by software. 2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/LOW-state that triggers external interrupt 1. 1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge/LOW-state is detected. Cleared by hardware when the interrupt is processed, or by software. 0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/LOW-state that triggers external interrupt 0. 6.4.1 Mode 0 Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a fixed divide-by-32 prescaler. Figure 7 shows Mode 0 operation. overflow osc/6 Tn pin C/T = 0 C/T = 1 control TLn (5-bits) THn (8-bits) TFn interrupt TRn TnGate INTn pin Fig 7. 002aaa519 Timer/counter 0 or 1 in Mode 0 (13-bit counter) In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TFn. The count input is enabled to the timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the special function register TCON (Table 17). The GATE bit is in the TMOD register. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1; see Figure 7. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 28 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.4.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used; see Figure 8. overflow C/T = 0 osc/6 Tn pin C/T = 1 control TLn (8-bits) THn (8-bits) TFn interrupt TRn TnGate INTn pin Fig 8. 002aaa520 Timer/counter 0 or 1 in Mode 1 (16-bit counter) 6.4.3 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TLn) with automatic reload, as shown in Figure 9. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1. C/T = 0 osc/6 Tn pin C/T = 1 control TLn (8-bits) overflow TFn interrupt reload TRn TnGate THn (8-bits) INTn pin Fig 9. 002aaa521 Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload) 6.4.4 Mode 3 When Timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in mode 3, the P89CV51RB2/RC2/RD2 can look like it has an additional timer. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 29 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI C/T = 0 osc/6 T0 pin control C/T = 1 TL0 (8-bits) overflow TH0 (8-bits) overflow TF0 interrupt TF1 interrupt TR0 TnGate INT0 pin osc/2 control TR1 002aaa522 Fig 10. Timer/counter 0 Mode 3 (two 8-bit counters) 6.5 Timer 2 Timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud rate generator which are selected according to Table 18 using T2CON (Table 19 and Table 20) and T2MOD (Table 21 and Table 22). Table 18. Timer 2 operating mode RCLK + TCLK CP/RL2 TR2 T2OE Mode 0 0 1 0 16-bit auto reload 0 1 1 0 16-bit capture 0 0 1 1 Programmable clock-out 1 X 1 0 Baud rate generator X X 0 X off Table 19. T2CON - Timer/Counter 2 control register (address C8H) bit allocation Bit addressable; reset value: 00H. Bit Symbol 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Table 20. T2CON - Timer/Counter 2 control register (address C8H) bit description Bit Symbol Description 7 TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1 or when Timer 2 is in Clock-out mode. 6 EXF2 Timer 2 external flag is set when Timer 2 is in capture, reload or baud rate mode, EXEN2 = 1 and a negative transition on T2EX occurs. If Timer 2 interrupt is enabled EXF2 = 1 causes the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. 5 RCLK Receive clock flag. When set, causes the UART to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 30 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 20. T2CON - Timer/Counter 2 control register (address C8H) bit description …continued Bit Symbol Description 4 TCLK Transmit clock flag. When set, causes the UART to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. 3 EXEN2 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. 2 TR2 Start/stop control for Timer 2. A logic 1 enables the timer to run. 1 C/T2 Timer or counter select. (Timer 2) 0 = internal timer (fosc / 6) 1 = external event counter (falling edge triggered; external clock’s maximum rate = fosc / 12) 0 CP/RL2 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Table 21. T2MOD - Timer 2 mode control register (address C9H) bit allocation Not bit addressable; reset value: XX00 0000B. Bit 7 6 5 4 3 2 1 0 Symbol - - - - - - T2OE DCEN Table 22. T2MOD - Timer 2 mode control register (address C9H) bit description Bit Symbol Description 7 to 2 - Reserved for future use. Should be set to 0 by user programs. 1 T2OE Timer 2 Output Enable bit. Used in programmable Clock-out mode only. 0 DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. 6.5.1 Capture mode In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overflowing sets bit TF2, the Timer 2 overflow bit. The Capture mode is illustrated in Figure 11. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit ET2 in the IE register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 31 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI OSC ÷6 C/T2 = 0 TL2 (8-bits) TF2 control C/T2 = 1 T2 pin TH2 (8-bits) TR2 capture transition detector timer 2 interrupt RCAP2L RCAP2H T2EX pin EXF2 control EXEN2 002aaa523 Fig 11. Timer 2 in Capture mode There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2 pin transitions or fosc / 6 pulses. Since once loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer 2 interrupt is signalled it has to be serviced before a new capture event on T2EX pin occurs. Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to the previously reported interrupt. 6.5.2 Auto-reload mode (up or down counter) In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (via C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Table 21 and Table 22). When reset is applied, DCEN = 0 and Timer 2 will default to counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 12 shows Timer 2 counting up automatically (DCEN = 0). OSC ÷6 C/T2 = 0 TL2 (8-bits) TF2 control C/T2 = 1 T2 pin TH2 (8-bits) TR2 reload transition detector timer 2 interrupt RCAP2L RCAP2H T2EX pin EXF2 control EXEN2 002aaa524 Fig 12. Timer 2 in Auto-reload mode (DCEN = 0) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 32 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (overflow flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Auto reload frequency when Timer 2 is counting up can be determined from Equation 1: SupplyFrequency ---------------------------------------------------------------------------65536 – ( RCAP2H , RCAP2L ) (1) Where SupplyFrequency is either fosc (C/T2 = 0) or frequency of signal on T2 pin (C/T2 = 1). If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 is 1. The microcontroller’s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 = 1: in the first machine cycle pin T2EX has to be sampled as 1; in the second machine cycle it has to be sampled as 0, and in the third machine cycle EXF2 will be set to 1. In Figure 13, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. toggle (down-counting reload value) OSC T2 pin ÷6 FFH FFH TL2 (8-bits) TH2 (8-bits) EXF2 C/T2 = 0 control C/T2 = 1 underflow timer 2 interrupt TF2 overflow TR2 RCAP2L RCAP2H count direction 1 = up 0 = down (up-counting reload value) T2EX pin 002aaa525 Fig 13. Timer 2 in Auto reload mode (DCEN = 1) When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 33 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.5.3 Programmable clock-out A 50 % duty cycle clock can be programmed to come out on pin T2 (P1[0], Clock-out mode). This pin, besides being a regular I/O pin, has two additional functions. It can be programmed: 1. To input the external clock for timer/counter 2, or 2. To output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency. To configure the timer/counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T2OE in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in Equation 2: OscillatorFrequency -----------------------------------------------------------------------------------------2 × ( 65536 – ( RCAP2H , RCAP2L ) ) (2) Where (RCAP2H, RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud rate generator. 6.5.4 Baud rate generator mode Bits TCLK and/or RCLK in T2CON allow the UART transmit and receive baud rates to be derived from either Timer 1 or Timer 2; see Section 6.6 for details. When TCLK = 0, Timer 1 is used as the UART transmit baud rate generator. When TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates, Timer 1 or Timer 2. Figure 14 shows Timer 2 in Baud rate generator mode: OSC ÷2 C/T2 = 0 TL2 (8-bits) TX/RX baud rate control C/T2 = 1 T2 pin TH2 (8-bits) reload TR2 transition detector RCAP2L RCAP2H T2EX pin EXF2 timer 2 interrupt control EXEN2 002aaa526 Fig 14. Timer 2 in Baud rate generator mode P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 34 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI The Baud rate generator mode is like the Auto-reload mode, when a roll-over in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below: Modes 1 and 3 baud rates = Timer 2 overflow rate / 16 The timer can be configured for either ‘timer’ or ‘counter’ operation. In many applications, it is configured for ‘timer' operation (C/T2 = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment at every machine cycle (i.e., 1⁄6 the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is shown in Equation 3: Modes 1 and 3 baud rates = OscillatorFrequency --------------------------------------------------------------------------------------------16 × ( 65536 – ( RCAP2H , RCAP2L ) ) (3) Where: (RCAP2H, RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 in Baud rate generator mode is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a roll-over in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the Baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer 2 is used as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer 2 is in the Baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 23 shows commonly used baud rates and how they can be obtained from Timer 2. 6.5.5 Summary of baud rate equations Timer 2 is in Baud rate generator mode: if Timer 2 is being clocked through pin T2 (P1[0]) the baud rate is: Baud rate = Timer 2 overflow rate / 16 If Timer 2 is being clocked internally, the baud rate is: Baud rate = fosc / (16 × (65536 − (RCAP2H, RCAP2L))) Where fosc = oscillator frequency To obtain the reload value for RCAP2H and RCAP2L, this equation can be rewritten as: RCAP2H, RCAP2L = 65536 − fosc / (16 × baud rate) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 35 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 23. Rate Timer 2-generated commonly used baud rates Oscillator frequency Timer 2 RCAP2H RCAP2L 750 kBd 12 MHz FF FF 19.2 kBd 12 MHz FF D9 9.6 kBd 12 MHz FF B2 4.8 kBd 12 MHz FF 64 2.4 kBd 12 MHz FE C8 600 Bd 12 MHz FB 1E 220 Bd 12 MHz F2 AF 600 Bd 6 MHz FD 8F 220 Bd 6 MHz F9 57 6.6 UART The UART operates in all standard modes. Enhancements over the standard 80C51 UART include framing error detection, and automatic address recognition. 6.6.1 Mode 0 Serial data enters and exits through RXD, and TXD outputs the shift clock. Only 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1⁄6 of the CPU clock frequency. The UART configured to operate in this mode outputs serial clock on the TXD line no matter whether it sends or receives data on the RXD line. 6.6.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1/Timer 2 overflow rate. 6.6.3 Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is transmitted, the 9th data bit (TB8 in special function register SCON) can be assigned the value of 0 or (e.g. the parity bit (P in special function register PSW) could be moved into bit TB8). When data is received, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. 6.6.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in mode 3 is variable and is determined by the Timer 1/Timer 2 overflow rate. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 36 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 24. SCON - Serial port control register (address 98H) bit allocation Bit addressable; reset value: 00H. Bit 7 6 5 4 3 2 1 0 Symbol SM0/FE SM1 SM2 REN TB8 RB8 TI RI Table 25. SCON - Serial port control register (address 98H) bit description Bit Symbol Description 7 SM0/FE The usage of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is SM0, which with SM1, defines the serial port mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared by valid frames but can only be cleared by software. (Note: It is recommended to set up UART mode bits SM0 and SM1 before setting SMOD0 to 1.) 6 SM1 With SM0, defines the serial port mode; see Table 26. 5 SM2 Enables the multiprocessor communication feature in modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. 4 REN Enables serial Reception. Set by software to enable reception. Clear by software to disable reception. 3 TB8 The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired. 2 RB8 In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is undefined. 1 TI Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the stop bit in the other modes, in any serial transmission. Must be cleared by software. 0 RI Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or approximately halfway through the stop bit time in all other modes. (See SM2 for exceptions). Must be cleared by software. Table 26. SCON - Serial port control register (address 98H) SM0/SM1 mode definition SM0, SM1 UART mode Baud rate 00 0: shift register CPU clock / 6 01 1: 8-bit UART variable 10 2: 9-bit UART CPU clock / 32 or CPU clock / 16 11 3: 9-bit UART variable 6.6.5 Framing error Framing Error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0, SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0 is set to 1. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 37 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.6.6 More about UART Mode 1 Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset to align its roll-overs with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and (b) either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. 6.6.7 More about UART Modes 2 and 3 Reception is performed in the same manner as in Mode 1. The signal to load special function register SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and (b) either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. 6.6.8 Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte: the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is 0. However, an address byte having the 9th bit set to 1 will interrupt all slaves, so that each slave can examine the received byte to see if it is being addressed or not. The addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that follow. The slaves that were not addressed leave their SM2 bits set and ignore the subsequent data bytes. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 38 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although it is preferable to use the Framing Error flag (FE). When the UART receives data in Mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 6.6.9 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled for the UART by setting the SM2 bit in SCON. In the 9-bit UART modes, Mode 2 and Mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the ‘given’ address or the ‘broadcast’ address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the broadcast address. Two special function registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are don’t care. The SADEN mask can be logically ANDed with the SADDR to create the given address which the master will use for addressing each of the slaves. Use of the given address allows multiple slaves to be recognized while excluding others. This device uses the methods presented in Figure 15 to determine if a given or broadcast address has been received or not. rx_byte(7) saddr(7) saden(7) . . . rx_byte(0) saddr(0) given_address_match saden(0) logic used by UART to detect 'given address' in received data saddr(7) saden(7) rx_byte(7) . . . saddr(0) saden(0) broadcast_address_match rx_byte(0) logic used by UART to detect 'given address' in received data 002aaa527 Fig 15. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor communications is enabled P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 39 of 76 NXP Semiconductors P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI The following examples help to show the versatility of this scheme. Example 1, slave 0: SADDR = 1100 0000 SADEN = 1111 1101 ---------------------------------------------------Given = 1100 00X0 Example 2, slave 1: SADDR = 1100 0000 SADEN = 1111 1110 ---------------------------------------------------Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0. Example 1, slave 0: SADDR = 1100 0000 SADEN = 1111 1001 ---------------------------------------------------Given = 1100 0XX0 Example 2, slave 1: SADDR = 1110 0000 SADEN = 1111 1010 ---------------------------------------------------Given = 1110 0X0X Example 3, slave 2: SADDR = 1100 0000 SADEN = 1111 1100 ---------------------------------------------------Given = 1100 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The broadcast address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FFH. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all don’t cares as well as a broadcast P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 40 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI address of all don’t cares. This effectively disables the automatic addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature. 6.7 Serial Peripheral Interface (SPI) 6.7.1 SPI features • • • • • • • Master or slave operation 10 MHz bit frequency (max) LSB first or MSB first data transfer Four programmable bit rates End of transmission (SPIF) Write-collision flag protection (WCOL) Wake-up from Idle mode (Slave mode only) 6.7.2 SPI description The serial peripheral interface allows high-speed synchronous data transfer between the P89CV51RB2/RC2/RD2 and peripheral devices or between several P89CV51RB2/RC2/RD2 devices. Figure 16 shows the correspondence between master and slave SPI devices. The SPICLK pin is the clock output and input for the Master and Slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin of the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPI interrupt Flag (SPIF) is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and the SPI interrupt enable bit, ES, are both set. An external master drives the Slave Select input pin (SS) LOW to select the SPI module as a slave. If SS has not been driven LOW, then the slave SPI unit is not active and the MOSI pin can also be used as an input port pin. CPHA and CPOL control the phase and polarity of the SPI clock (SCK). Figure 17 and Figure 18 show the four possible combinations of these two bits. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 41 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI MSB master LSB MISO MSB slave LSB MISO 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER MOSI SPI CLOCK GENERATOR MOSI SCK SCK SS SS VDD VSS 002aaa528 Fig 16. SPI master-slave interconnection Table 27. SPCR - SPI control register (address D5H) bit allocation Reset source(s): any reset; reset value: 0000 0000B. Bit Symbol Table 28. 7 6 5 4 3 2 1 0 SPIE SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SPCR - SPI control register (address D5H) bit description Bit Symbol Description 7 SPIE SPI interrupt enable. If both SPIE = 1 and ES = 1, SPI interrupts are enabled. 6 SPEN SPI enable bit. When set enables SPI. 5 DORD Data transmission order. 0 = MSB first; 1 = LSB first in data transmission. 4 MSTR Master/Slave select. 1 = Master mode, 0 = Slave mode. 3 CPOL Clock polarity. 1 = SPICLK is HIGH when idle (active LOW), 0 = SPICLK is LOW when idle (active HIGH). 2 CPHA Clock Phase control bit. 1 = shift-triggered on the trailing edge of the clock; 0 = shift-triggered on the leading edge of the clock. 1 SPR1 SPI clock Rate select bit 1. Along with SPR0 controls the SPICLK rate of the device when a master. SPR1 and SPR0 have no effect on the slave; see Table 29. 0 SPR0 SPI clock Rate select bit 0. Along with SPR1 controls the SPICLK rate of the device when a master. SPR1 and SPR0 have no effect on the slave; see Table 29. Table 29. SPR1 SPCR - SPI control register (address D5H) clock rate selection SPR0 SPICLK = fosc divided by 6-clock mode 12-clock mode 0 0 2 4 0 1 8 16 1 0 32 64 1 1 64 128 P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 42 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 30. SPSR - SPI Status Register (address AAH) bit allocation Reset source(s): any reset; reset value: 0000 0000B. Bit Symbol Table 31. 7 6 5 4 3 2 1 0 SPIF WCOL - - - - - - SPSR - SPI Status Register (address AAH) bit description Bit Symbol Description 7 SPIF SPI interrupt flag. Upon completion of data transfer, this bit is set to 1. If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is cleared by software. 6 WCOL Write Collision flag. Set if the SPI data register is written to during data transfer. This bit is cleared by software. 5 to 0 - Reserved for future use. Should be set to 0 by user programs. SCK cycle # (for reference) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from master) MISO (from slave) MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SS (to slave) 002aaa529 Fig 17. SPI transfer format with CPHA = 0 SCK cycle # (for reference) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from master) MISO (from slave) MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB SS (to slave) 002aaa530 Fig 18. SPI transfer format with CPHA = 1 6.8 Watchdog timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer Reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user must write 01EH and 0E1H, in sequence, to the WDTRST SFR. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. There is no P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 43 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI way to disable the WDT, except through a reset (either a hardware reset or a WDT overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the RST pin. When the WDT is enabled (and thus running) the user needs to reset it by writing 01EH and 0E1H, in sequence, to the WDTRST SFR to avoid WDT overflow. The 14-bit counter reaches overflow when it reaches 16383 (3FFFH) and this will reset the device. The WDT’s counter cannot be read or written. When the WDT overflows it will generate an output pulse at the RST pin with a duration of 98 oscillator periods in 6-clock mode or 196 oscillator periods in 12-clock mode. 6.9 PCA The PCA includes a special 16-bit timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse-width modulator. Each module has a pin associated with it: Module 0 is connected to CEX0, module 1 to CEX1, etc. Registers CH and CL contain the current value of the free-running up-counting 16-bit PCA timer. The PCA timer is a common time base for all five modules and can be programmed to run at: 1⁄6 the oscillator frequency, 1⁄2 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1[2]). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR; see Table 32 and Table 33. 16 bits MODULE0 P1[3]/CEX0 MODULE1 P1[4]/CEX1 MODULE2 P1[5]/CEX2 MODULE3 P1[6]/CEX3 MODULE4 P1[7]/CEX4 16 bits PCA TIMER/COUNTER time base for PCA modules Module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit PWM - watchdog timer (module 4 only) 002aab913 Fig 19. PCA In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during Idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The watchdog timer function is implemented in module 4 of PCA. The CCON SFR contains the run control bit for the PCA (CR) and the flags for the PCA timer (CF) and each module (CCF[4:0]). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 44 of 76 NXP Semiconductors P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags can only be cleared by software. All the modules share one interrupt vector. The PCA interrupt system is shown in Figure 20. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that control the mode that each module will operate in. The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the CCFn flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module; see Figure 20. PWM (CCAPMn.1) enables the PWM mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode, these registers are used to control the duty cycle of the output. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 45 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI CF CR - CCF4 CCF3 CCF2 CCF1 CCON (D8H) CCF0 PCA TIMER/COUNTER MODULE0 IE.6 EC MODULE1 IE.7 EA to interrupt priority decoder MODULE2 MODULE3 MODULE4 CMOD.0 CCAPMn.0 ECF ECCFn 002aaa533 Fig 20. PCA interrupt system Table 32. CMOD - PCA counter mode register (address D9H) bit allocation Not bit addressable; reset value: 00H. Bit Symbol Table 33. 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF CMOD - PCA counter mode register (address D9H) bit description Bit Symbol Description 7 CIDL Counter Idle control. CIDL = 0 programs the PCA counter to continue functioning during Idle mode; CIDL = 1 programs it to be gated off during Idle mode. 6 WDTE WatchDog Timer Enable. WDTE = 0 disables watchdog timer function on module 4; WDTE = 1 enables it. 5 to 3 - Reserved for future use. Should be set to 0 by user programs. 2 to 1 CPS1, CPS0 PCA Count Pulse Select; see Table 34. 0 ECF PCA Enable Counter overflow interrupt Flag. ECF = 1 enables CF bit in CCON to generate an interrupt; ECF = 0 disables that function. Table 34. CMOD - PCA counter mode register (address D9H) count pulse select CPS1 CPS0 Select PCA input 0 0 0 internal clock, fosc / 6 P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 46 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 34. CMOD - PCA counter mode register (address D9H) count pulse select …continued CPS1 CPS0 Select PCA input 0 1 1 internal clock, fosc / 6 1 0 2 Timer 0 overflow 1 1 3 external clock at pin P1[2]/ECI (maximum rate = fosc / 4) Table 35. CCON - PCA counter control register (address D8H) bit allocation Bit addressable; reset value: 00H. Bit Symbol Table 36. 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON - PCA counter control register (address D8H) bit description Bit Symbol Description 7 CF PCA Counter overflow Flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. 6 CR PCA Counter Run control. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. 5 - Reserved for future use. Should be set to 0 by user programs. 4 CCF4 PCA Module 4 interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. 3 CCF3 PCA Module 3 interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. 2 CCF2 PCA Module 2 interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. 1 CCF1 PCA Module 1 interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. 0 CCF0 PCA Module 0 interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. Table 37. CCAPMn - PCA modules compare/capture register (address CCAPM0 DAH, CCAPM1 DBH, CCAPM2 DCH, CCAPM3 DDH, CCAPM4 DEH) bit allocation Not bit addressable; reset value: 00H. Bit 7 6 5 4 3 2 1 0 Symbol - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Table 38. CCAPMn - PCA modules compare/capture register (address CCAPM0 DAH, CCAPM1 DBH, CCAPM2 DCH, CCAPM3 DDH, CCAPM4 DEH) bit description Bit Symbol Description 7 - Reserved for future use. Should be set to 0 by user programs. 6 ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. 5 CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. 4 CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. 3 MATn Match. When MATn = 1 a match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 47 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 38. CCAPMn - PCA modules compare/capture register (address CCAPM0 DAH, CCAPM1 DBH, CCAPM2 DCH, CCAPM3 DDH, CCAPM4 DEH) bit description Bit Symbol Description 2 TOGn Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn pin to toggle. 1 PWMn Pulse Width Modulation mode. PWMn = 1 enables the CEXn pin to be used as a pulse-width modulated output. 0 ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. Table 39. PCA module modes (CCAPMn register) ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module function 0 0 0 0 0 0 0 no operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative-edge trigger on CEXn X 1 1 0 0 0 X 16-bit capture by any transition on CEXn 1 0 0 1 0 0 X 16-bit software timer 1 0 0 1 1 0 X 16-bit high-speed output 1 0 0 0 0 1 0 8-bit PWM 1 0 0 1 X 0 X watchdog timer 6.9.1 PCA capture mode To use one of the PCA modules in the Capture mode (Figure 21), either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs, the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 48 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) PCA interrupt (to CCFn) PCA timer/counter CH CL capture CEXn CCAPnH CCAPnL - ECOMn 0 CAPPn CAPNn MATn TOGn PWMn 0 0 0 ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) 002aaa538 Fig 21. PCA Capture mode If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 6.9.2 16-bit software timer mode The PCA modules can be used as software timers (Figure 22) by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 49 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI CF write to CCAPnH 0 1 - CCF4 reset CCAPnH write to CCAPnL CR CCF3 CCF2 CCF1 CCF0 (to CCFn) CCAPnL enable CCON (D8H) PCA interrupt match 16-BIT COMPARATOR CH CL PCA timer/counter - ECOMn CAPPn CAPNn MATn TOGn PWMn 0 0 1 0 0 ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) 002aaa539 Fig 22. PCA Compare mode 6.9.3 High-speed output mode In this mode (Figure 23) the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 50 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI CF write to CCAPnH CR 0 1 CCF4 reset CCAPnH write to CCAPnL - CCF3 CCF2 CCF1 CCF0 CCON (D8H) (to CCFn) CCAPnL enable PCA interrupt match 16-BIT COMPARATOR CH CL PCA timer/counter toggle CEXn - ECOMn CAPPn CAPNn MATn TOGn PWMn 0 0 1 0 0 ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) 002aaa540 Fig 23. PCA High-speed output mode 6.9.4 Pulse width modulator mode All of the PCA modules can be used as PWM outputs (Figure 24). Output frequency depends on the source for the PCA timer. CCAPnH 0 CCAPnL CL < CCAPnL enable CEXn 8-BIT COMPARATOR CL ≥ CCAPnL 1 CL PCA timer/counter - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 1 0 0 0 0 1 1 CCAPMn, n = 0 to 4 (DAH to DEH) 002aaa541 Fig 24. PCA PWM mode All of the modules will have the same output frequency because they all share only one PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPnL. When the value of the PCA CL SFR is less than the value in the P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 51 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI module’s CCAPnL SFR, the output will be LOW; when it is equal to, or greater, the output will be HIGH. When CL overflows from FFH to 00H, CCAPnL is reloaded with the value in CCAPnH. This allows the PWM to be updated without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable PWM mode. 6.9.5 PCA watchdog timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 24 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven HIGH. User’s software then must periodically change (CCAP4H, CCAP4L) to keep a match from occurring with the PCA timer (CH, CL). This code is given in the subroutine WATCHDOG shown below. In order to hold off the reset, the user has three options: • Periodically change the compare value so it will never match the PCA timer. • Periodically change the PCA timer value so it will never match the compare values. • Disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in the third option. If the program counter ever reaches an undesired value, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember that the PCA timer is the time base for all modules; changing the time base for other modules is not recommended. Thus, in most applications the first option is best. ;CALL the following WATCHDOG subroutine periodically. CLR EA ;Hold off interrupts MOV CCAP4L,#00 ;Next compare value is within 255 counts of current PCA timer value MOV CCAP4H,CH SETB EA ;Re-enable interrupts RET Do not use this routine as part of an interrupt service routine, because if the program counter would enter an infinite loop, still interrupts will be serviced and the watchdog will continually keep getting reset. Because this would defeat the purpose of the watchdog, it is recommended that this subroutine is called from the main program within 216 PCA timer counts. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 52 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.10 Security bits The security bits protect against software piracy and prevent the contents of the flash from being read by unauthorized parties in Parallel programmer mode and ISP mode. Since the end application might need to erase pages and read from the code memory, the security bits have no effect in IAP mode. However, the security bits’ programmed/erased state may be read using IAP function calls allowing the end-user code to limit access, if desired. The security bits and their effects are shown in Table 40. Note: On this device, MOVC instructions executed from external code memory are prevented from fetching code bytes from internal code memory. Table 40. Security bit functions Security bit Description 1 Write protect. When programmed, prohibits further erasing or programming, except to program other security bits or a chip erase. 2 Read protect. When programmed, inhibits reading of user code memory. 3 External execution inhibit. When programmed, prevents any execution of instructions from external code memory. 6.11 Interrupt priority and polling sequence The device supports eight interrupt sources under a four-level priority scheme. Table 41 summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector; see Figure 25. Table 41. Interrupt polling sequence Description Interrupt flag Vector address Interrupt enable Interrupt priority Service priority Wake-up Power-down External Interrupt 0 IE0 0003H EX0 PX0/PX0H 1 (highest) yes T0 TF0 000BH ET0 PT0/PT0H 2 no External Interrupt 1 IE1 0013H EX1 PX1/PX1H 3 yes T1 TF1 001BH ET1 PT1/PT1H 4 no UART TI/RI 0023H ES PS/PSH 5 no SPI SPIF 0023H ES PS/PSH 5 no PCA CF/CCFn 0033H EC PPC/PPCH 7 no T2 TF2, EXF2 003BH ET2 PT2/PT2H 6 no P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 53 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI highest priority interrupt IP/IPH/IPA/IPAH registers IE and IEA registers 0 INT0# IT0 IE0 1 TF0 interrupt polling sequence 0 INT1# IT1 IE1 1 TF1 ECF CF CCFn ECCFn RI TI SPIF SPIE TF2 EXF2 lowest priority interrupt global disable individual enables 002aac965 Fig 25. Interrupt structure Table 42. IE - Interrupt enable register 0 (address A8H) bit allocation Bit addressable; reset value: 00H. Bit Symbol Table 43. 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 IE - Interrupt enable register 0 (address A8H) bit description Bit Symbol Description 7 EA Interrupt Enable. EA = 1: interrupt(s) can be serviced; EA = 0: interrupt servicing disabled. 6 EC PCA interrupt Enable. 5 ET2 Timer 2 interrupt Enable. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 54 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 43. IE - Interrupt enable register 0 (address A8H) bit description …continued Bit Symbol Description 4 ES Serial port interrupt Enable. 3 ET1 Timer 1 overflow interrupt Enable. 2 EX1 External interrupt 1 Enable. 1 ET0 Timer 0 overflow interrupt Enable. 0 EX0 External interrupt 0 Enable. Table 44. IP - Interrupt priority low register (address B8H) bit allocation Bit addressable; reset value: 00H. Bit 7 6 5 4 3 2 1 0 Symbol - PPC PT2 PS PT1 PX1 PT0 PX0 Table 45. IP - Interrupt priority low register (address B8H) bit description Bit Symbol Description 7 - Reserved for future use. Should be set to 0 by user programs. 6 PPC PCA interrupt Priority Low. 5 PT2 Timer 2 interrupt Priority Low. 4 PS Serial Port interrupt Priority Low. 3 PT1 Timer 1 interrupt Priority Low. 2 PX1 External interrupt 1 Priority Low. 1 PT0 Timer 0 interrupt Priority Low. 0 PX0 External interrupt 0 Priority Low. Table 46. IPH - Interrupt priority high register (address B7H) bit allocation Not bit addressable; reset value: 00H. Bit 7 6 5 4 3 2 1 0 Symbol - PPCH PT2H PSH PT1H PX1H PT0H PX0H Table 47. IPH - Interrupt priority high register (address B7H) bit description Bit Symbol Description 7 - Reserved for future use. Should be set to 0 by user programs. 6 PPCH PCA interrupt Priority High. 5 PT2H Timer 2 interrupt Priority High. 4 PSH Serial Port interrupt Priority High. 3 PT1H Timer 1 interrupt Priority High. 2 PX1H External interrupt 1 Priority High. 1 PT0H Timer 0 interrupt Priority High. 0 PX0H External interrupt 0 Priority High. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 55 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.12 Power-saving modes The device provides two power-saving modes of operation for applications where power consumption is critical. The two modes are Idle and Power-down; see Table 48. 6.12.1 Idle mode Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the program counter is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode. The device exits Idle mode through either a system interrupt or a hardware reset. When exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exiting the Interrupt Service Routine (ISR), the interrupted program resumes execution at the instruction immediately following the instruction which invoked the Idle mode. A hardware reset starts the device similar to a power-on reset. 6.12.2 Power-down mode The Power-down mode is entered by setting the PD bit in the PCON register. In the Power-down mode, the clock is stopped and external interrupts are active for level-sensitive interrupts only. SRAM contents are retained during power-down, the minimum VDD level is 4.5 V. The device exits Power-down mode through either an enabled external level-sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding an external interrupt pin LOW restarts the oscillator, the signal must hold LOW at least 1024 clock cycles before bringing back HIGH to complete the exit. When the interrupt signal is restored to logic VIH, the interrupt service routine program execution resumes at the instruction immediately following the instruction which invoked Power-down mode. A hardware reset starts the device similar to a power-on reset. To exit properly out of power-down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). Table 48. Power-saving modes Mode Initiated by State of MCU Exited by Idle Software (Set IDL bit in PCON) MOV PCON, #01H CLK is running. Interrupts, serial port and timers/counters are active. Program counter is stopped. ALE and PSEN signals at a HIGH-state during Idle. All registers remain unchanged. Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruction, program resumes execution beginning at the instruction following the one that invoked Idle mode. A hardware reset restarts the device similar to a power-on reset. Power-down Software (Set PD bit in PCON) MOV PCON, #02H CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN signals at a LOW-state during power-down. External interrupts are only active for level-sensitive interrupts, if enabled. Enabled external level-sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits Power-down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power-down mode. A hardware reset restarts the device similar to a power-on reset. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 56 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.13 System clock and clock options 6.13.1 Clock input options and recommended capacitor values for oscillator Shown in Figure 26 and Figure 27 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven. At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF once the external signal meets the VIL and VIH specifications. Resonator manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. Table 49 shows the typical values for C1 and C2 versus resonator type for various frequencies. Table 49. Recommended values for C1 and C2 by crystal type Resonator C1 = C 2 Quartz 20 pF to 30 pF Ceramic 40 pF to 50 pF C2 XTAL2 XTAL1 C1 VSS 002aaa545 Fig 26. Oscillator characteristics (using the on-chip oscillator) n.c. XTAL2 external oscillator signal XTAL1 VSS 002aaa546 Fig 27. Oscillator characteristics (external clock drive) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 57 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 6.13.1.1 Clock control register (CKCON) By default, the device runs at twelve clock cycles per machine cycle (12-clock mode). The device may be run at 6 clock cycles per machine cycle (6-clock mode) by programming of either a non-volatile bit (FX2) or an SFR bit (X2); see Table 52 “Clock modes”. If the FX2 non-volatile bit is programmed, the device will run in 6-clock mode and the X2 SFR bit has no effect. If the FX2 bit is erased, then the clock mode is controlled by the X2 SFR bit. Table 50. CKCON - Clock control register (address 8FH) bit allocation Not bit addressable; reset value 00H. Bit Symbol Table 51. 7 6 5 4 3 2 1 0 SPIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 CKCON - Clock control register (address 8FH) bit description Bit Symbol Description 7 SPIX2 SPI clock; 0 = 6 clock cycles for each SPI clock cycle; 1 = 12 clock cycles 6 WDX2 Watchdog clock; 0 = 6 clock cycles for each WDT clock cycle; 1 = 12 clock cycles 5 PCAX2 PCA clock; 0 = 6 clock cycles for each PCA clock cycle; 1 = 12 clock cycles 4 SIX2 UART clock; 0 = 6 clock cycles for each UART clock cycle; 1 = 12 clock cycles 3 T2X2 Timer 2 clock; 0 = 6 clock cycles for each Timer 2 clock cycle; 1 = 12 clock cycles 2 T1X2 Timer 1 clock; 0 = 6 clock cycles for each Timer 1 clock cycle; 1 = 12 clock cycles 1 T0X2 Timer 0 clock; 0 = 6 clock cycles for each Timer 0 clock cycle; 1 = 12 clock cycles 0 X2 CPU clock; 0 = 12 clock cycles for each machine cycle; 1 = 6 clock cycles Table 52. Clock modes FX2 clock mode bit X2 bit CPU clock mode Peripheral clock mode bit (e.g. T0X2) Mode erased 0 12-clock (default) X 12-clock (default) 1 6-clock programmed X 6-clock P89CV51RB2_RC2_RD2_3 Product data sheet 0 6-clock 1 12-clock 0 6-clock 1 12-clock © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 58 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 7. Limiting values Table 53. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Parameters are valid over operating temperature range unless otherwise specified; all voltages are with respect to VSS unless otherwise noted. Symbol Parameter Conditions Min Max Unit Tamb(bias) Tstg bias ambient temperature −55 +125 °C storage temperature −65 +150 °C VI input voltage on EA pin to VSS −0.5 +14 V Vn voltage on any other pin except VSS; with respect to VDD −0.5 VDD + 0.5 V IOL(I/O) LOW-level output current per input/output pin - 15 mA Ptot(pack) total power dissipation (per package) - 1.5 W based on package heat transfer, not device power consumption 8. Static characteristics Table 54. Static characteristics Tamb = −40 °C to +85 °C; VDD = 4.5 V to 5.5 V; VSS = 0 V. Symbol Min Typ Max Unit JEDEC Standard A117 [1] 10000 - - cycles tret(fl) flash memory retention time JEDEC Standard A103 [1] 100 - - years Ilatch I/O latch-up current [1] 100 + IDD - - mA Vth(HL) HIGH-LOW threshold voltage −0.5 - +0.2VDD − 0.1 V Vth(LH) LOW-HIGH threshold voltage except XTAL1, RST 0.2VDD + 0.9 - VDD + 0.5 V VOL LOW-level output voltage VDD = 4.5 V; except PSEN, ALE - - 0.4 V - - 0.45 V VDD − 0.7 - - V VDD − 0.7 - - V −1 - −75 µA - - −650 µA nendu(fl) Parameter endurance of flash memory Conditions JEDEC Standard 78 [2][3][4] IOL = 1.6 mA VDD = 4.5 V; ALE, PSEN IOL = 3.2 mA VOH HIGH-level output voltage VDD = 4.5 V; ports 1, 2, 3, 4 [5] IOH = −30 µA VDD = 4.5 V; port 0 in External bus mode, ALE, PSEN IOH = −3.2 mA IIL LOW-level input current VI = 0.4 V; ports 1, 2, 3, 4 [6] ITHL HIGH-LOW transition current VI = 2 V; ports 1, 2, 3, 4 ILI input leakage current 0.45 V < VI < VDD − 0.3 V; port 0 - - ±10 µA 0 V < VI < 6 V - - 10 µA P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 59 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 54. Static characteristics …continued Tamb = −40 °C to +85 °C; VDD = 4.5 V to 5.5 V; VSS = 0 V. Symbol Parameter Conditions Rpd pull-down resistance on pin RST Ciss input capacitance 1 MHz; Tamb = 25 °C; VI = 0 V IDD(oper) operating supply current IDD(idle) IDD(pd) Idle mode supply current Power-down mode supply current Min Typ Max Unit 40 - 225 kΩ - - 15 pF fosc = 12 MHz - - 11.5 mA fosc = 40 MHz - - 50 mA Programming and erase mode - - 70 mA fosc = 12 MHz - - 8.5 mA fosc = 40 MHz - - 42 mA minimum VDD = 4.5 V - - 90 µA [7] [1] This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. [2] Under steady state (non-transient) conditions, IOL must be externally limited as follows: a) Maximum IOL per 8-bit port: 26 mA b) Maximum IOL total for all outputs: 71 mA c) If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. [3] Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input. [4] Load capacitance for Port 0, ALE and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. [5] Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD − 0.7 V specification when the address bits are stabilizing. [6] Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VI is approximately 2 V. [7] Pin capacitance is characterized but not tested. Capacitance on pin EA = 25 pF (max.). P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 60 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 002aaa813 50 (1) IDD (mA) 40 (2) 30 20 (3) 10 (4) 0 0 10 20 30 40 internal clock frequency (MHz) (1) Maximum active IDD (2) Maximum idle IDD (3) Typical active IDD (4) Typical idle IDD Fig 28. IDD as a function of frequency P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 61 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 9. Dynamic characteristics Table 55. Dynamic characteristics Over operating conditions: load capacitance for port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. Tamb = −40 °C to +85 °C; VDD = 4.5 V to 5.5 V; VSS = 0 V.[1][2] Symbol Parameter oscillator frequency fosc Conditions Min Typ Max Unit 12-clock mode 0 - 40 MHz 6-clock mode 0 - 20 MHz IAP 0.25 - 40 MHz tLHLL ALE pulse width 2Tcy(clk) − 15 - - ns tAVLL address valid to ALE LOW time Tcy(clk) − 15 - - ns tLLAX address hold after ALE LOW time Tcy(clk) − 15 - - ns tLLIV ALE LOW to valid instruction in time - - 4Tcy(clk) − 45 ns tLLPL ALE LOW to PSEN LOW time Tcy(clk) − 15 - - ns tPLPH PSEN pulse width 3Tcy(clk) − 15 - - ns tPLIV PSEN LOW to valid instruction in time - - 3Tcy(clk) − 50 ns tPXIX input instruction hold after PSEN time 0 - - ns tPXIZ input instruction float after PSEN time - - Tcy(clk) − 15 ns tPXAV PSEN to address valid time Tcy(clk) − 8 - - ns tAVIV address to valid instruction in time - - 5Tcy(clk) − 60 ns tPLAZ PSEN LOW to address float time - - 10 ns tRLRH RD LOW pulse width 6Tcy(clk) − 30 - - ns tWLWH WR LOW pulse width 6Tcy(clk) − 30 - - ns tRLDV RD LOW to valid data in time - - 5Tcy(clk) − 50 ns tRHDX data hold after RD time 0 - - ns tRHDZ data float after RD time - - 2Tcy(clk) − 12 ns tLLDV ALE LOW to valid data in time - - 8Tcy(clk) − 50 ns tAVDV address to valid data in time - - 9Tcy(clk) − 75 ns tLLWL ALE LOW to RD or WR LOW time 3Tcy(clk) − 15 - 3Tcy(clk) + 15 ns tAVWL address to RD or WR LOW time 4Tcy(clk) − 30 - - ns tWHQX data hold after WR time Tcy(clk) − 20 - - ns tQVWH data output valid to WR HIGH time 7Tcy(clk) − 50 - - ns tRLAZ RD LOW to address float time - - 0 ns tWHLH RD or WR HIGH to ALE HIGH time Tcy(clk) − 15 - Tcy(clk) + 15 ns [1] Tcy(clk) = 1 / fosc. [2] Calculated values are for 6-clock mode only. P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 62 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 9.1 Explanation of symbols Each timing symbol used in Figure 29 to Figure 33 has 5 characters. The first character is always a ‘t’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A — Address C — Clock D — Input data H — Logic level HIGH I — Instruction (program memory contents) L — Logic level LOW or ALE P — PSEN Q — Output data R — RD signal T — cycle Time V — Valid W — WR signal X — No longer a valid logic level Z — High impedance (float) Example: tAVLL = Address valid to ALE LOW time tLLPL = ALE LOW to PSEN LOW time tLHLL ALE tPLPH tAVLL tLLIV tLLPL tPLIV PSEN tPXAV tPLAZ tLLAX port 0 tPXIZ tPXIX A0 to A7 INSTR IN A0 to A7 tAVIV port 2 A8 to A15 A8 to A15 002aaa548 Fig 29. External program memory read cycle P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 63 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI ALE tWHLH PSEN tLLDV tLLWL RD tAVLL tRLRH tLLAX tRHDZ tRLAZ tRHDX tRLDV A0 to A7 from RI to DPL port 0 DATA IN A0 to A7 from PCL INSTR IN tAVWL tAVDV P2.0 to P2.7 or A8 to A15 from DPH port 2 A0 to A15 from PCH 002aaa549 Fig 30. External data memory read cycle tLHLL ALE tWHLH PSEN tLLWL WR tWLWH tLLAX tWHQX tAVLL tQVWH port 0 A0 to A7 from RI or DPL DATA OUT A0 to A7 from PCL INSTR IN tAVWL port 2 P2[7:0] or A8 to A15 from DPH A8 to A15 from PCH 002aaa550 Fig 31. External data memory write cycle P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 64 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI Table 56. External clock drive Symbol Parameter Oscillator Unit 40 MHz Variable Min Max Min Max fosc oscillator frequency - - 0 40 MHz Tcy(clk) clock cycle time 25 - - - ns tCHCX clock HIGH time 8.75 - 0.35Tcy(clk) 0.65Tcy(clk) ns tCLCX clock LOW time 8.75 - 0.35Tcy(clk) 0.65Tcy(clk) ns tCLCH clock rise time - 10 - - ns tCHCL clock fall time - 10 - - ns tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 32. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) Table 57. Serial port timing Symbol Parameter Oscillator Unit 40 MHz Variable Min Max Min Max TXLXL serial port clock cycle time 0.3 - 12Tcy(clk) - µs tQVXH output data set-up to clock rising edge time 117 - 10Tcy(clk) − 133 - ns tXHQX output data hold after clock rising edge time 0 - 2Tcy(clk) − 50 - ns tXHDX input data hold after clock rising edge 0 time - 0 - ns tXHDV input data valid to clock rising edge time 117 - 10Tcy(clk) − 133 ns - P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 65 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI instruction 0 1 2 3 4 5 6 7 8 ALE TXLXL clock tXHQX tQVXH output data 0 write to SBUF input data 1 2 3 4 5 6 7 tXHDX set TI tXHDV valid valid valid valid valid valid valid valid clear RI set RI 002aaa552 Fig 33. Shift register mode timing waveforms Table 58. Symbol SPI interface timing Parameter Conditions Variable clock fosc = 18 MHz Unit Min Max Min Max 0 Tcy(clk) / 4 0 10 4Tcy(clk) - 222 - ns fSPI SPI operating frequency TSPICYC SPI cycle time tSPILEAD SPI enable lead time see Figure 36, 37 250 - 250 - ns tSPILAG SPI enable lag time see Figure 36, 37 250 - 250 - ns tSPICLKH SPICLK HIGH time see Figure 34, 35, 36, 37 2Tcy(clk) - 111 - ns tSPICLKL SPICLK LOW time see Figure 34, 35, 36, 37 2Tcy(clk) - 111 - ns tSPIDSU SPI data set-up time master or slave; see Figure 34, 35, 36, 37 100 - 100 - ns tSPIDH SPI data hold time master or slave; see Figure 34, 35, 36, 37 100 - 100 - ns see Figure 34, 35, 36, 37 MHz tSPIA SPI access time see Figure 36, 37 0 80 0 80 ns tSPIDIS SPI disable time see Figure 36, 37 0 160 - 160 ns tSPIDV SPI enable to output data valid time see Figure 34, 35, 36, 37 - 111 - 111 ns tSPIOH SPI output data hold time see Figure 34, 35, 36, 37 0 - 0 - ns tSPIR SPI rise time see Figure 34, 35, 36, 37 SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 ns SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 ns SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns tSPIF SPI fall time see Figure 34, 35, 36, 37 P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 66 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI SS TSPICYC tSPIF tSPICLKH tSPICLKL tSPIR SPICLK (CPOL = 0) (output) tSPIF tSPIR tSPICLKL tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in MSB/LSB in tSPIDV MOSI (output) tSPIOH tSPIDV tSPIF tSPIR master MSB/LSB out master LSB/MSB out 002aaa908 Fig 34. SPI master timing (CPHA = 0) SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in MSB/LSB in tSPIDV MOSI (output) tSPICLKL tSPIOH tSPIDV tSPIF tSPIR master MSB/LSB out master LSB/MSB out 002aaa909 Fig 35. SPI master timing (CPHA = 1) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 67 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI SS tSPIR tSPIR TSPICYC tSPILEAD tSPIF tSPICLKH tSPICLKL tSPIR tSPILAG SPICLK (CPOL = 0) (input) tSPIF tSPICLKL tSPICLKH SPICLK (CPOL = 1) (input) tSPIA MISO (output) tSPIOH tSPIOH tSPIDV tSPIDV tSPIOH slave MSB/LSB out tSPIDSU MOSI (input) tSPIR tSPIDH slave LSB/MSB out tSPIDSU tSPIDSU MSB/LSB in tSPIDIS not defined tSPIDH LSB/MSB in 002aaa910 Fig 36. SPI slave timing (CPHA = 0) SS tSPIR tSPILEAD tSPIR TSPICYC tSPIF tSPICLKL tSPIR tSPILAG tSPICLKH SPICLK (CPOL = 0) (input) tSPIF tSPICLKL SPICLK (CPOL = 1) (input) tSPIR tSPICLKH tSPIOH tSPIOH tSPIDV tSPIDV tSPIOH tSPIDV tSPIDIS tSPIA MISO (output) not defined tSPIDSU MOSI (input) slave LSB/MSB out slave MSB/LSB out tSPIDH tSPIDSU MSB/LSB in tSPIDSU tSPIDH LSB/MSB in 002aaa911 Fig 37. SPI slave timing (CPHA = 1) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 68 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI to tester to DUT CL 002aaa555 Fig 38. Test load example VDD P0 VDD RST VDD IDD VDD 8 EA DUT clock signal (n.c.) XTAL2 XTAL1 VSS 002aaa556 All other pins disconnected Fig 39. IDD test condition, Active mode VDD P0 RST VDD IDD 8 VDD EA DUT clock signal (n.c.) XTAL2 XTAL1 VSS 002aaa557 All other pins disconnected Fig 40. IDD test condition, Idle mode P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 69 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI VDD = 4.5 V VDD P0 RST DUT (n.c.) VDD IDD 8 VDD EA XTAL2 XTAL1 VSS 002aad019 All other pins disconnected Fig 41. IDD test condition, Power-down mode P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 70 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 10. Package outline TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm SOT376-1 c y X A 33 23 34 22 ZE e E HE A A2 w M (A 3) A1 θ bp pin 1 index Lp L detail X 12 44 11 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.2 0.15 0.05 1.05 0.95 0.25 0.45 0.30 0.18 0.12 10.1 9.9 10.1 9.9 0.8 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1 0.75 0.45 0.2 0.2 0.1 Z D(1) Z E(1) 1.2 0.8 1.2 0.8 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC SOT376-1 137E08 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 02-03-14 MS-026 Fig 42. Package outline SOT376-1 (TQFP44) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 71 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 β 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.51 0.25 3.05 0.53 0.33 0.180 0.02 0.165 0.01 0.12 0.021 0.032 0.656 0.656 0.05 0.013 0.026 0.650 0.650 0.63 0.59 0.63 0.59 Lp v w y 1.44 1.02 0.18 0.18 0.1 ZD(1) ZE(1) max. max. 2.16 β 2.16 45 o 0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT187-2 112E10 MS-018 EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 43. Package outline SOT187-2 (PLCC44) P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 72 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 11. Abbreviations Table 59. Abbreviations Acronym Description ALE Address Latch Enable CPU Central Processing Unit DPTR Data PoinTeR DUT Device Under Test EPROM Erasable Programmable Read-Only Memory EMI Electro-Magnetic Interference ID IDentifier IAP In-Application Programming ISP In-System Programming LSB Least Significant Bit MCU MicroController Unit MSB Most Significant Bit PCA Programmable Counter Array PCH Programmable Counter High PCL Programmable Counter Low PWM Pulse-Width Modulator RAM Random Access Memory RC Resistance-Capacitance SFR Special Function Register SPI Serial Peripheral Interface SRAM Static Random Access Memory UART Universal Asynchronous Receiver/Transmitter WDT WatchDog Timer P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 73 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 12. Revision history Table 60. Revision history Document ID Release date P89CV51RB2_RC2_RD2_3 20090825 Modifications: • • • • • • • Change notice Supersedes Product data sheet - P89CV51RB2_RC2_RD2_2 Table 4: AUXR1, replaced ‘-’ with ‘ENBOOT’. Table 4: CMOD, replaced ‘C1H’ with ‘D9H’. Table 8: Replaced ‘-’ with ‘ENBOOT’. Table 32: Replaced ‘C1H’ with ‘D9H’. Table 33: Replaced ‘C1H’ with ‘D9H’. Table 34: Replaced ‘C1H’ with ‘D9H’. P89CV51RB2_RC2_RD2_2 20090422 Modifications: Data sheet status Product data sheet P89CV51RB2_RC2_RD2_1 Section 6.2.1: Corrected value for EXTRAM bit setting. P89CV51RB2_RC2_RD2_1 20071005 Product data sheet P89CV51RB2_RC2_RD2_3 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 74 of 76 P89CV51RB2/RC2/RD2 NXP Semiconductors 80C51 with 1 kB RAM, SPI 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] P89CV51RB2_RC2_RD2_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 25 August 2009 75 of 76 NXP Semiconductors P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI 15. Contents 1 2 2.1 2.2 2.3 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 Comparison to P89C51RB2/RC2/RD2 devices 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 9 Special function registers . . . . . . . . . . . . . . . . . 9 Memory organization . . . . . . . . . . . . . . . . . . . 13 Expanded data RAM addressing . . . . . . . . . . 13 Dual data pointers. . . . . . . . . . . . . . . . . . . . . . 15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 17 Flash organization . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Boot block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-on reset code execution. . . . . . . . . . . . 18 Hardware activation of the bootloader . . . . . . 18 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Using ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IAP method . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 26 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 31 Auto-reload mode (up or down counter) . . . . . 32 Programmable clock-out . . . . . . . . . . . . . . . . . 34 Baud rate generator mode . . . . . . . . . . . . . . . 34 Summary of baud rate equations . . . . . . . . . . 35 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 37 More about UART Mode 1 . . . . . . . . . . . . . . . 38 More about UART Modes 2 and 3 . . . . . . . . . 38 Multiprocessor communications . . . . . . . . . . . 38 Automatic address recognition . . . . . . . . . . . . 39 6.7 6.7.1 6.7.2 6.8 6.9 6.9.1 6.9.2 6.9.3 6.9.4 6.9.5 6.10 6.11 6.12 6.12.1 6.12.2 6.13 6.13.1 Serial Peripheral Interface (SPI). . . . . . . . . . . SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . SPI description . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . PCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCA capture mode. . . . . . . . . . . . . . . . . . . . . 16-bit software timer mode. . . . . . . . . . . . . . . High-speed output mode . . . . . . . . . . . . . . . . Pulse width modulator mode . . . . . . . . . . . . . PCA watchdog timer . . . . . . . . . . . . . . . . . . . Security bits . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt priority and polling sequence . . . . . . Power-saving modes . . . . . . . . . . . . . . . . . . . Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down mode . . . . . . . . . . . . . . . . . . . . . System clock and clock options . . . . . . . . . . . Clock input options and recommended capacitor values for oscillator . . . . . . . . . . . . . 6.13.1.1 Clock control register (CKCON) . . . . . . . . . . . 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 8 Static characteristics . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 9.1 Explanation of symbols . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information . . . . . . . . . . . . . . . . . . . . . . 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information . . . . . . . . . . . . . . . . . . . . 15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 41 43 44 48 49 50 51 52 53 53 56 56 56 57 57 58 59 59 62 63 71 73 74 75 75 75 75 75 75 76 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 August 2009 Document identifier: P89CV51RB2_RC2_RD2_3