PHILIPS 74LVC1G38GF

74LVC1G38
2-input NAND gate; open drain
Rev. 03 — 27 August 2007
Product data sheet
1. General description
The 74LVC1G38 provides a 2-input NAND function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
u JESD8-7 (1.65 V to 1.95 V)
u JESD8-5 (2.3 V to 2.7 V)
u JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Open drain outputs
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +125 °C.
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G38GW
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G38GV
−40 °C to +125 °C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
74LVC1G38GM
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
74LVC1G38GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code
74LVC1G38GW
YB
74LVC1G38GV
YB
74LVC1G38GM
YB
74LVC1G38GF
YB
5. Functional diagram
Y
1
A
1
Y 4
2
B
A
&
4
2
001aab717
Fig 1. Logic symbol
B
Fig 2. IEC logic symbol
74LVC1G38_3
Product data sheet
GND
001aab716
001aab715
Fig 3. Logic diagram
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
2 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
6. Pinning information
6.1 Pinning
74LVC1G38
74LVC1G38
A
1
B
2
GND
3
5
VCC
A
1
6
VCC
B
2
5
n.c.
GND
4
4
3
Y
74LVC1G38
Y
1
6
VCC
B
2
5
n.c.
GND
3
4
Y
001aab832
001aaf180
Transparent top view
Transparent top view
001aab718
Fig 4. Pin configuration SOT353-1
and SOT753
A
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SOT353-1/SOT753
SOT886/SOT891
A
1
1
data input
B
2
2
data input
GND
3
3
ground (0 V)
Y
4
4
data output
n.c.
-
5
not connected
VCC
5
6
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
A
B
L
L
Z
L
H
Z
H
L
Z
H
H
L
[1]
Y
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
3 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
IIK
input clamping current
VI
input voltage
IOK
output clamping current
[1]
output voltage
VO
VI < 0 V
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
−0.5
+6.5
V
-
±50
mA
Active mode
[1][2]
−0.5
+6.5
V
Power-down mode
[1][2]
−0.5
+6.5
V
-
±50
mA
VO > VCC or VO < 0 V
IO
output current
VO = 0 V to VCC
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
[3]
−65
+150
°C
-
300
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
Conditions
Min
Typ
Max
Unit
supply voltage
1.65
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
Active mode
0
-
5.5
V
Disable mode; VCC = 1.65 V to 5.5 V
0
-
5.5
V
Power-down mode; VCC = 0 V
0
-
5.5
V
Tamb
ambient temperature
−40
-
+125
°C
∆t/∆V
input transition rise and VCC = 1.65 V to 2.7 V
fall rate
VCC = 2.7 V to 5.5 V
-
-
20
ns/V
-
-
10
ns/V
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
4 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = −40 °C to +85
VIH
VIL
VOL
Conditions
Min
Typ
Max
Unit
°C[1]
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VCC = 1.65 V to 1.95 V
0.65 × VCC -
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35 × VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3 × VCC
V
VI = VIH or VIL
-
-
-
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
II
input leakage current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
±0.1
±5
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND;
VCC = 5.5 V
-
±0.1
±10
µA
IOFF
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
±0.1
±10
µA
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
0.1
10
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V; per pin
-
5
500
µA
CI
input capacitance
-
2.5
-
pF
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 1.65 V to 1.95 V
0.65 × VCC -
-
V
VCC = 2.3 V to 2.7 V
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35 × VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3 × VCC
V
74LVC1G38_3
Product data sheet
-
V
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
5 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
VOL
VI = VIH or VIL
-
-
-
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
LOW-level output voltage
Unit
IO = 4 mA; VCC = 1.65 V
-
-
0.70
V
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.80
V
II
input leakage current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
-
±100
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND;
VCC = 5.5 V
-
-
±200
µA
IOFF
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
-
±200
µA
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
-
200
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V; per pin
-
-
5000
µA
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
propagation delay
tpd
power dissipation
capacitance
CPD
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
3.0
10.0
1.0
12.5
ns
VCC = 2.3 V to 2.7 V
0.5
1.8
6.0
0.5
7.5
ns
VCC = 2.7 V
0.5
2.5
5.0
0.5
6.5
ns
VCC = 3.0 V to 3.6 V
0.5
2.3
4.5
0.5
5.7
ns
VCC = 4.5 V to 5.5 V
0.5
1.5
3.9
0.5
4.9
ns
-
6
-
-
-
pF
A, B to Y; see Figure 7
VCC = 3.3 V;
VI = GND to VCC
[2]
[3]
[1]
Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPZL and tPLZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74LVC1G38_3
Product data sheet
Unit
Typ[1]
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
6 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
12. AC waveforms
VI
A, B input
VM
GND
t PLZ
t PZL
VCC
Y output
VM
VOL
VX
001aab719
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The input (A, B) to output (Y) propagation delays.
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
1.65 V to 1.95 V
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
2.3 V to 2.7 V
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
4.5 V to 5.5 V
0.5 × VCC
0.5 × VCC
VOL + 0.3 V
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
7 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
8 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
E
D
SOT353-1
A
X
c
y
HE
v M A
Z
5
4
A2
A
(A3)
A1
θ
1
Lp
3
L
e
w M
bp
detail X
e1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
e1
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.1
0
1.0
0.8
0.15
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
1.3
2.25
2.0
0.425
0.46
0.21
0.3
0.1
0.1
0.60
0.15
7°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT353-1
REFERENCES
IEC
JEDEC
JEITA
MO-203
SC-88A
EUROPEAN
PROJECTION
ISSUE DATE
00-09-01
03-02-19
Fig 9. Package outline SOT353-1 (TSSOP5)
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
9 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
Plastic surface-mounted package; 5 leads
SOT753
D
E
B
y
A
X
HE
5
v M A
4
Q
A
A1
c
1
2
3
Lp
detail X
bp
e
w M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.100
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT753
JEITA
SC-74A
EUROPEAN
PROJECTION
ISSUE DATE
02-04-16
06-03-16
Fig 10. Package outline SOT753 (SC-74A)
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
10 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
4
e1
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 11. Package outline SOT886 (XSON6)
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
11 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
1
SOT891
b
3
2
4×
(1)
L
L1
e
6
5
4
e1
e1
6×
A
(1)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
Fig 12. Package outline SOT891 (XSON6)
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
12 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G38_3
20070827
Product data sheet
-
74LVC1G38_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
In Section 10 “Static characteristics”, changed conditions for input leakage and supply current.
Figure 12 “Package outline SOT891 (XSON6)” updated.
74LVC1G38_2
20060913
Product data sheet
-
74LVC1G38_1
74LVC1G38_1
20041018
Product data sheet
-
-
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
13 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74LVC1G38_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 27 August 2007
14 of 15
74LVC1G38
NXP Semiconductors
2-input NAND gate; open drain
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 August 2007
Document identifier: 74LVC1G38_3