74LVC2G08 Dual 2-input AND gate Rev. 06 — 4 September 2007 Product data sheet 1. General description The 74LVC2G08 provides a 2-input AND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Complies with JEDEC standard: ◆ JESD8-7 (1.65 V to 1.95 V) ◆ JESD8-5 (2.3 V to 2.7 V) ◆ JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: ◆ HBM EIA/JESD22-A114E exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G08DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G08DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74LVC2G08GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm 74LVC2G08GM −40 °C to +125 °C XQFN8 plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-1 4. Marking Table 2. Marking Type number Marking code 74LVC2G08DP V08 74LVC2G08DC V08 74LVC2G08GT V08 74LVC2G08GM V08 5. Functional diagram 1 1 1A 2 1B 5 2A 6 2B 1Y 7 2 2Y 3 5 & 7 & 3 6 mna724 mna725 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y B mna221 Fig 3. Logic diagram (one gate) 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 2 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 6. Pinning information 6.1 Pinning 74LVC2G08 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aae981 Fig 4. Pin configuration TSSOP8 and VSSOP8 74LVC2G08 8 VCC 1B 2 7 1Y 2Y 3 6 2B 1Y 1 2B 2A 8 1 7 1A 2 6 1B 3 5 2Y 4 1A VCC terminal 1 index area 74LVC2G08 4 5 2A GND GND 001aae982 Transparent top view 001aae983 Transparent top view Fig 5. Pin configuration XSON8 Fig 6. Pin configuration XQFN8 6.2 Pin description Table 3. Pin description Symbol Pin Description TSSOP8, VSSOP8 XSON8 XQFN8 1A 1 1 7 data input 1B 2 2 6 data input 2Y 3 3 5 data output GND 4 4 4 ground (0 V) 2A 5 5 3 data input 2B 6 6 2 data input 1Y 7 7 1 data output VCC 8 8 8 supply voltage 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 3 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 7. Functional description Table 4. Function table[1] Input Output nA nB nY L X L X L L H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit −0.5 +6.5 V [1] −0.5 +6.5 V [1] −0.5 VCC + 0.5 V [1][2] −0.5 +6.5 V VI < 0 V −50 - mA Active mode Power-down mode IIK input clamping current IOK output clamping current VO < 0 V or VO > VCC - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 300 mW Tamb = −40 °C to +125 °C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition. [3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Min Typ Max Unit supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage Active mode 0 - VCC V Power-down mode 0 - 5.5 V −40 - +125 °C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V Tamb ambient temperature ∆t/∆V input transition rise and fall rate Conditions 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 4 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH VIL VOH VOL Conditions Min VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V Typ Max Unit 0.65 × VCC - - V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 1.2 1.53 - V IO = −8 mA; VCC = 2.3 V 1.9 2.13 - V IO = −12 mA; VCC = 2.7 V 2.2 2.50 - V IO = −24 mA; VCC = 3.0 V 2.3 2.60 - V IO = −32 mA; VCC = 4.5 V 3.8 4.10 - V °C[1] HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V - ±0.1 ±5 µA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 µA ∆ICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 µA Ci input capacitance - 2.5 - pF Tamb = −40 °C to +125 °C VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V 74LVC2G08_6 Product data sheet - V © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 5 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions Typ Max Unit IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VOL Min IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V IO = −32 mA; VCC = 4.5 V 3.4 - - V IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V II input leakage current - - ±20 µA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 40 µA ∆ICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5000 µA [1] VI = 5.5 V or GND; VCC = 0 V to 5.5 V All typical values are measured at Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8. Symbol Parameter −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.2 9.0 1.0 11.3 ns VCC = 2.3 V to 2.7 V 0.5 2.2 5.1 0.5 6.4 ns VCC = 2.7 V 1.0 2.5 5.3 1.0 6.7 ns VCC = 3.0 V to 3.6 V 0.5 2.1 4.7 0.5 5.9 ns VCC = 4.5 V to 5.5 V 0.5 1.7 3.8 0.5 4.8 ns - 14.4 - - - pF propagation delay nA, nB to nY; see Figure 7 tpd power dissipation capacitance CPD per gate; VI = GND to VCC [2] [3] [1] Typical values are measured at nominal VCC and at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 74LVC2G08_6 Product data sheet −40 °C to +125 °C Unit Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 6 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI VM nA, nB input GND t PHL t PLH VOH VM nY output VOL mna224 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Input (nA, nB) to output (nY) propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 7 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator VEXT = Test voltage for switching times Fig 8. Load circuitry for switching times Table 10. Test data Supply voltage Input VCC VI tr, tf Load CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC2G08_6 Product data sheet VEXT © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 8 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 9. Package outline SOT505-2 (TSSOP8) 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 9 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA MO-187 EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 10 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 11. Package outline SOT833-1 (XSON8) 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 11 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-16 05-11-25 Fig 12. Package outline SOT902-1 (XQFN8) 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 12 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G08_6 20070904 Product data sheet - 74LVC2G08_5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. In Section 10 “Static characteristics”, changed conditions for input leakage and supply current. 74LVC2G08_5 20060515 Product data sheet - 74LVC2G08_4 74LVC2G08_4 20050201 Product specification - 74LVC2G08_3 74LVC2G08_3 20040915 Product specification - 74LVC2G08_2 74LVC2G08_2 20031020 Product specification - 74LVC2G08_1 74LVC2G08_1 20030825 Product specification - - 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 13 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74LVC2G08_6 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 06 — 4 September 2007 14 of 15 74LVC2G08 NXP Semiconductors Dual 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 September 2007 Document identifier: 74LVC2G08_6