74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 7 — 8 February 2013 Product data sheet 1. General description The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: VCC(A): 0.8 V to 3.6 V VCC(B): 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 500 Mbit/s (1.8 V to 3.3 V translation) 320 Mbit/s (<1.8 V to 3.3 V translation) 320 Mbit/s (translate to 2.5 V or 1.8 V) 280 Mbit/s (translate to 1.5 V) 240 Mbit/s (translate to 1.2 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC2T45DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74AVC2T45DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74AVC2T45GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 1.95 0.5 mm 74AVC2T45GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1 0.5 mm 74AVC2T45GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; body 3 2 0.5 mm 74AVC2T45GN 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 1.0 0.35 mm SOT1116 74AVC2T45GS 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1.0 0.35 mm SOT1203 SOT1089 4. Marking Table 2. Marking Type number Marking code[1] 74AVC2T45DP B45 74AVC2T45DC B45 74AVC2T45GT B45 74AVC2T45GF B5 74AVC2T45GD B45 74AVC2T45GN B5 74AVC2T45GS B5 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 2 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 5. Functional diagram DIR 5 DIR 1A 2 1A 7 1B 1B 2A 3 2A 6 2B 2B VCC(A) VCC(B) VCC(A) VCC(B) 001aag577 Fig 1. 001aag578 Logic symbol Fig 2. Logic diagram 6. Pinning information 6.1 Pinning 74AVC2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 001aag579 Fig 3. Pin configuration SOT505-2 and SOT765-1 74AVC2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 74AVC2T45 DIR VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 001aag580 001aai261 Transparent top view Transparent top view Fig 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74AVC2T45 Product data sheet Fig 5. Pin configuration SOT996-2 All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 3 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 6.2 Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage A (referenced to pins 1A, 2A and DIR) 1A 2 data input or output 2A 3 data input or output GND 4 ground (0 V) DIR 5 direction control 2B 6 data input or output 1B 7 data input or output VCC(B) 8 supply voltage B (referenced to pins 1B and 2B) 7. Functional description Table 4. Function table[1] Supply voltage Input Input/output[2] VCC(A), VCC(B) DIR[3] nA nB 0.8 V to 3.6 V L nA = nB input 0.8 V to 3.6 V H input nB = nA GND[4] X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [3] The DIR input circuit is referenced to VCC(A). [4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into Suspend mode. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 4 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage A VCC(B) supply voltage B IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Max Unit 0.5 +4.6 V 0.5 +4.6 V 50 - mA 0.5 +4.6 V mA 50 - [1][2][3] 0.5 VCCO + 0.5 V [1] 0.5 +4.6 V VO < 0 V Active mode Min Suspend or 3-state mode IO output current VO = 0 V to VCCO - 50 mA ICC supply current ICC(A) or ICC(B) - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot [1] Tamb = 40 C to +125 C The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] [4] For TSSOP8 package: above 55 C the value of Ptot derates linearly at 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Min Max Unit VCC(A) supply voltage A Conditions 0.8 3.6 V VCC(B) supply voltage B 0.8 3.6 V VI input voltage 0 3.6 V output voltage VO Active mode [1] Suspend or 3-state mode Tamb t/V ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 [2] 0 VCCO V 0 3.6 V 40 +125 C - 5 ns/V © NXP B.V. 2013. All rights reserved. 5 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 10. Static characteristics Table 7. Typical static characteristics at Tamb = 25 C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V Min Typ Max Unit - 0.69 - V - 0.07 - V - 0.025 0.25 A - 0.5 2.5 A II input leakage current DIR input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - 0.1 1 A B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - 0.1 1 A [3] CI input capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 1.0 - pF CI/O input/output capacitance A and B port; Suspend mode; VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V - 4.0 - pF [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter IOZ includes the input leakage current. Table 8. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCCI = 0.8 V 0.70VCCI - 0.70VCCI - V VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V VCCI = 3.0 V to 3.6 V 2 - 2 - V VCC(A) = 0.8 V 0.70VCC(A) - 0.70VCC(A) - V VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V VCC(A) = 3.0 V to 3.6 V 2 - 2 - V data input DIR input 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 6 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage 40 C to +85 C Conditions 40 C to +125 C Min Max Min Max Unit data input VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.9 - 0.9 V VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.9 - 0.9 V VCCO 0.1 - VCCO 0.1 - V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - 0.85 - V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - 1.05 - V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - 1.2 - V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - 1.75 - V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - 2.3 - V - 0.1 - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - 0.25 - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - 0.35 - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - 0.45 - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - 0.55 - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - 0.7 - 0.7 V - 1 - 1.5 A - 5 - 7.5 A DIR input VOH VOL HIGH-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V LOW-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V II input leakage current DIR input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - 5 - 35 A B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - 5 - 35 A 74AVC2T45 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 7 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 8 - 11.5 A VCC(A) = 3.6 V; VCC(B) = 0 V - 8 - 11.5 A VCC(A) = 0 V; VCC(B) = 3.6 V 2 - 8 - A - 8 - 11.5 A VCC(A) = 3.6 V; VCC(B) = 0 V 2 - 8 - A VCC(A) = 0 V; VCC(B) = 3.6 V - 8 - 11.5 A - 16 - 23 A supply current A port; VI = 0 V or VCCI; IO = 0 A B port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter IOZ includes the input leakage current. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 8 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 11. Dynamic characteristics Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions VCC(B) 0.8 V tpd [1] 1.8 V 2.5 V 3.3 V 15.5 8.1 7.6 7.7 8.4 9.2 ns B to A 15.5 12.7 12.3 12.2 12.0 11.8 ns DIR to A 12.2 12.2 12.2 12.2 12.2 12.2 ns DIR to B 11.7 7.9 7.6 8.2 8.7 10.2 ns enable time ten 1.5 V propagation delay A to B disable time tdis 1.2 V Unit DIR to A 27.2 20.6 19.9 20.4 20.7 22.0 ns DIR to B 27.7 20.3 19.8 19.9 20.6 21.4 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter tpd [1] Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V propagation delay A to B 15.5 12.7 12.3 12.2 12.0 11.8 ns B to A 15.5 8.1 7.6 7.7 8.4 9.2 ns enable time ten VCC(A) 0.8 V disable time tdis Conditions DIR to A 12.2 4.9 3.8 3.7 2.8 3.4 ns DIR to B 11.7 9.2 9.0 8.8 8.7 8.6 ns DIR to A 27.2 17.3 16.6 16.5 17.1 17.8 ns DIR to B 27.7 17.6 16.1 15.9 14.8 15.2 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter power dissipation capacitance CPD [1] Conditions VCC(A) and VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A port: (direction A to B); B port: (direction B to A) 1 2 2 2 2 2 pF A port: (direction B to A); B port: (direction A to B) 9 11 11 12 14 17 pF CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = . 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 9 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions VCC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max 0.5 5.7 0.5 6.1 ns VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B 1.0 9.0 0.7 6.8 0.6 6.1 B to A 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns tdis disable time DIR to A 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns DIR to B 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns DIR to A - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns DIR to B - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns A to B 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns B to A 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns enable time ten VCC(A) = 1.4 V to 1.6 V propagation delay tpd disable time tdis enable time ten DIR to A 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns DIR to B 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns DIR to A - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns DIR to B - 14.3 - 11.7 - 10.9 - 10.0 - 9.8 ns VCC(A) = 1.65 V to 1.95 V propagation delay A to B 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns B to A 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns tdis disable time DIR to A 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns DIR to B 1.8 7.7 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns ten enable time DIR to A - 13.8 - 10.3 - 10.2 - 8.4 - 8.9 ns DIR to B - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis propagation delay A to B 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns B to A 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns disable time DIR to A 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns DIR to B 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns DIR to A - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns DIR to B - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns 0.5 2.8 0.5 2.4 ns enable time ten VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B 1.0 7.1 0.5 4.5 0.5 3.7 B to A 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns DIR to B 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns DIR to A - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns DIR to B - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 10 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions VCC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns B to A 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns tdis disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns DIR to B 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns DIR to A - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns DIR to B - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns A to B 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns B to A 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns enable time ten VCC(A) = 1.4 V to 1.6 V propagation delay tpd disable time tdis enable time ten DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns DIR to B 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns DIR to A - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns DIR to B - 15.8 - 13.0 - 12.1 - 11.1 - 10.9 ns VCC(A) = 1.65 V to 1.95 V propagation delay A to B 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns B to A 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns tdis disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns DIR to B 1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns ten enable time DIR to A - 15.3 - 11.4 - 11.3 - 9.3 - 9.9 ns DIR to B - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis propagation delay A to B 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns B to A 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns DIR to B 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns DIR to A - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns DIR to B - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns enable time ten VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns B to A 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns tdis disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns DIR to B 1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns DIR to A - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns DIR to B - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 11 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12. Waveforms VI VM nA, nB input GND tPLH tPHL VOH VM nB, nA output 001aak114 VOL Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The data input (nA, nB) to output (nB, nA) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 14. Enable and disable times Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.1 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH 0.15 V 3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 12 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 8. Table 15. Test circuit for measuring switching times Test data Supply voltage Input VCC(A), VCC(B) VI[1] t/V[2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3] 1.1 V to 1.6 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO 1.65 V to 2.7 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO 3.0 V to 3.6 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO [1] Load VEXT VCCI is the supply voltage associated with the data input port. [2] dV/dt 1.0 V/ns [3] VCCO is the supply voltage associated with the output port. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 13 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in Figure 9 is an example of the 74AVC2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC(A) VCC1 VCC2 74AVC2T45 1A 2A GND VCC1 1 8 2 7 3 6 4 5 system-1 VCC(B) VCC2 1B 2B DIR VCC2 system-2 001aag581 Fig 9. Unidirectional logic level-shifting application Table 16. 74AVC2T45 Product data sheet Unidirectional logic level-shifting application Pin Name Function Description 1 VCC(A) VCC1 supply voltage of system-1 (0.8 V to 3.6 V) 2 1A OUT1 output level depends on VCC1 voltage 3 2A OUT2 output level depends on VCC1 voltage 4 GND GND device GND 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 2B IN2 input threshold value depends on VCC2 voltage 7 1B IN1 input threshold value depends on VCC2 voltage 8 VCC(B) VCC2 supply voltage of system-2 (0.8 V to 3.6 V) All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 14 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13.2 Bidirectional logic level-shifting application Figure 10 shows the 74AVC2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 VCC2 VCC1 VCC2 74AVC2T45 I/O-1 PULL-UP/DOWN VCC(A) 8 1 1A 2A GND 2 7 3 6 4 5 VCC(B) PULL-UP/DOWN I/O-2 1B 2B DIR DIR CTRL DIR CTRL system-2 system-1 001aag582 System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. Fig 10. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 17. Bidirectional logic level-shifting application[1][2] State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on the pull-up or pull-down. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on the pull-up or pull-down. 4 L input output system-2 data to system-1 [1] [2] System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 15 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. Typical total supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 A 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 A 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 A 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 A 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 A 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 A 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 A 13.4 Enable times The enable times for the 74AVC2T45 are calculated from the following formulas: • ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA) • ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVC2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 16 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 14. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 11. Package outline SOT505-2 (TSSOP8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 17 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 12. Package outline SOT765-1 (VSSOP8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 18 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 13. Package outline SOT833-1 (XSON8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 19 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.35 0.40 0.04 0.20 1.40 1.05 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Fig 14. Package outline SOT1089 (XSON8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 20 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.1 sot996-2_po Outline version References IEC JEDEC JEITA European projection Issue date 07-12-21 12-11-20 SOT996-2 Fig 15. Package outline SOT996-2 (XSON8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 21 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Fig 16. Package outline SOT1116 (XSON8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 22 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 2 1 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Fig 17. Package outline SOT1203 (XSON8) 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 23 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 15. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVC2T45 v.7 20130208 Product data sheet - 74AVC2T45 v.6 Modifications: • For type number 74AVC2T45GD XSON8U has changed to XSON8. 74AVC2T45 v.6 20111208 Product data sheet - 74AVC2T45 v.5 74AVC2T45 v.5 20101130 Product data sheet - 74AVC2T45 v.4 74AVC2T45 v.4 20090505 Product data sheet - 74AVC2T45 v.3 74AVC2T45 v.3 20090129 Product data sheet - 74AVC2T45 v.2 74AVC2T45 v.2 20080620 Product data sheet - 74AVC2T45 v.1 74AVC2T45 v.1 20070703 Product data sheet - - 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 24 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 25 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AVC2T45 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 February 2013 © NXP B.V. 2013. All rights reserved. 26 of 27 74AVC2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 14 Unidirectional logic level-shifting application . 14 Bidirectional logic level-shifting application. . . 15 Power-up considerations . . . . . . . . . . . . . . . . 16 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact information. . . . . . . . . . . . . . . . . . . . . 26 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 February 2013 Document identifier: 74AVC2T45