2N7002K TrenchMOS™ logic level FET Rev. 01 — 20 October 2003 Product data M3D088 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. 1.2 Features ■ Logic level compatible ■ Very fast switching ■ Subminiature surface mount package ■ Gate-source ESD protection diodes. 1.3 Applications ■ Relay driver ■ High speed line driver. 1.4 Quick reference data ■ VDS ≤ 60 V ■ Ptot ≤ 0.83 W ■ ID ≤ 340 mA ■ RDSon ≤ 3.9 Ω. 2. Pinning information Table 1: Pinning - SOT23, simplified outline and symbol Pin Description 1 gate (g) 2 source (s) 3 drain (d) Simplified outline Symbol d 3 g 1 2 Top view MSB003 03ab60 SOT23 s 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 3. Ordering information Table 2: Ordering information Type number 2N7002K Package Name Description Version SOT23 Plastic surface mounted package; 3 leads. SOT23 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 60 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 60 V VGS gate-source voltage (DC) - ±15 V ID drain current (DC) Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 - 340 mA Tsp = 100 °C; VGS = 10 V; Figure 2 - 215 mA IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 680 mA Ptot total power dissipation Tsp = 25 °C; Figure 1 - 0.83 W Tstg storage temperature −65 +150 °C Tj junction temperature −65 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp = 25 °C - 340 mA ISM peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs - 680 mA - 1 kV Electrostatic discharge voltage Vesd electrostatic discharge voltage Human Body Model 1; C = 100 pF; R = 1.5 kΩ © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 2 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 03aa17 120 03aa25 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 0 200 50 100 150 Tsp (°C) P tot P der = ----------------------- × 100% P ° 200 Tsp (°C) ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. Fig 2. Normalized continuous drain current as a function of solder point temperature. 03an66 1 Limit RDSon = VDS/ ID tp = 10 µ s ID (A) 100 µ s 10-1 1 ms DC 10 ms 100 ms 10-2 1 10 VDS (V) 102 Tsp = 25 °C; IDM is single pulse; VGS = 10 V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 3 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Figure 4 Rth(j-a) thermal resistance from junction to ambient Min Typ Max Unit - - 150 K/W 350 - K/W minimum footprint; mounted on a printed-circuit board 5.1 Transient thermal impedance 03aa39 103 Zth(j-sp) (K/W) 102 δ = 0.5 0.2 0.1 10 0.05 δ= P 0.02 single pulse tp T t tp T 1 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 4 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage V(BR)GSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 10 µA; VGS = 0 V Tj = 25 °C 60 75 - V Tj = −55 °C 55 - - V 16 22 - V IG = ±1 mA; VDS = 0 V ID = 1 mA; VDS = VGS; Figure 9 V Tj = 25 °C 1 2 - V Tj = 150 °C 0.6 - - V Tj = −55 °C - - 3.5 V VDS = 48 V; VGS = 0 V Tj = 25 °C - 0.01 1 µA Tj = 150 °C - - 10 µA - 50 500 nA IGSS gate-source leakage current VGS = ±10 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 10 V; ID = 500 mA; Figure 7 and 8 Tj = 25 °C - 2.8 3.9 Ω Tj = 150 °C - 5.2 7.2 Ω VGS = 4.5 V; ID = 200 mA; Figure 7 and 8 - 3.8 5.3 Ω VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 11 - 13 40 pF - 8 30 pF - 4 10 pF - 3 10 ns - 9 15 ns - 0.93 1.5 V - 30 - ns - 30 - nC Dynamic characteristics Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance ton turn-on time toff turn-off time VDD = 50 V; RL = 250 Ω; VGS = 10 V; RG = 50 Ω; RGS = 50 Ω Source-drain diode VSD source-drain (diode forward) voltage IS = 300 mA; VGS = 0 V; Figure 12 trr reverse recovery time Qr recovered charge IS = 300 mA; dIS/dt = −100 A/µs; VGS = 0 V; VR = 25 V © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 5 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 03an70 0.5 ID (A) VGS = 10V Tj = 25 °C 03an72 0.5 6V ID (A) 0.4 VDS > ID x RDSon 0.4 4.5 V 0.3 0.3 4V 0.2 150 °C 0.2 Tj = 25 °C 3.5 V 0.1 0.1 3V 0 0 0 0.5 1 1.5 2 VDS (V) Tj = 25 °C 0 2 4 VGS (V) Tj = 25 °C and 150 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03an71 10 03aa28 2.4 Tj = 25 °C VGS = 3.5 V RDSon 6 a (Ω) 8 4V 6 1.8 4.5 V 1.2 4 6V 10 V 0.6 2 0 0 0 0.1 0.2 0.3 0.4 ID (A) 0.5 -60 60 120 180 Tj (°C) Tj = 25 °C R DSon a = ---------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data 0 Rev. 01 — 20 October 2003 6 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 03aa34 2.4 ID (A) 10-2 VGS(th) typ (V) 03aa37 10-1 1.8 10-3 min typ 1.2 min 10-4 0.6 10-5 10-6 0 -60 0 60 120 Tj (°C) 180 0 0.6 1.2 1.8 VGS (V) 2.4 Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03aa46 102 C (pF) Ciss 10 Coss Crss 1 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 7 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 03an73 0.5 IS (A) 0.4 03ab09 15 ID = 0.5A VGS = 0 V VGS VDD = 48 V (V) Tj = 25 °C 10 0.3 0.2 5 150 °C 0.1 Tj = 25 °C 0 0 0 0.3 0.6 0.9 VSD (V) 1.2 Tj = 25 °C and 150 °C; VGS = 0 V 0 0.6 0.9 QG (nC) 1.2 ID = 0.5 A; VDD = 48 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data 0.3 Rev. 01 — 20 October 2003 8 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 7. Package outline Plastic surface mounted package; 3 leads SOT23 D E B A X HE v M A 3 Q A A1 1 2 e1 bp c w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max. bp c D E e e1 HE Lp Q v w mm 1.1 0.9 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 1.9 0.95 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 OUTLINE VERSION SOT23 REFERENCES IEC JEDEC EIAJ TO-236AB EUROPEAN PROJECTION ISSUE DATE 97-02-28 99-09-13 Fig 14. SOT23. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 9 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 8. Revision history Table 6: Revision history Rev Date 01 20031020 CPCN Description Product data (9397 750 11703) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Product data Rev. 01 — 20 October 2003 10 of 12 2N7002K Philips Semiconductors TrenchMOS™ logic level FET 9. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11703 Rev. 01 — 20 October 2003 11 of 12 Philips Semiconductors 2N7002K TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 5.1 6 7 8 9 10 11 12 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 October 2003 Document order number: 9397 750 11703