PMN40LN TrenchMOS™ logic level FET M3D302 Rev. 01 — 13 November 2002 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™ technology. Product availability: PMN40LN in SOT457 (TSOP6). 2. Features ■ TrenchMOS™ technology ■ Logic level compatible ■ Surface mount package. 3. Applications ■ Battery management ■ High speed switch ■ Low power DC to DC converter. 4. Pinning information Table 1: Pinning - SOT457 (TSOP6), simplified outline and symbol Pin Description 1,2,5,6 drain (d) 3 gate (g) 4 source (s) Simplified outline 6 5 Symbol d 4 g 1 Top view 2 3 MBK092 SOT457 (TSOP6) MBB076 s PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 30 V ID drain current (DC) Tsp = 25 °C; VGS = 10 V - 5.4 A Ptot total power dissipation Tsp = 25 °C - 1.75 W Tj junction temperature - 150 °C RDSon drain-source on-state resistance VGS = 10 V; ID = 2.5 A; Tj = 25 °C 32 38 mΩ VGS = 4.5 V; ID = 2 A; Tj = 25 °C 40 45 mΩ Min Max Unit 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage (DC) - ±15 V ID drain current (DC) Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 - 5.4 A Tsp = 70 °C; VGS = 10 V; Figure 2 - 4 A IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 21.6 A Ptot total power dissipation Tsp = 25 °C; Figure 1 - 1.75 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp = 25 °C - 1.45 A ISM peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs - 5.8 A © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 2 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 03aa17 120 03aa25 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 0 200 50 100 150 Tsp (°C) P tot P der = ---------------------- × 100% P ° ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. Fig 2. Normalized continuous drain current as a function of solder point temperature. 03aj86 102 ID (A) 200 Tsp (°C) Limit RDSon = VDS / ID tp = 10 µ s 10 100 µ s 1 ms 1 10 ms DC 100 ms 10-1 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 °C; VGS = 10 V; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 3 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit thermal resistance from junction to solder point mounted on a metal clad board; Figure 4 - Rth(j-sp) - 70 K/W 7.1 Transient thermal impedance 03aj85 102 Zth(j-sp) (K/W) δ = 0.5 0.2 10 0.1 0.05 0.02 1 δ= P tp T single pulse t tp T 10-1 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 4 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 30 - - V Tj = −55 °C 27 - - V Tj = 25 °C 1 1.5 2 V Tj = 150 °C 0.6 - - V Tj = −55 °C - - 2.2 V - 0.05 1 µA Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 0.25 mA; VGS = 0 V ID = 1 mA; VDS = VGS; Figure 9 VDS = 24 V; VGS = 0 V Tj = 25 °C Tj = 150 °C - - 500 µA - 10 100 nA Tj = 25 °C - 40 45 mΩ Tj = 150 °C - 64 72 mΩ - 32 38 mΩ IGSS gate-source leakage current VGS = ±15 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 4.5 V; ID = 2 A; Figure 7 and 8 VGS = 10 V; ID = 2.5 A; Figure 7 Tj = 25 °C Dynamic characteristics Qg(tot) total gate charge - 13.8 - nC Qgs gate-source charge ID = 5 A; VDD = 15 V; VGS = 10 V; Figure 13 - 1.8 - nC Qgd gate-drain (Miller) charge - 2.4 - nC Ciss input capacitance - 555 - pF VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 Coss output capacitance - 105 - pF Crss reverse transfer capacitance - 70 - pF td(on) turn-on delay time - 5 - ns tr rise time - 7 - ns td(off) turn-off delay time - 19 - ns tf fall time - 8 - ns - 0.8 1.2 V VDD = 15 V; RL = 12 Ω; VGS = 10 V; RG = 6 Ω Source-drain diode VSD source-drain (diode forward) voltage IS = 1.7 A; VGS = 0 V; Figure 12 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 5 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 03aj87 20 ID (A) 03aj89 20 10 V 5 V 4.5 V 4 V 3.6 V VDS > ID x RDSon ID (A) 15 15 3.2 V 10 10 3V 2.8 V 5 5 2.6 V Tj = 150 °C 25 °C VGS = 2.4 V 0 0 0 0.2 0.4 0.6 0.8 1 VDS (V) Tj = 25 °C 0 2 3 VGS (V) 4 Tj = 25 °C and 150 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03aj88 80 Tj = 25 °C RDSon 1 03af18 2 VGS = 3.2 V a (mΩ) 60 3.6 V 1.5 40 4V 4.5 V 5V 1 10 V 20 0.5 0 0 0 5 10 15 ID (A) 20 Tj = 25 °C -60 60 120 Tj (°C) 180 R DSon a = --------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data 0 Rev. 01 — 13 November 2002 6 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 03aa33 2.5 max ID (A) 10-2 typ 10-3 VGS(th) (V) 2 1.5 03aa36 10-1 min min 1 10-5 0 10-6 0 max 10-4 0.5 -60 typ 60 120 Tj (°C) 180 0 1 2 VGS (V) 3 Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03aj91 103 Ciss C (pF) 102 Coss Crss 10 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 7 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 03aj90 20 VGS VGS = 0 V IS (A) 03aj92 10 ID = 5 A (V) Tj = 25 °C 8 15 VDD = 15 V 6 10 4 150 °C Tj = 25 °C 5 2 0 0 0 0.5 1 VSD (V) 1.5 Tj = 25 °C and 150 °C; VGS = 0 V 0 8 12 QG (nC) 16 ID = 5 A; VDD = 15 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data 4 Rev. 01 — 13 November 2002 8 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 9. Package outline Plastic surface mounted package; 6 leads SOT457 D E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT457 REFERENCES IEC JEDEC EIAJ SC-74 EUROPEAN PROJECTION ISSUE DATE 97-02-28 01-05-04 Fig 14. SOT457 (TSOP6). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 9 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 10. Revision history Table 6: Revision history Rev Date 01 20021113 CPCN - Description Product data. 11. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Product data Rev. 01 — 13 November 2002 10 of 12 PMN40LN Philips Semiconductors TrenchMOS™ logic level FET 12. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13. Definitions 14. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10192 Rev. 01 — 13 November 2002 11 of 12 Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 November 2002 Document order number: 9397 750 10192