INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. Tamb = 25°C. • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C. • Output capability: standard • ICC category: SSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay nA, nB, nC to nY CI Input capacitance CPD CONDITIONS CL = 15 pF; VCC = 3.3 V Power dissipation capacitance per gate See Notes 1 and 2 TYPICAL UNIT 9 ns 3.5 pF 12 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40°C to +125°C 74LV10 N 74LV10 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74LV10 D 74LV10 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV10 DB 74LV10 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV10 PW 74LV10PW DH SOT402-1 PIN DESCRIPTION PIN NUMBER 1, 3, 9 2, 4, 10 7 FUNCTION TABLE SYMBOL 1A – 3A 1B – 3B nA nB nC nY Data inputs L L L H L L L L H H H L H H H H H H H H L L H H L H L H H H H L Ground (0 V) 12, 6, 8 1Y – 3Y Data outputs 13, 5, 11 1C – 3C Data inputs VCC OUTPUTS Data inputs GND 14 INPUTS NAME AND FUNCTION Positive supply voltage NOTES: H = HIGH voltage level L = LOW voltage level 1998 Apr 20 2 853–1919 19256 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 PIN CONFIGURATION LOGIC SYMBOL 14 VCC 1 1A 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y 1 1A 2 1B 13 1C 3 2A 4 2B 5 2C 9 3A 10 3B 11 3C 1Y 12 2Y 6 3Y 8 SV00416 SV00417 LOGIC SYMBOL (IEEE/IEC) LOGIC DIAGRAM (ONE GATE) 1 2 13 & 3 4 5 & 9 10 11 & 12 A 6 B Y C 8 SV00419 SV00418 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. See Note1 1.0 0 0 DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – MAX UNIT 3.3 3.6 V – VCC V – VCC V +85 +125 °C 500 200 100 ns/V – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. 1998 Apr 20 3 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). PARAMETER SYMBOL CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +4.6 V IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 IGND, ICC Tstg PTOT DC VCC or GND current for types with – standard outputs mA mA 50 Storage temperature range °C –65 to +150 Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level l l Input I t voltage l l Input I t LOW level voltage HIGH level output voltage; all outputs VOH HIGH level output voltage; STANDARD outputs -40°C to +125°C MAX MIN VCC = 1.2 V 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 2.0 UNIT MAX V VCC = 1.2 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 VCC = 2.7 to 3.6 V 0.8 0.8 VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA VOH O TYP1 V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 0.25 0.40 0.50 V VOL O LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6mA Input leakage current VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA Quiescent supply current; SSI VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 40 µA II ICC 1998 Apr 20 4 V Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS TYP1 MIN Additional quiescent supply current per input ∆ICC -40°C to +125°C MAX VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V MIN UNIT MAX 500 µA 850 NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER LIMITS CONDITION WAVEFORM –40 to +85 °C VCC(V) Propagation g delay y nA, nB, nC to nY tPHL/PLH / TYP1 MIN –40 to +125 °C MAX MIN 1.2 55 2.0 19 36 44 2.7 14 26 33 3.0 to 3.6 102 21 26 Figure 1, 1 2 UNIT MAX ns NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C. 2. Typical values are measured at VCC = 3.3 V. AC WAVEFORMS TEST CIRCUIT VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. VCC nA, nB, nC INPUT VO VI VI PULSE GENERATOR VM D.U.T. 50pF RT GND t PHL CL RL = 1k t PLH VOH nY OUTPUT Test Circuit for switching times VM DEFINITIONS VOL RL = Load resistor SV00420 CL = Load capacitance includes jig and probe capacitance Figure 1. Input (nA, nB, nC) to output (nY) propagation delays. RT = Termination resistance should be equal to ZOUT of pulse generators. TEST tPLH/tPHL VCC < 2.7V 2.7–3.6V VI VCC 2.7V SV00901 Figure 2. Load circuitry for switching times. 1998 Apr 20 5 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 DIP14: plastic dual in-line package; 14 leads (300 mil) 1998 Apr 20 6 SOT27-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 Apr 20 7 SOT108-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 Apr 20 8 SOT337-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 Apr 20 9 SOT402-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Apr 20 10 Date of release: 05-96 9397-750-04407