Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION BUK127-50GT QUICK REFERENCE DATA Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package. SYMBOL PARAMETER MAX. UNIT VDS Continuous drain source voltage 50 V ID Continuous drain current 2.1 A APPLICATIONS PD Total power dissipation 1.8 W General purpose switch for driving lamps motors solenoids heaters in automotive systems and other applications. Tj Continuous junction temperature 150 ˚C RDS(ON) Drain-source on-state resistance 200 mΩ FEATURES FUNCTIONAL BLOCK DIAGRAM TrenchMOS output stage DRAIN Current trip protection Overload protection Overtemperature protection Protection latched reset by input 5 V logic compatible input level Control of output stage and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads O/V CLAMP POWER INPUT MOSFET RIG LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT223 PIN PIN CONFIGURATION DESCRIPTION 1 input 2 drain 3 source 4 drain (tab) December 2001 SYMBOL 4 D TOPFET I 2 1 1 3 P S Rev 2.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK127-50GT LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS ID ID II IIRM PD Tstg Tj PARAMETER CONDITIONS 1 Continuous drain source voltage Drain current2 Continuous drain current Continuous input current Non-repetitive peak input current Total power dissipation Storage temperature Continuous junction temperature MIN. MAX. UNIT -55 - 50 current trip 2.1 3 10 1.8 150 150 V A A mA mA W ˚C ˚C Ta = 25˚C clamping tp ≤ 1 ms Ta = 25 ˚C normal operation3 ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model; C = 250 pF; R = 1.5 kΩ MIN. MAX. UNIT - 2 kV OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS EDSM Non-repetitive clamping energy EDRM Repetitive clamping energy Ta ≤ 25 ˚C; IDM ≤ ID(TO); inductive load Tsp ≤ 125 ˚C; IDM = 1 A; f = 250 Hz MIN. MAX. UNIT - 100 mJ - 5 mJ OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads. Overload protection operates by means of drain current trip or by activating the overtemperature protection. SYMBOL PARAMETER REQUIRED CONDITION VDDP Protected drain source supply voltage VIS ≥ 4 V MIN. MAX. UNIT - 35 V THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth j-sp Rth j-b Rth j-a Thermal resistance Junction to solder point Junction to board4 Junction to ambient CONDITIONS Mounted on any PCB Mounted on PCB of fig. 4 MIN. TYP. MAX. UNIT - 12 40 - 18 70 K/W K/W K/W 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 Refer to OVERLOAD PROTECTION CHARACTERISTICS. 3 Not in an overload condition with drain current limiting. 4 Temperature measured 1.3 mm from tab. December 2001 2 Rev 2.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK127-50GT OUTPUT CHARACTERISTICS Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified SYMBOL V(CL)DSS IDSS PARAMETER CONDITIONS Off-state VIS = 0 V Drain-source clamping voltage Drain source leakage current MIN. TYP. MAX. UNIT ID = 10 mA 50 - - V ID = 200 mA; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V - 0.1 100 10 µA µA - 150 380 200 mΩ mΩ MIN. TYP. MAX. UNIT Tmb = 25˚C 0.6 1.1 1.6 2.4 2.1 V V VDS = 40 V Tmb = 25 ˚C RDS(ON) On-state VIS ≥ 4 V; tp ≤ 300 µs; δ ≤ 0.01 Drain-source resistance ID = 100 mA Tmb = 25 ˚C INPUT CHARACTERISTICS The supply for the logic and overload protection is taken from the input. Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA IIS Input supply current normal operation; VIS = 5 V VIS = 4 V 100 80 220 195 400 330 µA µA IISL Input supply current protection latched; VIS = 5 V VIS = 3 V 1.4 0.7 2 1.1 2.5 1.5 mA mA VISR Protection reset voltage1 reset time tr ≥ 100 µs 1.5 2 2.5 V tlr Latch reset time VIS1 = 5 V, VIS2 < 1 V 10 40 100 µs V(CL)IS Input clamping voltage II = 1.5 mA 5.5 - 8.5 V RIG Input series resistance2 to gate of power MOSFET - 2.5 - kΩ Tmb = 25˚C OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until reset by the input. SYMBOL ID(TO) PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Overload protection VIS = 4 V to 5.5 V Drain current trip threshold Tj = 25˚C 4 - 8 A -40˚C ≤ Tj ≤ 150˚C 3 - 9 A 150 170 - ˚C Overtemperature protection Tj(TO) Threshold junction temperature VIS = 4 V to 5.5 V 1 The input voltage below which the overload protection circuits will be reset. 2 Not directly measureable from device terminals. December 2001 3 Rev 2.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK127-50GT SWITCHING CHARACTERISTICS Ta = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms SYMBOL PARAMETER CONDITIONS td on Turn-on delay time VIS = 0 V to VIS = 5 V tr Rise time td off Turn-off delay time tf Fall time VIS = 5 V to VIS = 0 V MIN. TYP. MAX. UNIT - 0.5 0.9 µs - 0.7 1.5 µs - 3.2 6.5 µs - 1.6 3.5 µs REVERSE DIODE LIMITING VALUE SYMBOL PARAMETER CONDITIONS IS Continuous forward current Tmb ≤ 25 ˚C; VIS = 0 V MIN. MAX. UNIT - 2 A REVERSE DIODE CHARACTERISTICS Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VSDO Forward voltage IS = 2 A; VIS = 0 V; tp = 300 µs - 0.83 1.1 V trr Reverse recovery time not applicable1 - - - - 1 The reverse diode of this type is not intended for applications requiring fast reverse recovery. December 2001 4 Rev 2.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK127-50GT MECHANICAL DATA Plastic surface mounted package; collector pad for good heat transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 OUTLINE VERSION SOT223 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION SC-73 ISSUE DATE 97-02-28 99-09-13 Fig.2. SOT223 surface mounting package1. 1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8". Net Mass: 0.11 g December 2001 5 Rev 2.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK127-50GT MOUNTING INSTRUCTIONS PRINTED CIRCUIT BOARD Dimensions in mm. Dimensions in mm. 3.8 36 min 1.5 min 18 60 1.5 min 4.5 4.6 9 2.3 6.3 10 (3x) 1.5 min 7 4.6 15 50 Fig.4. PCB for thermal resistance and power rating. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). Fig.3. Soldering pattern for surface mounting. December 2001 6 Rev 2.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK127-50GT DEFINITIONS DATA SHEET STATUS DATA SHEET STATUS1 PRODUCT STATUS2 DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1 Please consult the most recently issued datasheet before initiating or completing a design. 2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. December 2001 7 Rev 2.000