Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in a 3 pin plastic envelope, intended as a general purpose switch for automotive systems and other applications. APPLICATIONS BUK101-50GL QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID PD Tj RDS(ON) Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance VIS = 5 V MAX. UNIT 50 26 75 150 60 V A W ˚C mΩ General controller for driving lamps motors solenoids heaters FEATURES Vertical power DMOS output stage Low on-state resistance Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by input 5 V logic compatible input level Control of power MOSFET and supply of overload protection circuits derived from input Low operating input current ESD protection on input pin Overvoltage clamping for turn off of inductive loads FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP POWER INPUT MOSFET RIG LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - TO220AB PIN DESCRIPTION 1 input 2 drain 3 source tab PIN CONFIGURATION D tab TOPFET I drain 1 23 January 1993 SYMBOL 1 P S Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VIS = 0 V VIS ID ID IDRM PD Tstg Tj Continuous off-state drain source voltage Continuous input voltage Continuous drain current Continuous drain current Repetitive peak on-state drain current Total power dissipation Storage temperature Continuous junction temperature1 Tmb ≤ 25 ˚C; VIS = 5 V Tmb ≤ 100 ˚C; VIS = 5 V Tmb ≤ 25 ˚C; VIS = 5 V Tmb ≤ 25 ˚C normal operation Tsold Lead temperature during soldering MIN. MAX. UNIT - 50 V 0 -55 - 6 26 16 100 75 150 150 V A A A W ˚C ˚C - 250 ˚C OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload. SYMBOL VISP PARAMETER CONDITIONS 2 Protection supply voltage for valid protection MIN. MAX. UNIT 4 - V Over temperature protection VDDP(T) Protected drain source supply voltage VIS = 5 V - 50 V VDDP(P) PDSM Short circuit load protection Protected drain source supply voltage3 VIS = 5 V Instantaneous overload dissipation Tmb = 25 ˚C - 35 1.3 V kW OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS IDROM EDSM Repetitive peak clamping current Non-repetitive clamping energy EDRM Repetitive clamping energy VIS = 0 V Tmb ≤ 25 ˚C; IDM = 26 A; VDD ≤ 20 V; inductive load Tmb ≤ 95 ˚C; IDM = 8 A; VDD ≤ 20 V; f = 250 Hz MIN. MAX. UNIT - 26 625 A mJ - 40 mJ MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model; C = 250 pF; R = 1.5 kΩ 1 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 2 The input voltage for which the overload protection circuits are functional. 3 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum. For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS. January 1993 2 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - 1.3 1.67 K/W - 60 - K/W MIN. TYP. MAX. UNIT 50 - - V - - 70 V - 0.5 1 10 45 10 20 100 60 µA µA µA mΩ Thermal resistance Rth j-mb Junction to mounting base Rth j-a Junction to ambient in free air STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(CL)DSS Drain-source clamping voltage VIS = 0 V; ID = 10 mA V(CL)DSS Drain-source clamping voltage IDSS IDSS IDSS RDS(ON) VIS = 0 V; IDM = 2 A; tp ≤ 300 µs; δ ≤ 0.01 Zero input voltage drain current VDS = 12 V; VIS = 0 V Zero input voltage drain current VDS = 50 V; VIS = 0 V Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C Drain-source on-state VIS = 5 V; IDM = 13 A; tp ≤ 300 µs; resistance δ ≤ 0.01 OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input. SYMBOL PARAMETER CONDITIONS 1 Tmb = 25 ˚C; L ≤ 10 µH VDD = 13 V; VIS = 5 V VDD = 13 V; VIS = 5 V EDS(TO) td sc Short circuit load protection Overload threshold energy Response time Tj(TO) Over temperature protection Threshold junction temperature VIS = 5 V; from ID ≥ 1 A2 MIN. TYP. MAX. UNIT - 0.4 0.8 - J ms 150 - - ˚C INPUT CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VIS(TO) IIS VISR Input threshold voltage Input supply current Protection reset voltage3 VDS = 5 V; ID = 1 mA VIS = 5 V; normal operation 1.0 2.0 1.5 0.2 2.6 2.0 0.35 3.5 V mA V VISR Protection reset voltage Tj = 150 ˚C 1.0 - - IISL V(BR)IS RIG Input supply current Input clamp voltage Input series resistance VIS = 5 V; protection latched II = 10 mA to gate of power MOSFET 0.5 6 - 1.2 7 4 2.0 - mA V kΩ 1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES. 2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition. 3 The input voltage below which the overload protection circuits will be reset. January 1993 3 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL TRANSFER CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 10 V; IDM = 13 A tp ≤ 300 µs; δ ≤ 0.01 ID(SC) Drain current1 VDS = 13 V; VIS = 5 V MIN. TYP. MAX. UNIT 10 16 - S - 40 - A MIN. TYP. MAX. UNIT SWITCHING CHARACTERISTICS Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits. SYMBOL PARAMETER CONDITIONS td on Turn-on delay time VDD = 13 V; VIS = 5 V - 2.5 - µs tr Rise time resistive load RL = 2.1 Ω - 15 - µs td off Turn-off delay time VDD = 13 V; VIS = 0 V - 10 - µs tf Fall time resistive load RL = 2.1 Ω - 7 - µs td on Turn-on delay time VDD = 10 V; VIS = 5 V - 2 - µs tr Rise time inductive load IDM = 6 A - 4 - µs td off Turn-off delay time VDD = 10 V; VIS = 0 V - 15 - µs tf Fall time inductive load IDM = 6 A - 1 - µs REVERSE DIODE LIMITING VALUE SYMBOL PARAMETER CONDITIONS IS Continuous forward current Tmb ≤ 25 ˚C MIN. MAX. UNIT - 26 A REVERSE DIODE CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VSDS Forward voltage IS = 26 A; VIS = 0 V; tp = 300 µs - 1.0 1.5 V trr Reverse recovery time not applicable2 - - - - MIN. TYP. MAX. UNIT - 3.5 - nH - 4.5 - nH - 7.5 - nH ENVELOPE CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Ld Internal drain inductance Ld Internal drain inductance Ls Internal source inductance Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad 1 During overload before short circuit load protection operates. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery. January 1993 4 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 120 BUK101-50GL Normalised Power Derating PD% BUK101-50GL Zth / (K/W) 10 110 100 90 D= 80 1 0.5 70 0.2 60 50 0.1 40 0.1 0.05 30 20 10 0 0 20 40 60 80 100 Tmb / C 120 0.01 1E-07 140 Fig.2. Normalised power dissipation. PD% = 100⋅PD/PD(25 ˚C) = f(Tmb) 120 80 110 tp T t T 0 1E-05 1E-03 t/s 1E-01 1E+01 BUK101-50GL ID / A 70 100 90 VIS / V = 6 60 80 50 70 5 60 50 40 30 40 30 20 20 10 10 0 0 4 3 2 0 20 40 60 80 Tmb / C 100 120 140 0 Fig.3. Normalised continuous drain current. ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V 1000 D= Fig.5. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% tp PD 0.02 8 12 16 VDS / V 20 24 28 Fig.6. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc BUK101-50GL ID & IDM / A 4 50 ID / A BUK101-50GL Overload protection characteristics not shown 40 D /I DS 100 ) ON 30 10 us S( RD VIS = 5 V VIS = 6 V tp = =V 100 us VIS = 4 V 20 10 1 ms DC 10 10 ms 100 ms 0 1 1 100 10 0 VDS / V 2 3 4 5 VDS / V Fig.4. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp January 1993 1 Fig.7. Typical on-state characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 250 µs 5 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL BUK101-50GL RDS(ON) / ohm 0.20 a (3V) Normalised RDS(ON) = f(Tj) 1.5 0.15 VIS = 4 V 5V 6V 1.0 0.10 0.5 0.05 0 0 0 20 40 ID / A 60 80 ID / A 0 20 40 60 Tj / C 80 100 120 140 Fig.11. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 13 A; VIS = 5 V Fig.8. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VIS; tp = 250 µs 50 -60 -40 -20 BUK101-50GL 100 BUK101-50GL td sc / ms 40 NORMAL 10 30 PDSM 20 1 OVERLOAD 10 RESET PROTECTION LATCHED 0.1 0 1 0 3 2 5 4 0.1 1 PDS / kW VIS / V Fig.9. Typical transfer characteristics, Tj = 25 ˚C. ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Fig.12. Typical overload protection characteristics. td sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C. BUK101-50GL gfs / S 10 PDSM% 120 100 80 60 40 20 0 0 10 20 30 ID / A 40 50 -60 60 Fig.10. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs January 1993 -40 -20 0 20 40 60 Tmb / C 80 100 120 140 Fig.13. Normalised limiting overload dissipation. PDSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb) 6 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 1 BUK101-50GL Energy & Time BUK101-50GL 500 II / uA BUK101-50GL 400 Tj = 25 C Time / ms 300 0.5 200 150 C Energy / J 100 Tj(TO) 0 0 -60 -20 20 60 100 Tmb / C 140 180 220 0 4 6 8 10 VIS / V Fig.17. Typical DC input characteristics. II = f(VIS); normal operation; parameter: Tj Fig.14. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ 30 2 ID / A BUK101-50GL 3 IISL / mA BUK101-50GL PROTECTION LATCHED 20 2 typ. RESET 1 10 NORMAL 0 0 50 60 VIS / V 0 70 Fig.15. Typical clamping characteristics, 25 ˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs 2 4 VIS / V 6 8 Fig.18. Typical DC input characteristics, Tj = 25 ˚C. IISL = f(VIS); overload protection operated ⇒ ID = 0 A VIS(TO) / V 100 IS / A BUK101-50GL max. 2 typ. 50 min. 1 0 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 0 120 140 Fig.16. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V January 1993 1 VSD / V 2 Fig.19. Typical reverse diode current, Tj = 25 ˚C. IS = f(VSDS); conditions: VIS = 0 V 7 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL VDD VDD = VCL RL LD t p : adjust for correct ID TOPFET D I TOPFET I D.U.T. P D D.U.T. P RI RI VIS VIS S ID measure S ID measure 0V 0V 0R1 0R1 Fig.23. Test circuit for inductive load switching times. Fig.20. Test circuit for resistive load switching times. 15 BUK101-50GL RESISTIVE TURN-ON 15 BUK101-50GL INDUCTIVE TURN-ON VDS / V 10 10 td on tr tr td on ID / A ID / A 90% 5 90% 5 VIS / V VIS / V VDS / V 10% 10% 0 0 0 10 20 30 40 50 0 10 Fig.24. Typical switching waveforms, inductive load. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C. BUK101-50GL RESISTIVE TURN-OFF 15 BUK101-50GL INDUCTIVE TURN-OFF VDS / V VDS / V 10 10 td off 5 td off tf ID / A 90% 90% 5 10% ID / A 5 10 time / us 15 10% 0 20 0 Fig.22. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. January 1993 90% VIS / V 0 tf 90% VIS / V 0 50 40 time / us Fig.21. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. 15 30 20 time / us 5 10 time / us 15 20 Fig.25. Typical switching waveforms, inductive load. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C. 8 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL Iiso normalised to 25 C EDSM% 120 110 100 1.5 90 80 70 60 50 1 40 30 20 10 0 0.5 0 20 40 60 80 Tmb / C 100 120 140 -60 Fig.26. Normalised clamping energy rating. EDSM% = f(Tmb); conditions: ID = 26 A; VIS = 5 V -20 20 60 Tj / C 100 140 180 Fig.29. Normalised input current (normal operation). IIS/IIS25 ˚C = f(Tj); VIS = 5 V V(CL)DSS Iisl normalised to 25 C VDS VDD + 0 VDD 1.5 L ID VDS 0 - D VIS TOPFET 0 I -ID/100 1 D.U.T. P Schottky RIS S R 01 shunt 0.5 -60 Fig.27. Clamping energy test circuit, RIS = 50 Ω. EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSS /(V(CL)DSS − VDD ) 1 mA -20 20 60 Tj / C 100 140 180 Fig.30. Normalised input current (protection latched). IISL/IISL25 ˚C = f(Tj); VIS = 5 V Idss 100 uA 10 uA typ. 1 uA 100 nA 0 20 40 60 80 Tj / C 100 120 140 Fig.28. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V. January 1993 9 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.31. TO220AB; pin 2 connected to mounting base. Notes 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8". January 1993 10 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1993 11 Rev 2.600