PHD20N06T N-channel TrenchMOS standard level FET Rev. 02 — 1 December 2009 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics 1.3 Applications DC-to-DC convertors Switched-mode power supplies General purpose switching 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 55 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 and 3 - - 18 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 51 W VGS = 10 V; ID = 25 A; VDS = 44 V; Tj = 25 °C; see Figure 13 - 6 - nC VGS = 10 V; ID = 10 A; Tj = 175 °C; see Figure 11 and 12 - - 154 mΩ VGS = 10 V; ID = 10 A; Tj = 25 °C; see Figure 11 and 12 - 65 77 mΩ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 2 1 3 SOT428 (DPAK) 3. Ordering information Table 3. Ordering information Type number PHD20N06T Package Name Description Version DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 55 V VDGR drain-gate voltage RGS = 20 kΩ - 55 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 100 °C; see Figure 1 - 13 A VGS = 10 V; Tmb = 25 °C; see Figure 1 and 3 - 18 A - 73 A - 51 W IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C [1] Source-drain diode IS source current Tmb = 25 °C - 18 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 73 A - 36 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive VGS = 10 V; Tj = 25 °C; ID = 6 A; RGS = 50 Ω; drain-source avalanche Vsup ≤ 55 V; unclamped inductive load energy Peak drain current is limited by chip, not package. PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 2 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 03aa24 120 03aa16 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 200 0 50 100 150 Tmb (°C) Fig 1. 200 Tmb (°C) Fig 2. Normalized continuous drain current as a function of mounting base temperature Normalized total power dissipation as a function of mounting base temperature 003aaa043 103 ID (A) 102 RDSon = VDS/ ID tp = 10 μs 10 100 μs P δ= tp D.C. T 1 ms 10 ms 1 t tp T 10−1 1 Fig 3. 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 3 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-mb) Rth(j-a) Conditions Min Typ Max Unit thermal resistance from see Figure 4 junction to mounting base - - 2.9 K/W thermal resistance from minimum footprint; FR4 board junction to ambient - 71.4 - K/W 003aaa053 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 10−1 P 0.02 δ= tp T Single pulse t tp 10−2 10−6 T 10−5 10−4 10−3 10−2 10−1 1 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 4 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 50 - - V ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 55 - - V gate-source threshold voltage ID = 1 mA; VDS= VGS; Tj = -55 °C; see Figure 10 - - 4.4 V ID = 1 mA; VDS= VGS; Tj = 175 °C; see Figure 10 1 - - V ID = 1 mA; VDS= VGS; Tj = 25 °C; see Figure 10 2 3 4 V VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VDS = 55 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 10 A; Tj = 175 °C; see Figure 11 and 12 - - 154 mΩ VGS = 10 V; ID = 10 A; Tj = 25 °C; see Figure 11 and 12 - 65 77 mΩ ID = 25 A; VDS = 44 V; VGS = 10 V; Tj = 25 °C; see Figure 13 - 11 - nC - 3 - nC - 6 - nC Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 VDS = 30 V; RL = 1.2 Ω; VGS = 10 V; RG(ext) = 10 Ω; Tj = 25 °C - 316 422 pF - 92 110 pF - 64 87 pF - 10 - ns - 50 - ns td(on) turn-on delay time tr rise time td(off) turn-off delay time - 70 - ns tf fall time - 40 - ns LD internal drain inductance measured from drain lead from package to centre of die; Tj = 25 °C - 2.5 - nH LS internal source inductance measured from source lead from package to source bond pad; Tj = 25 °C - 7.5 - nH Source-drain diode VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; see Figure 15 - 0.85 1.2 V trr reverse recovery time - 32 - ns Qr recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = -10 V; VDS = 30 V; Tj = 25 °C - 120 - nC PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 5 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 003aaa045 60 ID (A) VGS (V) = 50 16 12 40 10 003aaa051 160 RDSon (mΩ) 140 120 9.0 100 30 8.0 7.5 7.0 6.5 6.0 20 10 80 60 5.0 0 Fig 5. 0 2 4 6 40 8 10 VDS (V) Output characteristics: drain current as a function of drain-source voltage; typical values 5 Fig 6. 03aa35 10−1 ID (A) 10 15 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values 003aaa047 8 gfs min 10−2 typ max (S) 6 10−3 4 10−4 2 10−5 10−6 0 0 2 4 6 0 VGS (V) Fig 7. 10 15 20 25 ID (A) Sub-threshold drain current as a function of gate-source voltage Fig 8. Forward transconductance as a function of drain current; typical values PHD20N06T_2 Product data sheet 5 © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 6 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 003aaa049 25 03aa32 5 VGS(th) (V) ID (A) 20 4 15 3 10 2 5 max typ min 1 Tj = 175 °C Tj = 25 °C 0 −60 0 0 Fig 9. 2 4 6 8 VGS (V) 10 Transfer characteristics: drain current as a function of gate-source voltage; typical values 5.5 6 6.5 7 8 120 180 Tj (°C) 03aa28 2.4 VGS (V) = (mΩ) 60 Fig 10. Gate-source threshold voltage as a function of junction temperature 003aaa046 180 RDSon 0 a 10 160 1.8 140 120 1.2 100 80 0.6 60 40 0 10 20 30 40 ID (A) 50 Fig 11. Drain-source on-state resistance as a function of drain current; typical values 0 −60 60 120 180 Tj (°C) Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature PHD20N06T_2 Product data sheet 0 © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 7 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 003aaa050 10 VGS (V) 003aaa048 600 Ciss, Coss, Crss 500 VDD = 44 V 8 (pF) VDD = 14 V 400 6 Ciss 300 4 200 Coss 2 100 Crss 0 0 0 5 10 QG (nC) 15 10−3 10−2 1 102 10 VDS (V) Fig 13. Gate-source voltage as a function of gate charge; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aaa052 120 IS (A) 100 80 60 Tj = 175 °C 40 Tj = 25 °C 20 0 0 0.5 1.0 1.5 VSD (V) 2.0 Fig 15. Source current as a function of source-drain voltage; typical values PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 8 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 7. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E A A A1 b2 E1 mounting base D2 D1 HD 2 L L2 1 L1 3 b1 b w M c A e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D1 D2 min E E1 min e e1 HD L L1 min L2 w y max mm 2.38 2.22 0.93 0.46 0.89 0.71 1.1 0.9 5.46 5.00 0.56 0.20 6.22 5.98 4.0 6.73 6.47 4.45 2.285 4.57 10.4 9.6 2.95 2.55 0.5 0.9 0.5 0.2 0.2 OUTLINE VERSION SOT428 REFERENCES IEC JEDEC JEITA TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 06-02-14 06-03-16 Fig 16. Package outline SOT428 (DPAK) PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 9 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHD20N06T_2 20091201 Product data sheet - PHD20N06T-01 Modifications: PHD20N06T-01 (9397 750 07895) • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 20010222 Product specification - PHD20N06T_2 Product data sheet - © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 10 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 9.2 Definitions Draft— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data— The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license— Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS— is a trademark of NXP B.V. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] PHD20N06T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 1 December 2009 11 of 12 PHD20N06T NXP Semiconductors N-channel TrenchMOS standard level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 1 December 2009 Document identifier: PHD20N06T_2