PCA9554; PCA9554A 8-bit I2C-bus and SMBus I/O port with interrupt Rev. 9 — 19 March 2013 Product data sheet 1. General description The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, and so on. The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I2C-bus address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9554/PCA9554A open-drain interrupt output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight devices to share the same I2C-bus/SMBus. The PCA9554A is identical to the PCA9554 except that the fixed I2C-bus address is different allowing up to sixteen of these devices (eight of each) on the same I2C-bus/SMBus. 2. Features and benefits Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 8 I/O pins which default to 8 inputs 0 Hz to 400 kHz clock frequency PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA AEC-Q100 compliance available Packages offered: SO16, SSOP16, SSOP20, TSSOP16, HVQFN16 (2 versions: 4 4 0.85 mm and 3 3 0.85 mm), and bare die 3. Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9554D PCA9554D SO16 SOT162-1 PCA9554AD PCA9554AD plastic small outline package; 16 leads; body width 7.5 mm PCA9554DB 9554DB SSOP16 SOT338-1 PCA9554ADB 9554A plastic shrink small outline package; 16 leads; body width 5.3 mm PCA9554TS PCA9554 SSOP20 SOT266-1 PCA9554ATS PA9554A plastic shrink small outline package; 20 leads; body width 4.4 mm PCA9554PW 9554DH TSSOP16 9554DH plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PCA9554PW/Q900[1] PCA9554APW 9554ADH HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 4 0.85 mm SOT629-1 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 3 0.85 mm SOT758-1 bare die - - PCA9554BS 9554 PCA9554ABS 554A PCA9554BS3 P54 PCA9554ABS3 54A PCA9554U - [1] PCA9554PW/Q900 is AEC-Q100 compliant. Contact [email protected] for PPAP. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method PCA9554D PCA9554D,112 SO16 Standard marking * 1920 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554D,118 SO16 Reel 13” Q1/T1 *standard mark SMD 1000 Tamb = 40 C to +85 C PCA9554AD,112 SO16 Standard marking * 1920 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554AD,118 SO16 Reel 13” Q1/T1 *standard mark SMD 1000 Tamb = 40 C to +85 C PCA9554DB,112 SSOP16 Standard marking * 1092 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554DB,118 SSOP16 Reel 13” Q1/T1 *standard mark SMD Tamb = 40 C to +85 C PCA9554AD PCA9554DB PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 Minimum Temperature order quantity 2000 © NXP B.V. 2013. All rights reserved. 2 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Table 2. Ordering options …continued Type number Orderable part number Package Packing method PCA9554ADB PCA9554ADB,112 SSOP16 Standard marking * 1092 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554ADB,118 SSOP16 Reel 13” Q1/T1 *standard mark SMD 2000 Tamb = 40 C to +85 C PCA9554TS,112 SSOP20 Standard marking * 1350 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554TS,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9554ATS,112 SSOP20 Standard marking * 1350 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554ATS,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9554PW,112 TSSOP16 Standard marking * 2400 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554PW,118 TSSOP16 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9554PW/Q900 PCA9554PW/Q900,118 TSSOP16 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9554APW,112 TSSOP16 Standard marking * 2400 IC’s tube - DSC bulk pack Tamb = 40 C to +85 C PCA9554APW,118 TSSOP16 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9554BS PCA9554BS,118 HVQFN16 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 40 C to +85 C PCA9554ABS PCA9554ABS,118 HVQFN16 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 40 C to +85 C PCA9554BS3 PCA9554BS3,118 HVQFN16 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 40 C to +85 C PCA9554ABS3 PCA9554ABS3,118 HVQFN16 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 40 C to +85 C PCA9554U PCA9554U,029 bare die 7000 Tamb = 40 C to +85 C PCA9554TS PCA9554ATS PCA9554PW PCA9554APW PCA9554_9554A Product data sheet Reel 7” Q1/T1 *no mark die mounted on punched tape All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 Minimum Temperature order quantity © NXP B.V. 2013. All rights reserved. 3 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 4. Block diagram PCA9554/PCA9554A A0 A1 A2 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 8-bit SCL SDA INPUT FILTER I2C-BUS/SMBus CONTROL write pulse VDD POWER-ON RESET INPUT/ OUTPUT PORTS read pulse VDD VSS LP FILTER INT 002aac492 All I/Os are set to inputs at reset. Fig 1. PCA9554_9554A Product data sheet Block diagram of PCA9554/PCA9554A All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 4 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 5. Pinning information 5.1 Pinning A0 A1 A2 IO0 IO1 IO2 IO3 VSS 1 16 VDD 2 15 SDA 14 SCL 3 4 13 INT PCA9554D PCA9554AD 5 12 IO7 6 11 IO6 7 10 IO5 9 8 IO4 A0 1 16 VDD A1 2 15 SDA A2 3 14 SCL IO0 4 IO1 5 IO2 6 11 IO6 IO3 7 10 IO5 VSS 8 Pin configuration for SO16 Fig 3. Pin configuration for SSOP16 INT 1 20 IO7 SCL 2 19 IO6 A0 1 16 VDD n.c. 3 18 n.c. A1 2 15 SDA SDA 4 17 IO5 A2 3 14 SCL VDD 5 IO0 4 13 INT A0 6 IO1 5 12 IO7 A1 7 14 IO3 IO2 6 11 IO6 n.c. 8 13 n.c. IO3 7 10 IO5 A2 9 12 IO2 VSS 8 IO0 10 11 IO1 9 IO4 Fig 5. Pin configuration for SSOP20 13 SDA 16 A1 terminal 1 index area 15 A0 PCA9554BS3 PCA9554ABS3 13 SDA 14 VDD 16 A1 15 A0 PCA9554BS PCA9554ABS IO1 3 10 IO7 IO2 4 9 IO2 4 9 IO6 002aac490 Pin configuration for HVQFN16 (SOT629-1) IO6 002aac491 Transparent top view Fig 7. All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 8 10 IO7 IO5 3 7 IO1 IO4 11 INT 6 2 VSS IO0 5 11 INT 8 2 IO5 IO0 7 12 SCL 6 1 IO4 A2 VSS 12 SCL 5 1 IO3 A2 Transparent top view Fig 6. 15 VSS 002aac489 Pin configuration for TSSOP16 terminal 1 index area 16 IO4 PCA9554TS PCA9554ATS 14 VDD PCA9554PW PCA9554PW/Q900 PCA9554APW IO3 Fig 4. Product data sheet IO4 002aac487 002aac488 PCA9554_9554A 12 IO7 9 002aac486 Fig 2. 13 INT PCA9554DB PCA9554ADB Pin configuration for HVQFN16 (SOT758-1) © NXP B.V. 2013. All rights reserved. 5 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 5.2 Pin description Table 3. Pin description Symbol Pin Description SO16, SSOP16, TSSOP16 HVQFN16 SSOP20 A0 1 15 6 address input 0 A1 2 16 7 address input 1 A2 3 1 9 address input 2 IO0 4 2 10 input/output 0 IO1 5 3 11 input/output 1 IO2 6 4 12 input/output 2 IO3 7 5 14 input/output 3 8 6[1] 15 supply ground VSS IO4 9 7 16 input/output 4 IO5 10 8 17 input/output 5 IO6 11 9 19 input/output 6 IO7 12 10 20 input/output 7 INT 13 11 1 interrupt output (open-drain) SCL 14 12 2 serial clock line SDA 15 13 4 serial data line VDD 16 14 5 supply voltage n.c. - - 3, 8, 13, 18 not connected [1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. 6. Functional description Refer to Figure 1 “Block diagram of PCA9554/PCA9554A”. 6.1 Registers 6.1.1 Command byte Table 4. Command byte Command Protocol Function 0 read byte Input Port register 1 read/write byte Output Port register 2 read/write byte Polarity Inversion register 3 read/write byte Configuration register The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 6 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 6.1.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no external signal externally applied because of the internal pull-up resistors. Table 5. Register 0 - Input Port register bit description Bit Symbol Access Value Description 7 I7 read only X determined by externally applied logic level 6 I6 read only X 5 I5 read only X 4 I4 read only X 3 I3 read only X 2 I2 read only X 1 I1 read only X 0 I0 read only X 6.1.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 6. Register 1 - Output Port register bit description Legend: * default value. PCA9554_9554A Product data sheet Bit Symbol Access Value Description 7 O7 R 1* 6 O6 R 1* reflects outgoing logic levels of pins defined as outputs by Register 3 5 O5 R 1* 4 O4 R 1* 3 O3 R 1* 2 O2 R 1* 1 O1 R 1* 0 O0 R 1* All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 7 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 6.1.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. Table 7. Register 2 - Polarity Inversion register bit description Legend: * default value. Bit Symbol Access Value Description 7 N7 R/W 0* inverts polarity of Input Port register data 6 N6 R/W 0* 0 = Input Port register data retained (default value) 5 N5 R/W 0* 1 = Input Port register data inverted 4 N4 R/W 0* 3 N3 R/W 0* 2 N2 R/W 0* 1 N1 R/W 0* 0 N0 R/W 0* 6.1.5 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD. Table 8. Register 3 - Configuration register bit description Legend: * default value. Bit Symbol Access Value Description 7 C7 R/W 1* configures the directions of the I/O pins 6 C6 R/W 1* 0 = corresponding port pin enabled as an output 5 C5 R/W 1* 4 C4 R/W 1* 1 = corresponding port pin configured as input (default value) 3 C3 R/W 1* 2 C2 R/W 1* 1 C1 R/W 1* 0 C0 R/W 1* 6.2 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9554/PCA9554A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9554/PCA9554A registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 8 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 6.3 Interrupt output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from and output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. 6.4 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. data from shift register output port register data configuration register data from shift register D VDD Q1 Q FF write configuration pulse CK 100 kΩ Q D Q FF IO0 to IO7 write pulse CK Q2 output port register input port register D Q FF read pulse CK VSS input port register data to INT polarity inversion register data from shift register D Q polarity inversion register data FF write polarity pulse CK 002aac493 Remark: At power-on reset, all registers return to default values. Fig 8. Simplified schematic of IO0 to IO7 PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 9 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 6.5 Device address slave address slave address 0 1 0 0 A2 fixed A1 0 A0 R/W 1 1 1 fixed hardware selectable A2 A1 A0 R/W hardware selectable 002aac495 002aac494 Fig 9. PCA9554 device address Fig 10. PCA9554A device address 6.6 Bus transactions Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown in Figure 11 and Figure 12. Data is read from the PCA9554/PCA9554A registers using the Read mode as shown in Figure 13 and Figure 14. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 data to port command byte 0 A2 A1 A0 0 START condition A 0 0 0 0 0 R/W 0 0 1 A acknowledge from slave acknowledge from slave acknowledge from slave A DATA 1 P STOP condition write to port tv(Q) data out from port data 1 valid 002aac472 Fig 11. Write to Output Port register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 0 A2 A1 A0 0 START condition data to register data to register command byte A R/W acknowledge from slave 0 0 0 0 0 0 1 1/0 A acknowledge from slave DATA A acknowledge from slave P STOP condition 002aac473 Fig 12. Write to Configuration register or Polarity Inversion register PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 10 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt slave address SDA S 0 1 0 0 A2 A1 A0 0 START condition A R/W acknowledge from slave acknowledge from slave data from register slave address (cont.) S 0 1 0 0 A2 A1 A0 1 (repeated) START condition (cont.) A command byte A data from register R/W DATA (last byte) A DATA (first byte) acknowledge from master acknowledge from slave NA no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter P STOP condition 002aac474 Fig 13. Read from register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 0 A2 A1 A0 1 START condition DATA 1 A R/W A DATA 2 tv(INT_N) NA P no acknowledge from master STOP condition tsu(D) th(D) data into port DATA 4 acknowledge from master acknowledge from slave read from port data from port data from port DATA 3 DATA 4 trst(INT_N) INT 002aac475 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Fig 14. Read Input Port register PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 11 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 7. Application design-in information VDD (5 V) 10 kΩ 10 kΩ 10 kΩ 2 kΩ 10 kΩ VDD VDD MASTER CONTROLLER SCL SCL IO0 SUBSYSTEM 1 (e.g., temp. sensor) SDA SDA IO1 INT PCA9554 IO2 INT RESET IO3 INT SUBSYSTEM 2 (e.g., counter) IO4 VSS IO5 A IO6 IO7 A2 controlled switch (e.g., CBT device) enable A1 B A0 VSS ALARM SUBSYSTEM 3 (e.g., alarm system) VDD 002aac496 Device address configured as 0100 100X for this example. IO0, IO1, IO2 configured as outputs. IO3, IO4, IO5 configured as inputs. IO6 and IO7 are not used and must be configured as outputs. Fig 15. Typical application 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). PCA9554_9554A Product data sheet Symbol Parameter VDD Conditions Min Max Unit supply voltage 0.5 +6.0 V II input current - 20 mA VI/O voltage on an input/output pin VSS 0.5 5.5 V IO(IOn) output current on pin IOn - 50 mA IDD supply current - 85 mA ISS ground supply current - 100 mA Ptot total power dissipation - 200 mW Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C operating All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 12 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 9. Static characteristics Table 10. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 2.3 - 5.5 V IDD supply current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz - 104 175 A Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs - 550 700 A Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs - 0.25 1 A - 1.5 1.65 V VPOR power-on reset voltage no load; VI = VDD or VSS [1] Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V 3 6 - mA IL leakage current VI = VDD = VSS 1 - +1 A Ci input capacitance VI = VSS - 6 10 pF 0.5 - +0.8 V I/Os VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current VOH HIGH-level output voltage 2.0 - 5.5 V VOL = 0.5 V; VDD = 2.3 V [2] 8 10 - mA VOL = 0.7 V; VDD = 2.3 V [2] 10 13 - mA VOL = 0.5 V; VDD = 3.0 V [2] 8 14 - mA VOL = 0.7 V; VDD = 3.0 V [2] 10 19 - mA VOL = 0.5 V; VDD = 4.5 V [2] 8 17 - mA VOL = 0.7 V; VDD = 4.5 V [2] 10 24 - mA IOH = 8 mA; VDD = 2.3 V [3] 1.8 - - V IOH = 10 mA; VDD = 2.3 V [3] 1.7 - - V IOH = 8 mA; VDD = 3.0 V [3] 2.6 - - V IOH = 10 mA; VDD = 3.0 V [3] 2.5 - - V IOH = 8 mA; VDD = 4.75 V [3] 4.1 - - V IOH = 10 mA; VDD = 4.75 V [3] 4.0 - - V ILI input leakage current VDD = 3.6 V; VI = VDD 1 - +1 A IL leakage current VDD = 5.5 V; VI = VSS - - 100 A Ci input capacitance - 3.7 5 pF Co output capacitance - 3.7 5 pF 3 - - mA Interrupt INT IOL LOW-level output current PCA9554_9554A Product data sheet VOL = 0.4 V All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 13 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Table 10. Static characteristics …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Select inputs A0, A1, A2 VIL LOW-level input voltage 0.5 - 0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V ILI input leakage current 1 - 1 A [1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA. 10. Dynamic characteristics Table 11. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Min Max Fast-mode I2C-bus Min Max Unit fSCL SCL clock frequency 0 100 0 400 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - kHz s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time s 0 - 0 - 0.3 3.45 0.1 0.9 s 300 - 50 - ns tVD;ACK data valid acknowledge time [1] tVD;DAT data valid time [2] tSU;DAT data set-up time 250 - 100 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tv(Q) data output valid time - 200 - 200 ns tsu(D) data input set-up time 100 - 100 - ns th(D) data input hold time 1 - 1 - s Port timing Interrupt timing tv(INT_N) valid time on pin INT - 4 - 4 s trst(INT_N) reset time on pin INT - 4 - 4 s [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 14 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P 002aaa986 Fig 16. Definition of timing PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 15 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 11. Package outline SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT162-1 (SO16) PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 16 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 18. Package outline SOT338-1 (SSOP16) PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 17 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 o o 0 Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-152 Fig 19. Package outline SOT266-1 (SSOP20) PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 18 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 20. Package outline SOT403-1 (TSSOP16) PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 19 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm A B D SOT629-1 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 8 y y1 C v M C A B w M C b 5 L 9 4 e e2 Eh 1/2 e 1 12 terminal 1 index area 16 13 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.38 0.23 0.2 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 0.65 1.95 1.95 0.75 0.50 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT629-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 21. Package outline SOT629-1 (HVQFN16) PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 20 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm A B D SOT758-1 terminal 1 index area A E A1 c detail X e1 C 1/2 e e 5 y y1 C v M C A B w M C b 8 L 4 9 e e2 Eh 1/2 e 12 1 16 terminal 1 index area 13 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.75 1.45 3.1 2.9 1.75 1.45 0.5 1.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT758-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21 Fig 22. Package outline SOT758-1 (HVQFN16) PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 21 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 12. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 22 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 13. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 23 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 24 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 14. Soldering: PCB footprints Footprint information for reflow soldering of SO16 package SOT162-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 1.270 P2 Ay 1.320 11.200 By C D1 D2 6.400 2.400 0.700 Gx 0.800 10.040 Gy Hx Hy 8.600 11.900 11.450 sot162-1_fr Fig 24. PCB footprint for SOT162-1 (SO16); reflow soldering PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 25 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Footprint information for reflow soldering of TSSOP16 package SOT338-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 8.600 5.400 1.600 0.400 0.600 5.600 6.100 7.000 8.850 sot338-1_fr Fig 25. PCB footprint for SOT338-1 (HVQFN16); reflow soldering PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 26 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Footprint information for reflow soldering of SSOP20 package SOT266-1 Hx Gx (0.125) P2 Hy (0.125) By Gy Ay C D2 (4x) D1 P1 solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 sot266-1_fr Fig 26. PCB footprint for SOT266-1 (SSOP20); reflow soldering PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 27 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Footprint information for reflow soldering of TSSOP16 package SOT403-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 sot403-1_fr Fig 27. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 28 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Footprint information for reflow soldering of HVQFN16 package SOT629-1 Hx Gx D P 0.025 0.025 C (0.105) SPx nSPx Hy SPy tot SPy Gy SLy nSPy By Ay SPx tot SLx Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy 2 2 Dimensions in mm P Ax Ay Bx By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy 0.650 5.000 5.000 2.800 2.800 1.100 0.300 2.000 2.000 1.200 1.200 0.450 0.450 4.300 4.300 5.250 5.250 Issue date 07-05-07 09-06-15 sot629-1_fr Fig 28. PCB footprint for SOT629-1 (HVQFN16); reflow soldering PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 29 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Footprint information for reflow soldering of HVQFN16 package SOT758-1 Hx Gx D P 0.025 0.025 C (0.105) SPx Hy SPy tot nSPx Gy SPy nSPy SLy By Ay SPx tot SLx Bx Ax solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy 2 2 Dimensions in mm P Ax Ay Bx By C D SLx SLy 0.50 4.00 4.00 2.20 2.20 0.90 0.24 1.50 1.50 Issue date SPx tot SPy tot 0.90 0.90 SPx SPy Gx Gy Hx Hy 0.30 0.30 3.30 3.30 4.25 4.25 12-03-07 12-03-08 sot758-1_fr Fig 29. PCB footprint for SOT758-1 (HVQFN16); reflow soldering PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 30 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 15. Abbreviations Table 14. PCA9554_9554A Product data sheet Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General Purpose Input/Output HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light-Emitting Diode MM Machine Model PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 31 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 16. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9554_9554A v.9 20130319 Product data sheet - PCA9554_9554A v.8 Modifications: PCA9554_9554A v.8 • • • • Removed DIP16 package option (type numbers PCA9554N and PCA9554AN) • • • • Figure 16 “Definition of timing” modified: added 0.7 VDD and 0.3 VDD reference lines Added Section 3.1 “Ordering options” Deleted (old) Figure 2, “Pin configuration for DIP16” Figure 10 “PCA9554A device address” modified: label corrected from “programmable” to “hardware selectable” Deleted (old) Figure 18, “Package outline SOT38-4 (DIP16)” Deleted (old) Section 14, “Soldering of through-hole mount packages” Added Section 14 “Soldering: PCB footprints” 20110726 Product data sheet - PCA9554_9554A v.7 PCA9554_9554A v.7 20061113 Product data sheet - PCA9554_9554A v.6 PCA9554_9554A v.6 (9397 750 13289) 20040930 Product data - PCA9554_9554A v.5 PCA9554_9554A v.5 (9397 750 10163) 20020726 Product data 853-2243 28672 of PCA9554_9554A v.4 26 July 2002 PCA9554_9554A v.4 (9397 750 09817) 20020513 Product specification - PCA9554_9554A v.3 PCA9554_9554A v.3 (9397 750 08342) 20010507 Product specification - PCA9554_9554A v.2 PCA9554_9554A v.2 (9397 750 08209) 20010319 Product specification - PCA9554_9554A v.1 PCA9554_9554A v.1 (9397 750 08159) 20010319 Product specification - - PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 32 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9554_9554A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 33 of 35 PCA9554; PCA9554A NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with interrupt Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9554_9554A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 © NXP B.V. 2013. All rights reserved. 34 of 35 NXP Semiconductors PCA9554; PCA9554A 8-bit I2C-bus and SMBus I/O port with interrupt 19. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 6.5 6.6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register 0 - Input Port register . . . . . . . . . . . . . 7 Register 1 - Output Port register. . . . . . . . . . . . 7 Register 2 - Polarity Inversion register . . . . . . . 8 Register 3 - Configuration register . . . . . . . . . . 8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device address . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 Application design-in information . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Handling information. . . . . . . . . . . . . . . . . . . . 22 Soldering of SMD packages . . . . . . . . . . . . . . 22 Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering: PCB footprints. . . . . . . . . . . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32 Legal information. . . . . . . . . . . . . . . . . . . . . . . 33 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Contact information. . . . . . . . . . . . . . . . . . . . . 34 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 March 2013 Document identifier: PCA9554_9554A