PSoC® Creator™ Component Data Sheet
EZ I2C Slave
1.50
Features
•
Industry standard Philips I2C bus compatible interface
•
Emulates common I2C EEPROM interface
•
Only two pins (SDA and SCL) required to interface to I2C bus
•
Standard data rate up to 1 Mbps
•
High level API requires minimal user programming
•
Support one or two address decoding
General Description
The EZ I2C Slave component implements an I2C register-based slave device. The I2C bus is an
industry standard, two wire hardware interface developed by Philips®. The master initiates all
communication on the I2C bus and supplies the clock for all slave devices. The EZ I2C Slave
supports the standard mode with speeds up to 1000 kbps and is compatible with multiple
devices on the same bus.
The EZ I2C Slave is a unique implementation of an I2C slave in that all communication between
the master and slave is handled in the ISR (Interrupt Service Routine) and requires no
interaction with the main program flow. The interface appears as shared memory between the
master and slave. Once the Start() function is executed, there is little need to interact with the
API.
When to use a EZ I2C Slave
This component is best used when a shared memory model between the I2C Slave and I2C
Master is desired. The EZ I2C Slave buffer/s may be defined as any variable, array, or structure
in the user’s code without any thought of the I2C protocol. The I2C master may view any of the
variables in this buffer and modify the variables defined by the SetBuffer1 or SetBuffer2 function.
PRELIMINARY
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-62101 Rev. *A
Revised November 21, 2010
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
Input/Output Connections
This section describes the various input and output connections for EZ I2C Slave.
SDA – In/Out
This is the I2C data signal. It is a bi-directional data signal used to transmit or receive all bus
data. This pin should be configured as Open-Drain, Drive Low.
SCL – In/Out
The SCL signal is the master generated I2C clock. Although the slave never generates the clock
signal, it may hold it low until it is ready to NAK or ACK the latest data or address. This pin
should be configured as Open-Drain, Drive Low.
Schematic Macro Information
The default EZ I2C Slave in the Component Catalog is a schematic macro using an EZ I2C Slave
component with default settings. The EZ I2C Slave component is connected to a Pins
component, which is configured as an SIO pair.
PRELIMINARY
Page 2 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
Parameters and Setup
Drag an EZ I2C component onto your design and double-click it to open the Configure dialog.
The EZ I2C component provides the following parameters.
I2C Bus Speed
This parameter is used to set the I2C bus speed value from 50 kbps to 1 Mbps; the actual speed
may differ. The standard speeds are 50 kbps, 100 kbps (default), 400 kbps, and 1000 kbps. This
speed is referenced from the system bus clock.
Number of Addresses
This option determines if 1 (default) or 2 independent I2C slave addresses are recognized. If two
addresses are recognized, address detection will be performed in software and not hardware,
therefore the “Wake up from the low power modes” option becomes invalid.
Primary Slave Address
This is the primary I2C slave address (default is 4). This value can be entered in decimal and
hexadecimal format (the “0x” should be typed before the number).
Secondary Slave Address
This is the secondary I2C slave address (default is 5). This value can be entered in decimal and
hexadecimal format (the “0x” should be typed before the number). This second address is only
valid when the Number of Addresses parameter is set to 2. The primary and secondary slave
addresses must be different.
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 3 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
Sub-address Size
This option determines what range of data can be accessed. A sub-address of 8 (default) or 16
bits may be selected. If an address size of 8 bits is used, the master may only access data
offsets between 0 and 254. You may also select a sub-address size of 16 bits. That will allow the
I2C master to access data arrays of up to 65,535 bytes at each slave address.
I2C pins connected to
This option allows configuring what pins (Any, I2C0 or I2C1) I2C bus is connected to. The EZ I2C
component is able to wake up device from the Sleep mode on slave address match only if bus
pins are connected to I2C0 or I2C1 ports.
Enable wakeup from the Sleep mode
This parameter allows the device to be woken up from Sleep mode on slave address match. This
option is disabled by default. Wake up on address match option is valid if a single I2C address is
selected and the SDA and SCL signals are connected to SIO ports (I2C0 or I2C1).
Consult device errata for this feature availability. The possibility of EZ I2C to wake up device on
slave address match should be enabled while switching to the sleep mode, refer to the "Power
Management APIs" section of the System Reference Guide.
Clock Selection
The clock is tied to the system bus clock and cannot be changed by the user. The I2C block
supports 3, 6, 12, 24, 48, 96-102 MHz system bus clock for 100 kHz or 400 kHz operation in
PSoC 3 ES2, ES3 and PSoC 5 ES1. Later device’s revisions support all system bus clock
frequencies. Consult device errata for more information.
Resources
The fixed I2C block is used for this component.
Application Programming Interface
Application Programming Interface (API) routines allow you to configure the component using
software. The following table lists and describes the interface to each function. The subsequent
sections cover each function in more detail.
By default, PSoC Creator assigns the instance name "EZI2C_1" to the first instance of a
component in a given design. You can rename it to any unique value that follows the syntactic
rules for identifiers. The instance name becomes the prefix of every global function name,
variable, and constant symbol. For readability, the instance name used in the following table is
"EZI2C".
PRELIMINARY
Page 4 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
Function
Description
2
void EZI2C_Init(void)
Initializes/restores default EZ I C configuration provided with customizer.
void EZI2C_Enable(void)
Enables component operation.
void EZI2C_Start(void)
Starts responding to I C traffic. (Enables interrupt)
void EZI2C_Stop(void)
Stops responding to I C traffic (Disables interrupt)
void EZI2C_EnableInt(void)
Enables interrupt, Start does this automatically.
void EZI2C_DisableInt(void)
Disables interrupt, Stop does this automatically.
void EZI2C_SetAddress1(uint8 addr)
Sets the I C primary address that it should respond.
uint8 EZI2C_GetAddress1(void)
Returns the I C address for the primary device.
void EZI2C_SetBuffer1(uint16 bufSize,
uint16 rwBoundry, void * dataPtr);
Sets the buffer pointer for the primary address for both reads and writes.
uint8 EZI2C_GetActivity(void)
Checks status on device activity.
void EZI2C_SaveConfig(void)
Saves the current user configuration of the EZ I C component.
void EZI2C_RestoreConfig(void)
Restores the previously saved by EZI2C_SaveConfig() or EZI2C_Sleep()
configuration of the EZI2C component.
void EZI2C_Sleep(void)
Saves component enable state and configuration. Stops component
operation.
void EZI2C_Wakeup(void)
Restores component enable state and configuration. Should be called
just after awaking from sleep.
2
2
2
2
2
Optional Second Address API
These commands are present only if two I2C addresses are enabled.
Function
Description
2
void EZI2C_SetAddress2(uint8 addr)
Sets the I C secondary address that it should respond.
uint8 EZI2C_GetAddress2(void)
Returns the I C address for the secondary device.
void EZI2C_SetBuffer2(uint16 bufSize,
uint16 rwBoundry, void * dataPtr);
Sets the buffer pointer for the secondary address for both reads and
writes.
2
Optional Sleep/Wake modes
These functions are only available if a single address is used and the SCL and SDA signals are
routed to the I2C ports.
Function
Description
2
void EZI2C_SlaveSetSleepMode(void)
Disables the run time I C regulator and enables the sleep Slave I2C.
void EZI2C_SlaveSetWakeMode(void)
Disables the sleep EZ I C slave and re-enables the run time I C.
2
2
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 5 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
Global Variables
Function
Description
2
EZI2C_initVar
Indicates whether the EZ I C has been initialized. The variable is initialized to 0 and set to
1 the first time EZI2C_Start() is called. This allows the component to restart without
reinitialization in after the first call to the EZI2C_Start() routine.
If reinitialization of the component is required the variable should be set to 0 before the
2
EZI2C_Start() routine is called. Alternately, the EZ I C can be reinitialized by calling the
EZI2C_Init() and EZI2C_Enable() functions.
EZI2C_dataPtrS1
Stores pointer to the data exposed to an I C master for the first slave address.
EZI2C_rwOffsetS1
Stores offset for read and write operations, is set at each write sequence of the first slave
address.
EZI2C_rwIndexS1
Stores pointer to the next value to be read or written for the first slave address.
EZI2C_wrProtectS1
Stores offset where data is read only for the first slave address.
EZI2C_bufSizeS1
Stores size of data array exposed to an I C master for the first slave address.
EZI2C_dataPtrS2
Stores pointer to the data exposed to an I C master for the second slave address.
EZI2C_rwOffsetS2
Stores offset for read and write operations, is set at each write sequence of the second
slave device.
EZI2C_rwIndexS2
Stores pointer to the next value to be read or written for the second slave address.
EZI2C_wrProtectS2
Stores offset where data is read only for the second slave address.
EZI2C_bufSizeS2
Stores size of data array exposed to an I C master for the second slave address.
EZI2C_curState
Stores current state of an I C state machine.
EZI2C_curStatus
Stores current status of the component.
2
2
2
2
2
void EZI2C_Init(void)
2
Description:
Initializes/restores default EZI C configuration provided with customizer. Usually called in
EZI2C_Start(). All changes applied by API to the component's configuration will be reset.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
void EZI2C_Enable(void)
Description:
Enables the I2C block operation, sets interrupt priority, sets interrupt vector, clears ending
interrupts and enables interrupts. Clears status variables and reset state machine variable.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
PRELIMINARY
Page 6 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
void EZI2C_Start(void)
Description:
Starts the component and enables the interrupt. If this function is called at first (or
EZI2C_initVar was cleared, then EZI2C_Init() function is called and all offsets and pointers
are reset. Anyway, the state machine state is set to IDLE, status variable is cleared and the
interrupt is enabled.
Parameters:
None.
Return Value:
None.
Side Effects:
This component automatically enables its interrupt. If I C is enabled without the interrupt
2
enabled, it could lock up the I C bus.
2
void EZI2C_Stop(void)
2
Description:
Disables the I C block's slave operation and the corresponding interrupt.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
void EZI2C_EnableInt(void)
Description:
Enables the interrupt service routine This is normally handled with the Start() command.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
void EZI2C_DisableInt(void)
2
Description:
Disables I C interrupts. Normally this function is not required since the Stop function disables
2
2
the interrupt. If the I C interrupt is disabled while the I C master is still running, it may cause
2
the I C bus to lock up.
Parameters:
None.
Return Value:
None.
Side Effects:
If the I C interrupt is disabled and the master is addressing the current slave, the bus will be
locked until the interrupt is re-enabled.
2
void EZI2C_SetAddress1(uint8 address)
2
Description:
This function sets the main address of this I C slave device. This value may be any value
between 0 and 127.
Parameters:
address: The 7-bit slave address between 0 and 127.
Return Value:
None.
Side Effects:
None.
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 7 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
uint8 EZI2C_GetAddress1(void)
2
Description:
Returns the I C slave address for the primary device.
Parameters:
None.
Return Value:
The same I C slave address set by SetAddress1 or the default I C address.
Side Effects:
None.
2
2
void EZI2C_SetBuffer1(uint16 bufSize, uint16 rwBoundry, void * dataPtr)
Description:
This function sets the buffer pointer, size and read/write area for the slave data. This is the
2
data that is exposed to the I C Master.
Parameters:
bufSize: Size of the buffer in bytes.
rwBoundry: Sets how many bytes are writable in the beginning of the buffer. This value must
be less than or equal to the buffer size.
dataPtr: Pointer to the data buffer.
Return Value:
None
Side Effects:
None.
uint8 EZI2C_GetActivity(void)
Description:
This function returns a nonzero value if the I2C read or write cycle occurred since the last
time this function was called. The activity flag resets to zero at the end of this function call.
The Read and Write busy flags are cleared when read, but the "BUSY" flag is only cleared by
an I2C Stop.
Parameters:
A non-zero value is returned if activity is detected.
Return Value:
Status of I C activity.
2
Constant
Side Effects:
Description
EZI2C_STATUS_READ1
Set if Read sequence is detected for first address. Cleared
when status read.
EZI2C_STATUS_WRITE1
Set if Write sequence is detected for first address. Cleared
when status read.
EZI2C_STATUS_READ2
Set if Read sequence is detected for second address (if
enabled). Cleared when status read.
EZI2C_STATUS_WRITE2
Set if Write sequence is detected for second address (if
enabled). Cleared when status read.
EZI2C_STATUS_BUSY
Set if Start detected, cleared when stop detected.
EZI2C_STATUS_ERR
Set when I C hardware detected, cleared when status read.
2
None.
PRELIMINARY
Page 8 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
void EZI2C_SetAddress2(uint8 address)
2
Description:
Sets the I C slave address for the second device. This value may be any value between 0
2
and 127. This function is only provided if two I C addresses have been selected in the user
parameters.
Parameters:
address: The 7-bit slave address between 0 and 127.
Return Value:
None.
Side Effects:
None.
uint8 EZI2C_GetAddress2(void)
2
2
Description:
Returns the I C slave address for the second device. This function is only provided if two I C
addresses have been selected in the user parameters.
Parameters:
None.
Return Value:
The same I C slave address set by SetAddress2 or the default I C address.
Side Effects:
None.
2
2
void EZI2C_SetBuffer2(uint16 bufSize, uint16 rwBoundry, void * dataPtr)
Description:
This function sets the buffer pointer, size and read/write area for the second slave data. This
2
2
is the data that is exposed to the I C Master for the second I C address. This function is only
2
provided if two I C addresses have been selected in the user parameters.
Parameters:
bufSize: Size of the buffer exposed to the I C master.
2
2
rwBoundry: Sets how many bytes are readable and writable by the the I C master.
This value must be less than or equal to the buffer size. Data located at offset rwBoundry and
above are read only.
2
dataPtr: This is a pointer to the data array or structure that is used for the I C data buffer.
Return Value:
None.
Side Effects:
None.
void EZI2C_SlaveSetSleepMode(void)
2
2
Description:
Disables the run time I C regulator and enables the sleep Slave I C. Should be called just
2
prior to entering sleep. This function is only provided if a single I C address is used.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 9 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
void EZI2C_SlaveSetWakeMode(void)
2
2
Description:
Disables the sleep Ez I C slave and re-enables the run time I C. Should be called just after
awaking from sleep. Must preserve address to continue. This function is only provided if a
2
single I C address is used.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
void EZI2C_Sleep(void)
Description:
Saves component enable state and configuration. Stops component operation. Should be
called just prior to entering sleep. If "Enable wakeup from the Sleep mode" is properly
configured and enabled, this function should not be called.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
void EZI2C_Wakeup(void)
Description:
Restores component enable state and configuration. Should be called just after awaking from
sleep.
Parameters:
None.
Return Value:
None.
Side Effects:
Calling this function before EZI2C_SaveConfig() or EZI2C_Sleep() will lead to unpredictable
results.
void EZI2C_SaveConfig(void)
2
Description:
Saves the current user configuration of the EZ I C component.
Parameters:
None.
Return Value:
None.
Side Effects:
None.
void EZI2C_RestoreConfig(void)
Description:
Restores the previously saved by EZI2C_SaveConfig() or EZI2C_Sleep() configuration of the
2
EZ I C component.
Parameters:
None.
Return Value:
None.
Side Effects:
Calling this function before EZI2C_SaveConfig() or EZI2C_Sleep() will lead to unpredictable
results.
PRELIMINARY
Page 10 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
Sample Firmware Source Code
The following is a C language example demonstrating the basic functionality of the EZ I2C
component. This example assumes the component has been placed in a design with the default
name "EZI2C_1".
Note If you rename your component you must also edit the example code as appropriate to
match the component name you specify.
/*******************************************************************************
* Example code to demonstrate the use of the EZ I2C
*
* This example enables two Slave addresses. The buffer for
* the first is set to the structure MyI2C_Regs and the
* buffer for the second address is set to the constant
* string DESC. The slave addresses for buffer1 and buffer2
* are set to 6 and 7 respectively.
*
* Parameter Settings:
*
BusSpeed_kHz: 400
*
EnableWakeup: false
*
I2C_Address1: 4 (Does not matter since program resets to 6)
*
I2C_Address2: 5 (Does not matter since program resets to 7)
*
I2C_Addresses: 2
*
Sub_Address_Size: Width_8_bits
*
*******************************************************************************/
#include <device.h> /* Part specific constants and macros */
typedef struct _EZ2C_REGS
{
uint8 stat;
/* R/W
uint8 cmd;
/* R/W
int16 volts;
/* R/W
uint8 str[6];
/* Read only
} EZ2C_REGS;
variable */
variable */
variable */
to I2C */
EZ2C_REGS myRegs;
const char desc[] = "Hello I2C Master";
void main()
{
/* Enable global interrupts */
CYGlobalIntEnable;
/* Turn on EZI2C */
EZI2C_1_Start();
/* Set up Buffer1 */
EZI2C_1_SetBuffer1(sizeof(myRegs), 4, (void *) &myRegs);
/* Set up buffer2 */
EZI2C_1_SetBuffer2(sizeof(desc), 10, (void *) &desc);
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 11 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
/* Change address1 to 6 */
EZI2C_1_SetAddress1(6);
/* Change address2 to 7 */
EZI2C_1_SetAddress2(7);
while(1)
{
/* Place user code here to update and read structure data. */
}
}
Functional Description
This component supports only an I2C slave configuration with one or two I2C addresses. The
addresses are right justified.
This component requires that you enable global interrupts since the I2C hardware is interrupt
driven. Even though this component requires interrupts, you do not need to add any code to the
ISR (Interrupt Service Routine). The module services all interrupts (data transfers) independent
of your code. The memory buffers allocated for this interface look like simple dual port memory
between your application and the I2C Master.
If required, you can create a higher level interface between a master and this slave by defining
semaphores and command locations in the data structure.
Memory Interface
To an I2C master the interface looks very similar to a common I2C EEPROM. The EZ I2C API is
treated as RAM or FLASH that can be configured as simple variables, arrays, or structures. In a
sense it acts as a shared memory interface between your program and an I2C master on the I2C
bus. The API allows the user to expose any data structure to an I2C Master. The component only
allows the I2C master to access the specified area of memory and prevents any reads or writes
outside that area. The data exposed to the I2C interface can be a single variable, an array of
values, or a structure. All that is required is a pointer to the start of the variable or data structure
when initialized. The interface to the internal processor or I2C master is identical for both slave
addresses. For example, if the buffer for the primary slave address is configured as follows:
typedef struct _EZ2C_REGS
{
uint8 stat;
uint8 cmd;
int16 volts;
uint8 str[6];
} EZ2C_REGS;
/*
/*
/*
/*
R/W variable
R/W variable
R/W variable
Read only to
*/
*/
*/
I2C */
EZ2C_REGS myRegs;
EZI2C_SetBuffer1(sizeof(myRegs), 4, (void *) &myRegs);
PRELIMINARY
Page 12 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
The buffer representation in memory could be represented as shown in the following diagram:
Figure 1 Memory representation of the EZI2C buffer exposed to an I2C Master
This structure may contain any group of variables with any name as long as it is contiguous in
memory and referenced by a pointer. The interface (I2C Master) only sees it as an array of bytes,
and cannot access any memory outside the defined area. Using the example structure above, a
supplied API is used to expose the data structure to the I2C interface.
EZI2C_SetBuffer1(sizeof(myRegs), 4, (void *) &myRegs);
The first parameter sets the size of the exposed memory to the I2C interface. In this case, it is the
entire structure. The second parameter sets the boundary between the read/write and read only
areas by setting the number of bytes in the read/write area. The read/write area is first, followed
by the read only area. In this case, only the first 4 bytes may be written, but all bytes may be
read by the I2C master. The third parameter is a pointer to the data.
In the following example a 15-byte array is created and exposed to the I2C interface. The first 8
bytes of the array are read/write, and the remaining 7 (15-8) bytes are read only.
char theArray[15];
EZI2C_SetBuffer2(15, 8, (void *) theArray);
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 13 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
The following simple example shows only a single integer (2 bytes) is exposed. Both bytes are
readable and writable by the I2C master.
uint16 myVar;
EZI2C_SetBuffer1(2, 2, (void *) (&myVar));
Interface as Seen by External Master
The EZ I2C Slave component supports basic read and write operations for the RAM area and
read only operations for the FLASH area. The two buffer area interfaces contain separate data
pointers that are set with the first one or two data bytes of a write operation, depending on the
sub address size (Sub_Address_Size parameter). For the rest of this discussion, we will
concentrate on an 8-bit sub address size. For the 16-bit sub address size bus communication will
the same, but the data address field will have 16-bit length, not 8-bit.
Figure 2 The 8 bits and 16 bits sub address size (from top to bottom)
When writing one or more bytes, the first data byte is always the data pointer. The byte after the
data pointer is written into the location pointed to by the data pointer byte. The second data byte
is written to the data pointer plus one and so on. This data pointer increments for each byte read
or written, but is reset to the first value written at the beginning of each new read operation. A
new read operation begins to read data at the location pointed to by the data pointer.
The following diagram illustrates the bus communication for an 8-bit data write, data pointer
write, and a data read operation. Remember that a data write operation always rewrites the data
pointer.
Figure 3 Write x bytes to I2C slave
S SLAVE ADDR R/W A
DATA PTR
from slave to master
A
DATA[n]
A
DATA[n+1]
A
DATA[n+x]
A
P
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
from master to slave
S = START condition
P = STOP condition
PRELIMINARY
Page 14 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
For example, if the data pointer is set to four, a read operation begins to read data at location
four and continue sequentially until the end of the data or the host completes the read operation.
For example, if the data pointer is set to four, each read operation resets the data pointer to four
and reads sequentially from that location. This is true whether a single or multiple read
operations are performed. The data pointer is not changed until a new write operation is initiated.
If the I2C master attempts to write data past the area specified by the SetBuffer1() function, the
data is discarded and does not affect any RAM inside or outside the designated RAM area. Data
cannot be read outside the allowed range. Any read requests by the master, outside the allowed
range results in the return of invalid data.
Figure 4 Illustrates the data pointer write for and 8 Bit data Pointer.
Figure 4 Set slave data pointer
Figure 5 illustrates the read operation for 8 Bit data pointer. Remember that a data write
operation always rewrites the data pointer.
Figure 5 Read x bytes from I2C slave
At reset, or power on, the EZ I2C Slave component is configured and APIs are supplied, but the
resource must be explicitly turned on using the EZI2C_Start() function.
Detailed descriptions of the I2C bus and the implementation here are available in the complete
I2C specification available on the Philips web site, and by referring to the device data sheet
supplied with PSoC Creator.
External Electrical Connections
As the block diagram illustrates, the I2C bus requires external pull up resistors. The pull up
resistors (RP) are determined by the supply voltage, clock speed, and bus capacitance. Make
the minimum sink current for any device (master or slave) no less than 3 mA at VOLmax = 0.4V
for the output stage. This limits the minimum pull up resistor value for a 5V system to about
1.5 k . The maximum value for RP depends upon the bus capacitance and clock speed. For a
5V system with a bus capacitance of 150 pF, the pull-up resistors are no larger than 6 k . For
more information on "The I2C -Bus Specification", see the Philips web site at www.philips.com.
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 15 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
Figure 6 Connection of devices to the I2C-bus
+VDD
pull-up
resistors
Rp
Rp
SDA (Serial Data Line)
SCL (Serial Clock Line)
Device 1
Device 2
Note Purchase of I2C components from Cypress or one of its sublicensed Associated
Companies, conveys a license under the Philips I2C Patent Rights to use these components in
an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
Interrupt Service Routine
The interrupt service routine is used by the component code itself and should not be modified by
the user.
Component Debug Window
The EZ I2C component supports the PSoC Creator component debug window. Refer to the
appropriate device data sheet for a detailed description of each register. The following registers
are displayed in the EZ I2C component debug window.
Register:
EZI2C_XCFG
Name:
Extended Configuration Register
Description:
Used to configure some of the advanced configuration options of the fixed function block.
Register:
EZI2C_ADDR
Name:
Slave Address Register
Description:
Used to indicate the 7-bit slave address for hardware address match detection.
Register:
EZI2C_CFG
Name:
Configuration Register
Description:
Used to configure the standard configuration options.
PRELIMINARY
Page 16 of 18
Document Number: 001-62101 Rev. *A
PSoC® Creator™ Component Data Sheet
EZ I2C Slave
Register:
EZI2C_CSR
Name:
Status Register
Description:
For the Fixed Function block this register is the status feedback register from hardware and
includes some run-time control bits as a shared register.
Register:
EZI2C_DATA
Name:
Transmit and Receive Data Register
Description:
Used to load transmit data and read received data.
References
Not applicable
DC and AC Electrical Characteristics
5.0V/3.3V DC and AC Electrical Characteristics
Parameter
Typical
Min
Max
Units
Conditions and Notes
Input
Input Voltage Range
---
Vss to Vdd
V
Input Capacitance
---
---
pF
Input Impedance
---
---
Maximum Clock Rate
---
67
MHz
Component Changes
This section lists the major changes in the component from the previous version.
Version
Description of Changes
Reason for Changes / Impact
1.50.a
Moved component into subfolders of the component
catalog
1.50
Standard data rate has been updated to support up
to 1 Mbps.
Allows setting up I C bus speed up to 1 Mbps.
Keil reentrancy support was added.
Support for PSoC 3 with the Keil compiler the
capability for functions to be called from
multiple flows of control.
2
PRELIMINARY
Document Number: 001-62101 Rev. *A
Page 17 of 18
EZ I2C Slave
PSoC® Creator™ Component Data Sheet
Version
Description of Changes
Added Sleep/Wakeup and Init/Enable APIs.
To support low power modes, as well as to
provide common interfaces to separate control
of initialization and enabling of most
components.
The XML description of the component has been
added.
This allows for the PSoC Creator to provide a
mechanism for creating new debugger tool
windows for this component.
Added support for the PSoC 3 ES3 devices.
The required changes have been applied to
support hardware changes between PSoC 3
ES2 and ES3 devices.
The default schematic template has been added to
the component catalog.
Every component should have a schematic
template.
2
1.20.a
2
The EZ I C's bus speed generation was fixed.
Previously it was x4 greater than should be. Added
more comments in the source code to describe bus
speed calculation.
The proper I C bus speed calculation and
generation.
Optimized form height for Microsoft Windows 7.
In Windows 7 scrollbar appeared just after
customizer start.
Added tooltips for address input boxes with 'Use 0x
prefix for hexadecimals' text.
To inform user about possibility of hexadecimal
input.
Moved component into subfolders of the component
catalog.
Added information to the component that advertizes
its compatibility with silicon revisions.
1.20
Reason for Changes / Impact
The tool reports an error/warning if the
component is used on incompatible silicon. If
this happens, update to a revision that supports
your target device
The Configure dialog was updated.
Digital Port was changed to Pins component in the
schematic
© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PSoC® is a registered trademark, and PSoC Creator and Programmable System-on-Chip are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and
foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in
conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as
specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
PRELIMINARY
Page 18 of 18
Document Number: 001-62101 Rev. *A