#
$65<)343
®
89#45;.ð;#&026#)ODVK#((3520
)HDWXUHV
• Organization: 128K × 8 bits
• Sector Erase architecture
- Four 32K × 8 sectors
• Single 5.0±0.5V power supply for read/write operations
• High speed 120/150 ns address access time
• Low power consumption:
- 30 mA maximum read current
- 50 mA maximum program current
- 1.5 mA maximum standby current
- 1 mA maximum standby current (low power)
• 10,000 write/erase cycle endurance
• JEDEC standard write cycle commands
- protects data from accidental changes
• Program/erase cycle end signals:
- Data polling
- DQ6 toggle
• Low VCC write lock-out below 3.2V
• JEDEC standard packages and pinouts:
- 32-pin DIP
- 32-pin PLCC
- 32-pin TSOP
/RJLF#EORFN#GLDJUDP
3LQ#DUUDQJHPHQW
DQ0~DQ7
State
control
Command
register
Program voltage
switch
Data
latch
Chip enable
Output enable
Logic
VCC
WE
NC*
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
AS29F010
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
Program/erase
pulse timer
A0~A16
Y-Decoder
Y-Gating
X-Decoder
1,048,576 bit
Cell matrix
32-pin
TSOP
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS29F010
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
)/$6+
Low VCC detector
Address latch
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
CE
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A12
A15
A16
NC
VCC
WE
NC*
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
4
3
2
1
32
31
30
Input/output
buffers
32-pin
PLCC
14
15
16
17
18
19
20
WE
Erase voltage
switch
AS29F010
32-pin
PDIP
VCC
VSS
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
6HOHFWLRQ#JXLGH
AS29F010-120
AS29F010-150
Unit
Maximum access time
tAA
120
150
ns
Chip enable access time
tCE
120
150
ns
Output enable access time
tOE
50
50
ns
','#4407333:0$1#72:233
$//,$1&(#6(0,&21'8&725
4
Copyright ©1998 Alliance Semiconductor. All rights reserved.
$65<)343
®
)XQFWLRQDO#GHVFULSWLRQ
The AS29F010 is a high performance 1 megabit 5 volt-only Flash memory organized as 128K bytes of 8 bits each. It is divided into four
sectors of 32K bytes each. Each sector is separately erased and programmed without affecting data in the other sectors. All prog ram, erase,
and verify operations are 5-volt only, and require no external 12V supply pin. All required features for in-system programmability are
provided.
The AS29F010 provides high performance with a maximum access time of 120, or 150 ns. Chip Enable ( CE), Output Enable (OE), and
Write Enable (WE) pins allow easy interface with the system bus.
Program, erase, and verify operations are controlled with an on-chip command register using a JEDEC standard Write State Machine
approach to enter commands. Each command requires four write cycles to be executed. Address and data are latched internally during all
write, erase, and verify operations, and an internal timer terminates each command. The chip has a typical timer period of 200 µ s for all
commands but Erase, which has a typical period of 800 ms. Under nominal conditions, a sector can be completely programmed and verified
in less than 12 seconds. To program, erase, and verify a sector typically takes less than 18 seconds.
Data protection is provided by a low-VCC lockout and by error checking in the Write State Machine. DATA polling and Toggle Bit modes are
used to show that the chip is executing a command when the AS29F010 is read during a write or erase operation. After Erase or P ogram
commands,Verify-1 andVerify-0 command modes ensure sufficient margin for reliable operation. (See command summary on page 5.)
The AS29F010 is packaged in 32-pin DIP, PLCC and TSOP packages with JEDEC standard pinouts for one megabit Flash memories.
$UUD\#DUFKLWHFWXUH#DQG#GDWD#SRODULW\
The array consists of 128K (131,072) bytes divided into four sectors of 32K bytes each. Addresses A15 and A16 select the four sectors:
Sector
Address range
Address pins
Function
0
00000h–07FFFh
A0–A5
CA: Column addresses 00–3Fh
1
08000h–0FFFFh
A6–A14
RA: Row addresses 000–1FFh
2
10000h–17FFFh
A15–A16
SA: Sector addresses 0–3h
3
18000h–1FFFFh
)/$6+
The AS29F010 is shipped in the erased state with all bits set to 1. Programmed bits are set to 0. Data is programmed into the a ray one byte
at a time. All programmed bits remain set to 0 until the sector is erased and verified using the SectorErase and Verify algorit hm. Erase returns
all bytes in a 32K sector to the erased state FFh, or all bits set to 1. Each sector is erased individually with no effect on the other sectors.
2SHUDWLQJ#PRGHV
The AS29F010 is controlled by a Write State Machine (WSM) that interprets and executes commands. At power-up the WSM is reset to
normal read mode. Once a command is initiated by writing data into the DQ pins with the WE pin, the WSM enters the command mode and
keeps the chip powered up until the command is finished. After the command is terminated by the internal timer, the WSM returns to the
normal read mode.
5
$//,$1&(#6(0,&21'8&725
','#4407333:0$1#72:233
$65<)343
#
®
0RGH#WDEOH
Mode
CE
OE
WE
A0
A9
DQ
Read
L
L
H
A0
A9
DOUT
Output disable
L
H
H
X
X
High Z
Standby
H
H
H
X
X
High Z
Mfr. code
L
L
H
L
Vh
52h
Device code
L
L
H
H
Vh
CODE (03h,04h,06h)
Write command
L
H
L
A0
A9
DIN
†Key:
L =Low (<VIL); H = High (>VIH); Vh = 11.5–12.5V; X =Don’t care
Read mode: Selected with CE and OE low, WE high. Data is valid tAA after addresses are stable, tCE after CE is low and tOE after OE is low.
Output disable: Part remains powered up; but outputs disabled with OE pulled high.
Standby: Part is powered down, and ICC reduced to 1.5 mA for TTL input levels (<1.0 mA for CMOS input levels).
Mfr. (manufacturer) code, Device code: Selected by A9 = 11.5–12.5V. When CE and OE are pulled low the outputs are enabled and a data byte is read out.
When A0 is pulled low the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high DOUT = 03h,04h, 06h, the
Alliance device codes for the AS29F010.
Write command: Selected by CE and WE pulled low, OE pulled high. Initiates command mode in the WSM and latches addresses and data into the chip. Once
a write command starts, the WSM stays in command mode until the command is completed or it times out. Addresses are latched on the falling edge of WE
and CE, whichever occurs later; data is latched on the rising edge o WE and CE, whichever occurs first. The WE signal is filtered to prevent spurious events
from being detected as write commands.
&RPPDQG#IRUPDW
All commands require four bus write cycles to execute. After four write cycles the command is executed until terminated by the i nternal
timer. For verify commands a read operation after Write[4] in a write command bus cycle reads out the data from thearray. For manufacturer
and device code commands the ID code is read out. For other operations a read operation reads out a status byte on the outputs.
Data in
Bus write[1]
5555h
AAh
Bus write[2]
2AAAh
55h
Bus write[3]
5555h
Command code
Bus write[4]
Address in
Data in
Bus read
Address in
DOUT
Errors and timeout: Any of the following conditions sets the error flag.
Command timeout: For each operation the address and data are latched at
bus Write[4] and held until the operation completes and times-out. After
time-out the WSM returns the AS29F010 to normal mode. Each individual
operation requires the 4-cycle write command sequence to execute. The
AS29F010 does not remain in command mode after time-out. When a
command times-out only the error flag is not reset.
• Any write command which does not match the sequence above for Write{1]. Write{2], and Write[3].
• Any write cycle that follows more than 150 µs after the previous write cycle.
• The command Data [3] in Write[3] has more than one bit set high. This indicates conflicting commands.
• VCC drops below VLKO during command execution.
Once the error flag is set, the AS29F010 times out and returns to normal Readmode. The error flag remains until it is cleared by a reset
command. The error flag can be read by executing a status command and reading the status byte.
&RPPDQG#FRGHV#DQG#WLPH#RXW
The Command Code table displays the bus cycles required for each command mode. Read delay is the minimum delay after Write [4] during
a write command bus cycle before a valid read may be executed. Timeout indicates the maximum delay before the WSM returns the
AS29F010 to normal mode. Erase has a longer timeout than the other modes. Status byte can be read almost immediately after a Write[4], but
the verify commands require a 25 µs delay to read valid data.
','#4407333:0$1#72:233
$//,$1&(#6(0,&21'8&725
6
)/$6+
Address in
$65<)343
®
&RPPDQG#FRGH#WDEOH
Mode
DIN[3]
Write[3] data
AIN[4]
Write[4]
address
DIN[4]
data
Read address
Read data
Read delay
Maximum time out
Reset
00h
x
x
0000h
Status
100 ns
250 µs
Status
01h
x
x
0000h
Status
100 ns
250 µs
ID Read
code
02h
0000h
0001h
x
x
0000h
0001h
Mfr. code
Device code
52h 100 ns
04h 100 ns
250 µs
Verify-0
04h
AIN
x
AIN
DOUT
25 µs
250 µs
Verify-1
08h
AIN
x
AIN
DOUT
25 µs
250 µs
Converge
10h
AIN
00h
AIN
Status
100 ns
250 µs
Program
40h
AIN
DIN
AIN
Status
100 ns
250 µs
Erase
80h
AIN
FFh
AIN
Status
100 ns
1000 µs
&RPPDQG#DOJRULWKPV
Individual write commands are used together in eight program and erase algorithms to guarantee the AS29F010 operating margins for the
life of the part. Refer to the AS29F010 Programming Specification for details on the algorithms for program and erase operation .
5HFRPPHQGHG#RSHUDWLQJ#FRQGLWLRQV
Parameter
Supply voltage
)/$6+
Input voltage
+7D# #3ƒ&#WR#.:3ƒ&,
Symbol
Min
Typ
Max
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
VIH
2.0
-
VCC + 1.0
V
VIL
–0.5
-
0.8
V
$EVROXWH#PD[LPXP#UDWLQJV
Parameter
Symbol
Min
Max
Unit
Input voltage (Input or DQ pin)
VIN
–1.0
VCC + 1.0
V
Input voltage (A9 pin)
VIN
–1.0
+13.0
V
Output voltage
VOUT
–1.0
VCC + 1.0
V
Power supply voltage
VCC
+4.5
+5.5
V
Operating temperature
TOPR
–55
+125
°C
Storage temperature (plastic)
TSTG
–65
+125
°C
Short circuit output current
IOUT
-
100
mA
Latch-up current
IIN
±100
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
7
$//,$1&(#6(0,&21'8&725
','#4407333:0$1#72:233
$65<)343
#
®
20 ns
20 ns
20 ns
0D[LPXP#QHJDWLYH#RYHUVKRRW#ZDYHIRUP
+0.8V
-0.5V
-2.0V
0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP
VCC+2.0V
VCC+0.5V
+2.0V
20 ns
20 ns
20 ns
'&#HOHFWULFDO#FKDUDFWHULVWLFV
+9&&# #813“3189/#966# #39/#7D# #3ƒ&#WR#.:3ƒ&,
Parameter
Symbol
Test conditions
Min
Max
Unit
Input load current
ILI
VIN = VSS to VCC, VSS = VMAX
-
±1
µA
Output leakage current
ILO
VOUT = VSS to VCC, VSS = VMAX
-
±1
µA
Output short circuit current
IOS
VOUT = 0.5V
-
100
mA
Active current, read @ 6MHz
ICC
CE = VIL, OE = VIH
-
30
mA
Active current, program/erase
ICCPRG
CE = VIL, OE = VIH
-
50
mA
ISB1 (TTL)
CE = VIH
-
1.5
mA
ISB2 (CMOS) CE = VCC
-
1.0
mA
-
2
µA
Standby current
ICCPD
RP = 0V
VIL
0.5
0.8
V
Input: high level
VIH
2.0
VSS + 0.3
V
Output low voltage
VOL
IOL = 12mA
-
0.45
V
VOH1
IOH = -2.5 mA
2.4
-
V
VOH2
IOH = -100 µA
VCC - 0.4
-
V
Output high level
Low VCC lock out voltage
VLKO
3.2
4.2
V
Input HV select voltage
VID
11.5
12.5
V
)/$6+
Input: low level
1RWHV
1
2
3
Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems
caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.)
The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically
is less than 2 mA/MHz with OE at VIH.
ICC active while program or erase operations are in progress.
','#4407333:0$1#72:233
$//,$1&(#6(0,&21'8&725
8
$65<)343
®
$&#SDUDPHWHUV#³#UHDG#F\FOH
+9&&# #813“3189/#966# #39/#7D# #3ƒ&#WR#.:3ƒ&,
-120
Std symbol
Parameter
Min
Max
Min
Max
Unit
tAVAV
tRC
Read cycle time
120
-
150
-
ns
tAVQV
tACC
Address to output delay
-
120
-
150
ns
tELQV
tCE
Chip enable to output
-
120
-
150
ns
tGLQV
tOE
Output enable to output
-
50
-
50
ns
tEHQZ
tDF
Chip enable to output High Z
-
30
-
30
ns
tGHQZ
tDF
Output enable to output High Z
-
30
-
30
ns
tAXQX
tOH
Output hold time from addresses, first
occurrence of CE or OE
0
-
0
-
ns
$&#SDUDPHWHUV#³#ZULWH#F\FOH
)/$6+
-150
JEDEC
symbol
+9&&# #813“3189/#966# #39/#7D# #3ƒ&#WR#.:3ƒ&,
-120
-150
JEDEC
symbol
Std symbol
Parameter
Min
Max
Min
Max
Unit
tAVAV
tWC
Write cycle time
120
-
150
-
ns
tAVWL
tAS
Address setup time
0
-
0
-
ns
tWLAX
tAH
Address hold time
50
-
50
-
ns
tDVWH
tDS
Data setup time
50
-
50
-
ns
tWHDX
tDH
Data hold time
0
-
0
-
ns
tOES
Output enable setup time
0
-
0
-
ns
Output enable hold time: Read
0
-
0
-
ns
tOEH
Output enable hold time:
Toggle and DATA polling
10
-
10
-
ns
tGHWL
tGHWL
Read recover time before write
0
-
0
-
ns
tELWL
tCS
CE setup time
0
-
0
-
ns
tWHEH
tCH
CE hold time
0
-
0
-
ns
tWLWH
tWP
Write pulse width
80
-
80
-
ns
tWHWL
tWPH
Write pulse width high
20
-
20
-
ns
tWHWH1
tWHWH1
Programming pulse time
250
-
250
-
µs
tWHWH2
tWHWH2
Erase pulse time
1000
-
1000
-
µs
tVCS
VCC setup time
2
-
2
-
µs
9
$//,$1&(#6(0,&21'8&725
','#4407333:0$1#72:233
$65<)343
#
®
5HDG#ZDYHIRUP
tRC
stable
Addresses
CE
tOF
OE
WE
tOE
tOH
tCE
tACC
Outputs
High Z
enabled
tPWH
High Z
valid data out
:ULWH#FRPPDQG#ZDYHIRUP
tWPH
tAS
tAH
Addresses
tCS
CE
tOES
OE
tWP
WE
tDH
tDS
Outputs
data in
High Z
High-Z
Write[1]
Write[2]
Write[3]
Write[4]
Read
AIN[1] = 5555h
AIN[2] = 2AAAh
AIN[3] = 5555h
AIN[4] = AIN
AIN
DIN[1] = AAh
DIN[2] = 55h
DIN[3] = Com.
DIN[4] = DIN
)/$6+
:ULWH#FRPPDQG#EXV#ZDYHIRUP
Addresses
CE
OE
WE
Outputs
DOUT
For all waveforms, AIN[4:1], and DIN[4:1] = Address and Data for write cycles 1–4; DIN = Data to be programmed at address AIN; Com. = Command byte input
on the DQ pins during Write[3]; DOUT = Status byte, Manufacturer ID code, or array data for verify.
','#4407333:0$1#72:233
$//,$1&(#6(0,&21'8&725
:
$65<)343
®
$&#WHVW#FRQGLWLRQV
+5V
1N3064
or equivalent
Device under test
2.7KΩ
6.2KΩ
100 pF*
GND
1N3064
or equivalent
GND
*including scope
and jig capacitance
GND
/DWFKXS#WROHUDQFH#
Parameter
Min
Max
Unit
Input voltage with respect to VSS on pin A9
-1.0
+13.5
V
Input voltage with respect to VSS on all DQ pins
-1.0
VCC+1.0
V
Current
-100
+100
mA
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
7623#SLQ#FDSDFLWDQFH
+¦# #4#0+]/#7D# #58ƒ&,
Symbol
Parameter
Test setup
Typical
Max
Unit
CIN
Input capacitance
VIN = 0
6
7.5
pF
COUT
Output capacitance
VOUT = 0
8.5
12
pF
CIN2
Control pin capacitance
VIN = 0
7.5
9
µF
)/$6+
3/&&#DQG#3',3#SLQ#FDSDFLWDQFH
+¦# #4#0+]/#7D# #58ƒ&,
Symbol
Parameter
Test setup
Typical
Max
Unit
CIN
Input capacitance
VIN = 0
4
6
pF
COUT
Output capacitance
VOUT = 0
8
12
pF
CIN2
Control pin capacitance
VIN = 0
8
12
µF
(UDVH#DQG#SURJUDPPLQJ#SHUIRUPDQFH
+¦# #4#0+]/#7D# #URRP#WHPSHUDWXUH/#9&&# #89“43(,
Limits
Parameter
Min
Typical
Max
Unit
Sector erase and Verify-1 time (excludes 00h programming prior to erase)
-
6.0
8.2
sec
Sector programming time
-
-
8.2
sec
Chip programming time
-
48
80
sec
Erase program cycles
-
10,000
-
cycles
Byte program time
-
200
250
µs
Byte verify-0 time
-
200
250
µs
;
$//,$1&(#6(0,&21'8&725
','#4407333:0$1#72:233
$65<)343
#
®
'DWD#UHWHQWLRQ
Parameter
Minimum pattern data retention time
Temperature
Min
Unit
150°
10
years
125°
20
years
$65<)343#RUGHULQJ#LQIRUPDWLRQ
Package \ Access time
120 ns
150 ns
Plastic DIP, 600 mil, 32-pin
AS29F010-120PC
AS29F010-150PC
PLCC, 0.55 × 0.45'' 32-pin
AS29F010-120LC
AS29F010-150LC
TSOP, 8×20 mm, 32-pin
AS29F010-120TC
AS29F010-150TC
$65<)343#SDUW#QXPEHULQJ#V\VWHP
AS29F
010
–XXX
X
C
Flash EEPROM prefix
Device number
Address access time
Package: P = PDIP
L = PLCC
T = TSOP
Commercial temperature range,
0°C to 70 °C
)/$6+
','#4407333:0$1#72:233
$//,$1&(#6(0,&21'8&725
<
$65<)343
)/$6+
®
43
$//,$1&(#6(0,&21'8&725
','#4407333:0$1#72:233