NX2138 SINGLE CHANNEL MOBILE PWM CONTROLLER PRODUCTION DATA SHEET Pb Free Product FEATURES DESCRIPTION The NX2138 controller IC is a compact Buck controller n IC with 16 lead MLPQ package designed for step down n DC to DC converter in portable applications. It can be n selected to operate in synchronous mode or non-syn- n chronous mode to improve the efficiency at light n load.Constant on time control provides fast response, good line regulation and nearly constant frequency un- n der wide voltage input range. The NX2138 controller is optimized to convert single supply up to 22V bus voltage to as low as 0.75V output voltage. Over current n protection and FB UVLO followed by latch feature. Other n features includes: internal boost schottky diode, 5V gate n drive capability, power good indicator, over current pro- n tection, over voltage protection and adaptive dead band n control. n n n n Internal boost schottky diode Ultrasonic mode operation available Bus voltage operation from 4.5V to 22V Less than 1uA shutdown current with Enable low Excellent dynamic response with constant on time control Selectable between synchronous CCM mode and diode emulation mode to improve efficiency at light load Programmable switching frequency Current limit and FB UVLO with latch off Over voltage protection with latch off Power good indicator available Pb-free and RoHS compliant APPLICATIONS Notebook PCs and Desknotes Tablet PCs/Slates On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Hand-held portable instruments TYPICAL APPLICATION 4 PGOOD PGOOD TON 9 1u 2 2x10uF PVCC VCC 1u 15 ENSW /MODE 2 14 HDRV 12 NX2138 10 VIN 7V~22V 1n 100k 5V 1MEG 16 2.2 BST 13 1u SW 11 LDRV 8 Vout 1.8V/7A AO4714 5k 10.5k FB 3 NC 1.5uH 2R5TPE330MC 330uF OCSET 10 1 VOUT NC IRF7807 7.5k AGND 6 PGND 7 Figure1 - Typical application of NX2138 ORDERING INFORMATION Device NX2138CMTR Rev. 1.7 06/13/12 Temperature -10 o C to 100 o C Package 4X4 MLPQ-16L Pb-Free Yes 1 NX2138 ABSOLUTE MAXIMUM RATINGS VCC,PVCC to GND & BST to S W voltage ............ -0.3V to 6.5V TON to GND ......................................................... -0.3V to 28V HDRV to S W Voltage .......................................... -0.3V to 6.5V SW to GND ......................................................... -2V to 30V All other pins ........................................................ VCC+0.3V Storage Temperature Range ..................................-65 oC to 150 oC Operating Junction Temperature Range .................-40 oC to 150 oC ESD Susceptibility ............................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM R ATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION NC BST 16 15 14 13 TON ENSW/MODE 4x4 16-LEAD PLASTIC MLPQ θ JA ≈ 46o C/W 12 HDRV VO 1 VCC 2 FB 11 SW 17 PAD 3 10 OCSET 9 PVCC 5 6 7 NC AGND PGND PGOOD 4 LDRV 8 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =5 V, VIN=15V and T A =25oC, unless otherwise specified. PARAMETER VIN recommended voltage range Shut down current VCC,PVCC Supply Input voltage range Operating quiescent current Shut down current Rev. 1.7 06/13/12 SYM Test Condition Min TYP 4.5 ENSW=GND Vin Units 22 V uA 5.5 V 1 4.5 No switching, ENSW=5V ENSW=GND MAX 1.6 1 mA uA 2 NX2138 PARAMETER VCC UVLO Under-voltage Lockout threshold Falling VCC threshold ON and OFF time SYM VCC _UVLO TON operating current ON -time Minimum off time FB voltage Internal FB voltage Input bias current VIN=15V, Rton=1Mohm VIN=9V,VOUT=0.75V,Rton= 1Mohm Vref Line regulation OUTPUT voltage VCC from 4.5 to 5.5 Output range VOUT shut down discharge resistance Soft start time PGOOD Power good high rising threshold PGOOD propagation delay filter ENSW/MODE=GND Power good hysteresis Pgood output switch impedance Pgood leakage current SW zero cross comparator Offset voltage HighNSide Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time Rev. 1.7 06/13/12 Test Condition Min TYP MAX Units 3.9 3.7 4.1 3.9 4.5 4.3 V V 15 uA 312 380 390 590 468 800 ns ns 0.739 0.75 0.761 100 V nA -1 1 % 0.75 3.3 V 30 1.5 ohm ms 90 % Vref NOTE1 2 us NOTE1 5 % 13 1 ohm uA 5 mV R source(Hdrv) I=200mA 1.5 ohm R sink (Hdrv) I=200mA 1.5 ohm THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% 50 50 30 ns ns ns R source(Ldrv) I=200mA 1.5 ohm Rsink(Ldrv) I=200mA 0.5 ohm 50 50 10 ns ns ns TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 3 NX2138 PARAMETER ENSW/MODE threshold and bias current SYM Test Condition PFM/Non Synchronous Mode Ultrasonic Mode Synchronous Mode Shutdown mode Input bias current Current Limit Ocset setting current Over temperature Threshold Hysteresis Under voltage FB threshold Over voltage Over voltage tripp point Internal Schottky Diode Forward voltage drop Rev. 1.7 06/13/12 Leave it open or use limits in spec Min TYP 80% VCC 60% VCC MAX VCC+0 .3V 80% VCC 60% VCC 0.8 2 0 Units V V ENSW/MODE=VCC 5 V V uA ENSW/MODE=GND -5 uA 20 24 155 15 forward current=50mA 28 uA o C C o 70 %Vref 125 %Vref 500 mV 4 NX2138 PIN DESCRIPTIONS PIN NUMBER PIN SYMBOL Rev. 1.7 06/13/12 PIN DESCRIPTION This pin is directly connected to the output of the switching regulator and senses the VOUT voltage. An internal MOSFET discharges the output during turn off. 1 VOUT 2 VCC 3 FB 4 PGOOD 5 NC 6 AGND Analog ground. 7 PGND Power ground. 8 LDRV Low side gate driver output. 9 PVCC Provide the voltage supply to the lower MOSFET drivers. Place a high frequency decoupling capacitor 1uF X5R to this pin. 10 OCSET 11 SW 12 HDRV 13 BST This pin supplies voltage to high side FET drive r. A high freq 1uF X7R ceramic capacitor and 2.2ohm resistor in series are recommended to be placed as close as possible to and connected to this pin and S W pin. 14 NC Not used. 15 ENSW/ MODE Switching converter enable input. Connect to VCC for PFM/Non synchronous mode, connected to an external resistor divider equals to 70%VCC for ultrasonic, connected to GND for shutdown mode, floating or connected to 2V for the synchronous mode. 16 TON VIN sensing input. A resistor connects from this pin to VIN will set the frequency. A 1nF capacitor from this pin to GND is recommended to ensure the proper operation. 17 PAD Used as thermal pad. Connect this pad to ground plane through multiple vias. This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is placed as close as possible to this pin and ground pin. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage from 0.75V to 3.3 V. PGOOD indicator for switching regulato r. It requires a pull up resistor to Vcc or lower voltage. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. Not used. This pin is connected to the drain of the external low side MOSFET and is the input of over current protection(OCP) comparato r. An internal current source is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFE T. This pin is connected to source of high side FE Ts and provide return path for the high side driver. It is also the input of zero current sensing comparato r. High side gate driver output. 5 NX2138 BLOCK DIAGRAM VCC(2) Bias VIN TON(16) 4.3/4.1 ON time pulse genearation VOUT Disable_B Thermal shutdown start BST(13) ODB HD R S VOUT POR VIN HDRV(12) FET Driver HD_IN Q SW(11) 1.8V 5V PVCC(9) FB(3) OCP_COMP LDRV(8) Mini offtime 400ns PGND(7) VREF=0.75V start POR FBUVLO_latch soft start Diode emulation HD VCC ENSW /MODE(15) 1M 1M Disable MODE SELECTION PFM_nonultrasonic Sync OCSET(10) FB OVP 1.25*Vref/0.7VREF OCP_COMP AGND(6) FB FBUVLO_latch PGOOD(4) 0.7*Vref SS_finished VOUT VOUT(1) start 0.9*Vref Figure 2 - Simplified block diagram of the NX2138 Rev. 1.7 06/13/12 6 NX2138 TYPICAL APPLICATION (VIN=7V to 22V, VOUT=1.8V/7A) 4 PGOOD PGOOD TON R1 100k 9 5V C1 1u 2 C2 1u 15 2 14 PVCC VCC ENSW /MODE NX2138 R2 10 16 C3 1n HDRV 12 R8 2.2 BST 13 SW 11 VIN 7V~22V CI1 2x10uF M1 IRF7807 C4 1u Lo 1.5uH M2 LDRV 8 OCSET 10 1 VOUT NC R4 1MEG AO4714 R5 5k FB 3 NC AGND 6 PGND 7 Vout 1.8V/7A CO1 2R5TPE330MC 330uF R3 2.2 C5 1.5n R6 10.5k R7 7.5k Figure 3 - Demo board schematic Rev. 1.7 06/13/12 7 NX2138 Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Rev. 1.7 06/13/12 Quantity 2 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 Reference CI1 CO1 C1,C2,C4 C3 C5 Lo M1 M2 R1 R2 R3,R8 R4 R5 R6 R7 U1 Value 10uF/X5R/25V 2R5TPE330MC 1uF 1nF 1.5nF DO5010H-152 IRF7807 AO4714 100k 10 2.2 1M 5k 10.5k 7.5k NX2138 Manufacture SANYO COILCRAFT IR IR NEXSEM INC. 8 NX2138 Demoboard waveforms Fig.4 Startup (CH2 1.8V OUTPU T, CH3 PGOOD) Fig.5 Turn off (CH2 1.8V OUTPU T, CH3 PGOOD) Fig.7 Output transient in PFM mode (CH1 SW, CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig.8 Start into short (CH3 VOU T, CH4 OUTPUT CURRENT) Fig. 9 Output ripple at full load (CH1 SW, CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig. 10 Output ripple at light load in PFM mode(CH1 SW, CH2 1.8V OUTPUT AC) Rev. 1.7 06/13/12 9 NX2138 Demoboard waveforms(Cont') Fig. 11 Output ripple at no load in synchronous mode (CH1 SW, CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig. 13 Dynamic response in synchronous mode (CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig. 12 Dynamic response in synchronous mode (CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig. 14 Dynamic response in PFM mode (CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) VIN=12V, VOUT=1.8V 95.00% OUTPUT EFFICIENCY(%) 90.00% 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% 55.00% 50.00% 10 100 1000 10000 OUTPUTCURRENT(mA) Fig. 15 Dynamic response in PFM mode (CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Rev. 1.7 06/13/12 Fig. 16 Output efficiency 10 NX2138 APPLICATION INFORMATION FS is around 220kHz. VIN - Input voltage Output Inductor Selection VOUT - Output voltage IOUT - Output current Symbol Used In Application Information: The value of inductor is decided by inductor ripple current and working frequenc y. Larger inductor value normally means smaller ripple current. However if the DVRIPPLE - Output voltage ripple FS inductance is chosen too large, it brings slow response - Working frequency and lower efficiency. The ripple current is a design free- DIRIPPLE - Inductor current ripple dom which can be decided by design engineer according to various application requirements. The inductor Design Example value can be calculated by using the following equa- The following is typical application for NX2138, tions: the schematic is figure 1. VIN = 7 to 22V LOUT = VOUT=1.8V IRIPPLE ...(3) IRIPPLE =k × IOUTPUT FS=220kHz IOUT=7A where k is percentage of output current. In this example, inductor from COILCRAFT DO5010H-152 with L=1.5uH is chosen. DVRIPPLE <=60mV DVDROOP<=60mV @ 3A step Current Ripple is recalculated as below: On_Time and Frequency Calculation The constant on time control technique used in IRIPPLE = NX2138 delivers high efficiency, excellent transient dy- (22V-1.8V) × 372nS 1.5uH =5A notebook applications. An internal one shot timer turns on the high side driver with an on time which is proportional to the input supply VIN as well inversely proportional to the output VOUT. During this time, the output inductor charges the output cap increasing the output voltage by the amount equal to the output ripple. Once the timer turns off, the Hdrv turns off and cause the output voltage to decrease until reaching the internal FB voltage of 0.75V on the PFM comparator. At this point the comparator trips causing the cycle to repeat itself. A minimum off time of 400nS is internally set. (VIN -VOUT ON )×T L OUT = namic response, make it a good candidate for step down voltage ( VIN -VOUT ON) × T ...(4) Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both conditions. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(5). ∆IRIPPLE 8 × FS × COUT The equation setting the On Time is as follows: ∆VRIPPLE = ESR × ∆IRIPPLE + 4.45 × 10 −12 × R TON × VOUT TON = VIN − 0.5V ...(1) Where ESR is the output capacitors' equivalent VOUT FS = VIN × TON ...(2) series resistance,C OUT is the value of output capaci- In this application example, the RTON is chosen to be 1Mohm , when VIN=22V, the TON is 372nS and Rev. 1.7 06/13/12 ...(5) tors. Typically POSCAP is recommended to use in NX2139's applications. The amount of the output voltage ripple is dominated by the first term in equation(5) 11 NX2138 and the second term can be neglected. For this example, one POSCAP 2R5TPE330MC is chosen as output capacito r, the ESR and inductor current typically determines the output voltage ripple. When VIN reach maximum voltage, the output volt- ESR × COUT × VOUT ESR E × C E × VOUT = ...(10) ∆Istep ∆I step where ESRE and CE represents ESR and capaci- tance of each capacitor if multiple capacitors are used in parallel. age ripple is in the worst case. ∆V 60mV ESR desire = RIPPLE = = 12m Ω ∆IRIPPLE 5A L crit = The above equation shows that if the selected output inductor is smaller than the critical inductance, ...(6) the voltage droop or overshoot is only dependent on If low ESR is required, for most applications, mul- the ESR of output capacito r. For low frequency catiple capacitors in parallel are needed. The number of pacitor such as electrolytic capacito r, the product of output capacitor can be calculate as the following: E S R E × ∆ IR I P P L E ∆ VR IPPLE N = N= ESR and capacitance is high and L ≤ L crit is true. In that case, the transient spec is mostly like to depen- ...(7) dent on the ESR of capacito r. Most case, the output capacitor is multiple ca- 12m Ω × 5A 60m V pacitor in parallel. The number of capacitor can be calculated by the following N =1 The number of capacitor has to be round up to a integer. Choose N =1. N= ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(11) where Based On Transient Requirement 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP if L ≥ L crit ...(12) During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacito r, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a For example, assume voltage droop during transient is 60mV for 3A load step. If one POSCAP 2R5TPE330MC(330uF, 12mohm ESR) is used, the crticial inductance is given as ESRE ×CE × VOUT = ∆Istep DISTEP transient load, if assuming the bandwidth of sys- Lcrit = as the following equation. 12mΩ× 3300µF ×1.8V = 23.76µH 3A tem is high enough, the overshoot can be estimated ∆Vovershoot = ESR × ∆Istep + where VOUT × τ2 2 × L × COUT τ is the a function of capacito r,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT where ...(8) if L ≥ L crit ...(9 The selected inductor is 1.5uH which is smaller than critical inductance. In that case, the output voltage transient mainly dependent on the ESR. number of capacitor is N= ESR E × ∆Istep ∆Vtran 12mΩ × 3A 60mV = 0.6 = Choose N=1. Rev. 1.7 06/13/12 12 NX2138 Based On Stability Requirement ESR of the output capacitor can not be chosen and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall con- too low which will cause system unstable. The zero verter efficienc y. In this application, one IRF7807 for caused by output capacitor's ESR must satisfy the re- high side and one AO4714 with integrated schottky di- quirement as below: ode for low side are used. FESR = F 1 ≤ SW ...(13) 2 × π × ESR × COUT 4 Besides that, ESR has to be bigger enough so There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as: that the output voltage ripple can provide enough volt- PHCON =IOUT 2 × D × RDS(ON) × K age ramp to error amplifier through FB pin. If ESR is PLCON =IOUT 2 × (1 − D) × RDS(ON) × K too small, the error amplifier can not correctly dectect the ramp, high side MOSFET will be only turned off for minimum time 400nS. Double pulsing and bigger out- PTOTAL =PHCON + PLCON ...(15) where the R DS(ON) will increases as MOSFET junc- put ripple will be observed. In summar y, the ESR of tion temperature increases, K is RDS(ON) temperature the transient and DC ripple requirements. package rating or overall system thermal budget. Input Capacitor Selection conduction at the switching transition. The total output capacitor has to be big enough to make the sys- dependency. As a result, RDS(ON) should be selected for the worst case. Conduction loss should not exceed tem stable, but also has to be small enough to satify Input capacitors are usually a mix of high fre- Switching loss is mainly caused by crossover switching loss can be approximated. 1 × VIN × IOUT × TSW × FS ...(16) 2 ramic capacitors bypass the high frequency noise, and where I OUT is output current, T SW is the sum of T R bulk capacitors supply switching current to the and TF which can be found in mosfet datasheet, and MOSFETs. Usually 1uF ceramic capacitor is chosen FS is switching frequenc y. Swithing loss PSW is freto decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS cur- quency dependent. Also MOSFET gate driver loss should be considrent rating. The RMS current in the input capacitors ered when choosing the proper power MOSFE T. can be calculated as: MOSFET gate driver loss is the loss generated by disIRMS = IOUT × D × 1- D ...(14) charging the gate capacitor and is dissipated in driver D = TON × FS circuits.It is proportional to frequency and is defined When VIN = 22V, VOUT=1.8V, IOUT=7A, the result of as: input RMS current is 1.9A. Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(17) For higher efficiency, low ESR capacitors are where QHGATE is the high side MOSFE Ts gate recommended. One 10uF/X5R/25V and two 4.7uF/ charge,Q LGATE is the low side MOSFE Ts gate X5R/25V ceramic capacitors are chosen as input charge,VHGS is the high side gate source voltage, and capacitors. VLGS is the low side gate source voltage. This power dissipation should not exceed maxiPower MOSFETs Selection mum power dissipation of the driver device. The NX2138 requires at least two N-Channel power MOSFETs. The selection of MOSFETs is based Output Voltage Calculation on maximum drain source voltage, gate source voltOutput voltage is set by reference voltage and age, maximum current rating, MOSFET on resistance external voltage divider. The reference voltage is fixed quency ceramic capacitors and bulk capacitors. Ce- Rev. 1.7 06/13/12 PSW = 13 NX2138 at 0.75V. The divider consists of two ratioed resistors efficiency. so that the output voltage applied at the Fb pin is 0.75V when the output voltage is at the desired value. The following equation applies to figure11, which shows the relationship between age divide r. VOUT , VREF and volt- Vout R2 R1 In CCM mode, inductor current zero-crossing sensing is disabled, low side MOSFET keeps on even when inductor current becomes negative. In this way the efficiency is lower compared with PFM mode at light load, but frequency will be kept constant. Over Current Protection Over current protection for NX2138 is achieved by sensing current through the low side MOSFE T. An Fb typical internal current source of 24uA flows through an external resistor connected from OCSET pin to SW node sets the over current protection threshold. When Vref synchronous FET is on, the voltage at node S W is given as VSW =-IL × RDSON Figure 17 - Voltage Divider R 2 × VR E F R 1= V O U T R-V EF The voltage at pin OCSET is given as IOCP × ROCP +VSW ...(18) When the voltage is below zero, the over current occurs as shown in figure below. where R2 is part of the compensator, and the value vbus of R1 value can be set by voltage divide r. I OCP 24uA Mode Selection NX2138 can be operated in PFM mode, ultrasonic PFM mode, CCM mode and shutdown mode by applying different voltage on ENS W/MODE pin. When VCC applied to ENSW/MODE pin, NX2138 is In PFM mode. The low side MOSFET emulates the function of diode when discontinuous continuous mode happens, often in light load condition. During that time, the inductor current crosses the zero ampere border and becomes negative current. When the inductor current reaches negative territor y, the low side MOSFET OCP R OCP OCP comparator SW Figure 18 - Over Voltage Protection The over current limit can be set by the following equation. ISET = IOCP × ROCP /RDSON If the low side MOSFETRDSON=10mΩ at the OCP occuring moment, and the current limit is set at 12A, age to drop, the high side MOSFET waits longer to be then turned on. At the same time, no matter light load and I ×R 12A × 10m Ω is turned off and it takes longer time for the output volt- heavy load, the on time of high side MOSFET keeps the same. Therefore the lightier load, the lower the switching frequency will be. In ultrosonic PFM mode, the lowest frequency is set to be 25kHz to avoid audio frequency modulation. This kind of reduction of fre- R OCP = SET DSON IOCP = 24uA = 5k Ω Choose ROCP=5kΩ Power Good Output Power good output is open drain output, a pull quency keeps the system running at light light with high up resistor is needed. Typically when softstart is Rev. 1.7 06/13/12 14 NX2138 finised and FB pin voltage is over 90% of V REF, the PGOOD pin is pulled to high after a 1.6ms dela y. Smart Over Output Voltage Protection Active loads in some applications can leak cur- should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling rent from a higher voltage thanVOUT, cause output volt- ceramic cap which usually is 1uF age to rise. When the FB pin voltage is sensed over need to be practically touching the drain pin of the upper MOSFE T, a 112% of VREF, the high side MOSFET will be turned off plane connection is a must. and low side MOSFET will be turned on to discharge 3. The output capacitors should be placed as close the VOUT. NX2138 resumes its switching operation after as to the load as possible and plane connection is re- FB pin voltage drops to V REF. If FB pin voltage keeps rising and is sensed over 125% of VREF, the low side MOSFET will be latched to quired. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a be on to discharge the output voltage and over voltage plane and as close as possible. A snubber needs to be protection is triggered. To resume the switching opera- placed as close to this junction as possible. tion, resetting voltage on pin VCC or pin EN is necessary. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not Under Output Voltage Protection Typically when the FB pin voltage is under 70% of VREF, the high side and low side MOSFET will be enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be turned off. To resume the switching operation, VCC or wide and short. A place for gate drv resistors is needed ENSW has to be reset. to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other by- Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFE T, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching powe r. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input passing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divide r. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals, should be kept away from the inductor and other noise sources. The resistor divider must be located as close as possible to the FB pin of the device. 9. All GNDs need to go directly thru via to GND plane. 10. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. capacitor, inductor, output capacitor and the MOSFETs Rev. 1.7 06/13/12 15 NX2138 4x4 16 PIN MLPQ OUTLINE DIMENSIONS NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS. Rev. 1.7 06/13/12 16