NX2139A SINGLE CHANNEL MOBILE PWM AND LDO CONTROLLER PRODUCTION DATA SHEET Pb Free Product DESCRIPTION The NX2139A controller IC is a compact Buck control- n ler IC with 16 lead MLPQ package designed for step n down DC to DC converter in portable applications. It n n can be selected to operate in synchronous mode or non-synchronous mode to improve the efficiency at light n load.Constant on time control provides fast response, good line regulation and nearly constant frequency un- n der wide voltage input range. The NX2139 A controller is optimized to convert single supply up to 22V bus voltage to as low as 0.75V output voltage. Over cur- n n rent protection and FB UVLO followed by latch feature. A built-in LDO controller can drive an external N- n MOSFET to provide a second output voltage from ei- n ther PWM output source or other power source. Both n PWM controller and LDO controller have separate EN n feature. Other features includes: 5V gate drive capability, power good indicator, over voltage protection, n internal Boost schottky diode and adaptive dead band n n control. n FEATURES Internal Boost Schottky Diode Ultrasonic mode operation available Bus voltage operation from 4.5V to 22V Less than 1uA shutdown current with Enable low Excellent dynamic response with constant on time control Selectable between Synchronous CCM mode and diode emulation mode to improve efficiency at light load Programmable switching frequency Current limit and FB UVLO with latch off Over voltage protection with latch off LDO controller with seperate enable Two independent Power Good indicator available Pb-free and RoHS compliant APPLICATIONS Notebook PCs and Desknotes Tablet PCs/Slates On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Hand-held portable instruments TYPICAL APPLICATION 4 PGOOD PGOOD TON 1MEG 16 100k 9 5V 10 1u 2 2x10uF PVCC HDRV 12 2.2 BST 13 VCC 1u ENSW /MODE IRF7807 1u 1.5uH SW 11 NX2139 A 15 VIN 7V~22V 1n Vout 1.8V/7A 2R5TPE330MC 330uF LDRV 8 AO4714 OCSET 10 1 VOUT FB 5k 330p 3 10.5k 7.5k 14 LDODRV ENLDO 50 5V 100k LDOPG M3 SI4800 7 33n 5 LDOFB 6 LDOPG GND 1n 20k 7.5k 1.5V@2A 2x10uF 7.5k PAD Figure1 - Typical application of NX2139A ORDERING INFORMATION Device Temperature NX2139ACMTR -10 o C to 100 o C Rev. 2.4 06/13/12 Package 3X3 MLPQ-16L Pb-Free Yes 1 NX2139A ABSOLUTE MAXIMUM RATINGS VCC,PVCC to GND & BST to S W voltage ............ -0.3V to 6.5V TON to GND ......................................................... -0.3V to 28V HDRV to S W Voltage .......................................... -0.3V to 6.5V SW to GND ......................................................... -2V to 30V All other pins ........................................................ VCC+0.3V Storage Temperature Range .................................-65 oC to 150 oC Operating Junction Temperature Range .................-40 oC to 150 oC ESD Susceptibility ............................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM R ATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION TON ENSW/MODE ENLDO BST 3x3 16-LEAD PLASTIC MLPQ 16 15 14 13 θ JA ≈ 46o C/W 12 HDRV VO 1 VCC 2 FB 3 11 SW 17 AGND 10 OCSET 9 PVCC 6 7 LDOFB LDODRV 8 LDRV 5 LDOPG PGOOD 4 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =5 V, VIN=15V and T A =25oC, unless otherwise specified. PARAMETER VIN recommended voltage range Shut down current VCC,PVCC Supply Input voltage range Operating quiescent current Shut down current Rev. 2.4 06/13/12 SYM Test Condition VIN Min 4.5 ENLDO=GND, ENSW=GND VCC TYP VFB=0.85V, ENLDO=GND, ENSW=5V ENLDO=GND, ENSW=GND MAX Units 22 V 1 4.5 5.5 1.8 1 uA V mA uA 2 NX2139A PARAMETER VCC UVLO Under-voltage Lockout threshold Falling VCC threshold ON and OFF time SYM VCC_UVLO TON operating current ON -time Minimum off time FB voltage Internal FB voltage Input bias current Line regulation Test Condition VIN=15V, Rton=1Mohm VIN=9V,VOUT=0.75V, Rton=1Mohm Vref VCC from 4.5V to 5.5V OUTPUT voltage Output range VOUT shut down discharge resistance ENSW/MODE=GND Soft start time PGOOD Pgood high rising threshold PGOOD delay after softstart PGOOD propagation delay filter Power good hysteresis Pgood output switch impedance Pgood leakage current SW zero cross comparator Offset voltage HighNSide Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time Rev. 2.4 06/13/12 NOTE1 NOTE1 Min TYP MAX Units 3.9 3.7 4.1 3.9 4.5 4.3 V V 15 uA 312 380 390 590 468 800 ns ns 0.739 0.75 -1 0.761 100 1 V nA % 0.75 3.3 V 30 ohm 1.5 ms 90 1.6 % Vref ms 2 5 us % 13 ohm 1 uA 5 mV R source(Hdrv) I=200mA 1.5 ohm Rsink(Hdrv) I=200mA 1.5 ohm THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% 50 50 30 ns ns ns R source(Ldrv) I=200mA 1.5 ohm Rsink(Ldrv) I=200mA 0.5 ohm 50 50 10 ns ns ns TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 3 NX2139A PARAMETER ENSW/MODE threshold and bias current SYM Test Condition PFM/Non Synchronous Mode Ultrasonic Mode Synchronous Mode Shutdown mode Input bias current LDO Controller Quiescent current Leave it open or use limits in spec LDOFB input bias current LDODrv sourcing current LDODrv sinking current LDO PGOOD threshold LDO PGOOD propagation delay filter LDO PGOOD impedance Current Limit Ocset setting current Over temperature Threshold Hysteresis Under voltage FB threshold Over voltage Over voltage tripp point Internal Schottky Diode Forward voltage drop TYP 80% VCC 60% VCC MAX VCC+0 .3V 80% VCC 60% VCC 0.8 2 0 Units V V ENSW/MODE=VCC 5 V V uA ENSW/MODE=GND -5 uA PWM OFF, LDOEN=HI, IOUT=0mA 1 mA LDOEN logic high voltage LDOEN logic low voltage LDOFB reference voltage Output UVLO threshold Open loop gain Min 2 0.728 0.75 0.8 0.773 70 60 NOTE1 %Vref DB 1 LDOFB=0.72V LDOFB=0.78V NOTE1 20 NOTE1 Forward current=50mA V V V 2 2 uA mA mA 90 %Vref 2 13 us ohm 24 28 uA 155 o 15 o C C 70 %Vref 125 %Vref 500 mV NOTE1: This parameter is guaranteed by design but not tested in production(GBNT). Rev. 2.4 06/13/12 4 NX2139A PIN DESCRIPTIONS PIN NUMBER PIN SYMBOL PIN DESCRIPTION This pin is directly connected to the output of the switching regulator and senses the VOUT voltage. An internal MOSFET discharges the output during turn off. 1 VOUT 2 VCC 3 FB 4 PGOOD PGOOD indicator for switching regulato r. It requires a pull up resistor to Vcc or lower voltage. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. 5 LDOPG PGOOD indicator for LDO, requires a pull up resistor to Vcc or lower voltage. When LDOFB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. 6 LDOFB This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the LDO to set the output DC voltage. 7 LDODRV 8 LDRV Low side gate driver output. 9 PVCC Provide the voltage supply to the lower MOSFET drivers. Place a high frequency decoupling capacitor 1uF X5R to this pin. 10 OCSET 11 SW 12 HDRV 13 BST 14 ENLDO LDO enable input functions only when ENS W/MODE is not shutdown. 15 ENSW/ MODE Switching converter enable input. Connect to VCC for PFM/Non synchronous mode, connected to an external resistor divider equals to 70%VCC for ultrasonic, connected to GND for shutdown mode, floating or connected to 2V for the synchronous mode. 16 TON VIN sensing input. A resistor connects from this pin to VIN will set the frequency. A 1nF capacitor from this pin to GND is recommended to ensure the proper operation. PAD GND Power ground. Rev. 2.4 06/13/12 This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is placed as close as possible to this pin and ground pin. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage from 0.75V to 3.3 V. The drive signal for external LDO N channel MOSFE T. This pin is connected to the drain of the external low side MOSFET and is the input of over current protection(OCP) comparato r. An internal current source is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFE T. This pin is connected to source of high side FE Ts and provide return path for the high side driver. It is also the input of zero current sensing comparato r. High side gate driver output. This pin supplies voltage to high side FET drive r. A high freq 1uF X7R ceramic capacitor and 2.2ohm resistor in series are recommended to be placed as close as possible to and connected to this pin and S W pin. 5 NX2139A BLOCK DIAGRAM VCC(2) Bias TON(16) VIN 4.3/4.1 ON time pulse genearation VOUT Disable_B Thermal shutdown POR start R S VIN ODB HD VOUT BST(13) HDRV(12) FET Driver HD_IN Q SW(11) 1.8V 5V PVCC(9) FB(3) LDRV(8) Mini offtime 400ns OCP_COMP PGND VREF=0.75V start POR FBUVLO_latch soft start Diode emulation HD VCC ENSW /MODE(15) 1M 1M Disable PFM_nonultrasonic MODE SELECTION Sync OCSET(10) FB 1.25*Vref/0.7VREF OCP_COMP OVP GND(17 PAD) FB FBUVLO_latch PGOOD(4) 0.7*Vref SS_finished VOUT(1) VOUT start 0.9*Vref LDOFBUVLO_latch LDOPG(5) 1.5V@2A~5A 0.7*Vref LDOSS_finished 0.9*Vref LDO_POR LDOFBUVLO_latch ENLDO(14) LDO_EN soft start LDODRV(7) LDOFB(6) Figure 2 - Simplified block diagram of the NX2139A Rev. 2.4 06/13/12 6 NX2139A TYPICAL APPLICATION (VIN=7V to 22V, SW VOUT=1.8V/7A, LDO VOUT=1.5V/2A) 4 PGOOD PGOOD TON R1 100k 9 5V R2 10 C1 1u 2 C2 1u PVCC C3 1n VIN 7V~22V HDRV 12 R13 2.2 BST 13 C4 1u SW 11 VCC NX2139A ENSW 15 /MODE R4 1MEG 16 M1 IRF7807 Lo 1.5uH M2 LDRV 8 LDOPG R3 100k LDODRV ENLDO 7 5V LDOFB 6 5 LDOPG GND AO4714 R5 5k OCSET 10 1 VOUT C8 330p FB 3 14 CI1 2x10uF CO1 2R5TPE330MC 330uF R12 2.2 C7 1.5n R6 10.5k R7 7.5k R8 50 C6 33n C5 1n R9 20k Vout 1.8V/7A M3 SI4800 1.5V@2A R10 7.5k CO2 2x10uF R11 7.5k PAD Figure 3 - Demo board schematic Rev. 2.4 06/13/12 7 NX2139A Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Rev. 2.4 06/13/12 Quantity 2 2 1 3 2 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 2 1 Reference CI1 CO2 CO1 C1,C2,C4 C3,C5 C6 C7 C8 Lo M1 M2 M3 R1,R3 R2 R4 R5 R6 R7,R10,R11 R8 R9 R12,R13 U1 Value 10uF/25V/X5R 10uF/6.3V/X5R 2R5TPE330MC 1uF 1nF 33nF 1.5nF 330pF DO5010H-152 IRF7807 AO4714 SI4800 100k 10 1M 5k 10.5k 7.5k 50 20k 2.2 NX2139A Manufacture SANYO COILCRAFT IR AOS PHILIPS NEXSEM INC. 8 NX2139A Demoboard Waveforms Fig.4 Startup (CH1 1.8V OUTPUT, CH2 1.5V LDO, CH3 SW PGOOD, CH4 LDO PGOOD) Fig.5 Turn off (CH1 1.8V OUTPU T, CH2 1.5V LDO, CH3 SW PGOOD, CH4 LDO PGOOD) Fig.6 LDO output transient with S W in PFM mode (CH1 1.8V OUTPUT AC, CH2 1.5V LDO AC, CH4 LDO OUTPUT CURRENT) Fig.7 SW output transient (CH1 1.8V OUTPUT AC, CH2 1.5V LDO AC, CH4 1.8V OUTPUT CURRENT) Fig.8 Start into short (CH1 VIN, CH2 5V VCC, CH4 INDUCTOR CURRENT) Rev. 2.4 06/13/12 Fig. 9 VOUT ripple @ VIN=12 V,IOUT=4A (CH1 SW, CH3 VOUT AC) 9 NX2139A VIN=12V, VOUT=1.8V OUTPUT EFFICIENCY(%) 100.00% 90.00% 80.00% 70.00% 60.00% 50.00% 10 100 1000 10000 OUTPUT CURRENT(mA) Fig. 10 Output efficiency Rev. 2.4 06/13/12 10 NX2139A APPLICATION INFORMATION FS is around 220kHz. VIN - Input voltage Output Inductor Selection VOUT - Output voltage IOUT - Output current Symbol Used In Application Information: The value of inductor is decided by inductor ripple current and working frequenc y. Larger inductor value normally means smaller ripple current. However if the DVRIPPLE - Output voltage ripple FS inductance is chosen too large, it brings slow response - Working frequency and lower efficiency. The ripple current is a design free- DIRIPPLE - Inductor current ripple dom which can be decided by design engineer according to various application requirements. The inductor Design Example value can be calculated by using the following equa- The following is typical application for NX2139A, tions: the schematic is figure 1. VIN = 7 to 22V LOUT = VOUT=1.8V IRIPPLE ...(3) IRIPPLE =k × IOUTPUT FS=220kHz IOUT=7A where k is percentage of output current. In this example, inductor from COILCRAFT DO5010H-152 with L=1.5uH is chosen. DVRIPPLE <=60mV DVDROOP<=60mV @ 3A step Current Ripple is recalculated as below: On_Time and Frequency Calculation The constant on time control technique used in IRIPPLE = NX2139A delivers high efficienc y, excellent transient (22V-1.8V) × 372nS 1.5uH =5A down notebook applications. An internal one shot timer turns on the high side driver with an on time which is proportional to the input supply VIN as well inversely proportional to the output VOUT. During this time, the output inductor charges the output cap increasing the output voltage by the amount equal to the output ripple. Once the timer turns off, the Hdrv turns off and cause the output voltage to decrease until reaching the internal FB voltage of 0.75V on the PFM comparator. At this point the comparator trips causing the cycle to repeat itself. A minimum off time of 400nS is internally set. (VIN -VOUT ON )×T L OUT = dynamic response, make it a good candidate for step voltage ( VIN -VOUT ON) × T ...(4) Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both conditions. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(5). ∆IRIPPLE 8 × FS × COUT The equation setting the On Time is as follows: ∆VRIPPLE = ESR × ∆IRIPPLE + 4.45 × 10 −12 × R TON × VOUT TON = VIN − 0.5V ...(1) Where ESR is the output capacitors' equivalent VOUT FS = VIN × TON ...(2) series resistance,C OUT is the value of output capaci- In this application example, the RTON is chosen to be 1Mohm , when VIN=22V, the TON is 372nS and Rev. 2.4 06/13/12 ...(5) tors. Typically POSCAP is recommended to use in NX2139's applications. The amount of the output voltage ripple is dominated by the first term in equation(5) 11 NX2139A and the second term can be neglected. For this example, one POSCAP 2R5TPE330MC is chosen as output capacito r, the ESR and inductor current typically determines the output voltage ripple. When VIN reach maximum voltage, the output volt- ESR × COUT × VOUT ESR E × C E × VOUT = ...(10) ∆Istep ∆I step where ESRE and CE represents ESR and capaci- tance of each capacitor if multiple capacitors are used in parallel. age ripple is in the worst case. ∆V 60mV ESR desire = RIPPLE = = 12m Ω ∆IRIPPLE 5A L crit = The above equation shows that if the selected output inductor is smaller than the critical inductance, ...(6) the voltage droop or overshoot is only dependent on If low ESR is required, for most applications, mul- the ESR of output capacito r. For low frequency catiple capacitors in parallel are needed. The number of pacitor such as electrolytic capacito r, the product of output capacitor can be calculate as the following: E S R E × ∆ IR I P P L E ∆ VR IPPLE N = N= ESR and capacitance is high and L ≤ L crit is true. In that case, the transient spec is mostly like to depen- ...(7) dent on the ESR of capacito r. Most case, the output capacitor is multiple ca- 12m Ω × 5A 60m V pacitor in parallel. The number of capacitor can be calculated by the following N =1 The number of capacitor has to be round up to a integer. Choose N =1. N= ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(11) where Based On Transient Requirement 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP if L ≥ L crit ...(12) During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacito r, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a For example, assume voltage droop during transient is 60mV for 3A load step. If one POSCAP 2R5TPE330MC(330uF, 12mohm ESR) is used, the crticial inductance is given as ESRE ×CE × VOUT = ∆Istep DISTEP transient load, if assuming the bandwidth of sys- Lcrit = as the following equation. 12mΩ× 3300µF ×1.8V = 23.76µH 3A tem is high enough, the overshoot can be estimated ∆Vovershoot = ESR × ∆Istep + where VOUT × τ2 2 × L × COUT τ is the a function of capacito r,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT where ...(8) if L ≥ L crit ...(9 The selected inductor is 1.5uH which is smaller than critical inductance. In that case, the output voltage transient mainly dependent on the ESR. number of capacitor is N= ESR E × ∆Istep ∆Vtran 12mΩ × 3A 60mV = 0.6 = Choose N=1. Rev. 2.4 06/13/12 12 NX2139A Based On Stability Requirement ESR of the output capacitor can not be chosen and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall con- too low which will cause system unstable. The zero verter efficienc y. In this application, one IRF7807 for caused by output capacitor's ESR must satisfy the re- high side and one AO4714 with integrated schottky di- quirement as below: ode for low side are used. FESR = F 1 ≤ SW ...(13) 2 × π × ESR × COUT 4 Besides that, ESR has to be bigger enough so There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as: that the output voltage ripple can provide enough volt- PHCON =IOUT 2 × D × RDS(ON) × K age ramp to error amplifier through FB pin. If ESR is PLCON =IOUT 2 × (1 − D) × RDS(ON) × K too small, the error amplifier can not correctly dectect the ramp, high side MOSFET will be only turned off for minimum time 400nS. Double pulsing and bigger out- PTOTAL =PHCON + PLCON ...(15) where the R DS(ON) will increases as MOSFET junc- put ripple will be observed. In summar y, the ESR of tion temperature increases, K is RDS(ON) temperature the transient and DC ripple requirements. package rating or overall system thermal budget. Input Capacitor Selection conduction at the switching transition. The total output capacitor has to be big enough to make the sys- dependency. As a result, RDS(ON) should be selected for the worst case. Conduction loss should not exceed tem stable, but also has to be small enough to satify Input capacitors are usually a mix of high fre- Switching loss is mainly caused by crossover switching loss can be approximated. 1 × VIN × IOUT × TSW × FS ...(16) 2 ramic capacitors bypass the high frequency noise, and where I OUT is output current, T SW is the sum of T R bulk capacitors supply switching current to the and TF which can be found in mosfet datasheet, and MOSFETs. Usually 1uF ceramic capacitor is chosen FS is switching frequenc y. Swithing loss PSW is freto decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS cur- quency dependent. Also MOSFET gate driver loss should be considrent rating. The RMS current in the input capacitors ered when choosing the proper power MOSFE T. can be calculated as: MOSFET gate driver loss is the loss generated by disIRMS = IOUT × D × 1- D ...(14) charging the gate capacitor and is dissipated in driver D = TON × FS circuits.It is proportional to frequency and is defined When VIN = 22V, VOUT=1.8V, IOUT=7A, the result of as: input RMS current is 1.9A. Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(17) For higher efficiency, low ESR capacitors are where QHGATE is the high side MOSFE Ts gate recommended. One 10uF/X5R/25V and two 4.7uF/ charge,Q LGATE is the low side MOSFE Ts gate X5R/25V ceramic capacitors are chosen as input charge,VHGS is the high side gate source voltage, and capacitors. VLGS is the low side gate source voltage. This power dissipation should not exceed maxiPower MOSFETs Selection mum power dissipation of the driver device. The NX2139A requires at least two N-Channel power MOSFETs. The selection of MOSFETs is based Output Voltage Calculation on maximum drain source voltage, gate source voltOutput voltage is set by reference voltage and age, maximum current rating, MOSFET on resistance external voltage divider. The reference voltage is fixed quency ceramic capacitors and bulk capacitors. Ce- Rev. 2.4 06/13/12 PSW = 13 NX2139A at 0.75V. The divider consists of two ratioed resistors tion of frequency keeps the system running at light light so that the output voltage applied at the Fb pin is 0.75V with high efficienc y. In CCM mode, inductor current zero-crossing when the output voltage is at the desired value. The following equation applies to figure11, which shows the relationship between age divide r. VOUT , VREF and volt- R1 when inductor current becomes negative. In this way the efficiency is lower compared with PFM mode at light load, but frequency will be kept constant. Vout R2 sensing is disabled, low side MOSFET keeps on even Over Current Protection Over current protection for NX2139A is achieved Fb by sensing current through the low side MOSFE T. An typical internal current source of 24uA flows through an external resistor connected from OCSET pin to SW Vref node sets the over current protection threshold. When synchronous FET is on, the voltage at node S W is given as Figure 11 - Voltage Divider VSW =-IL × RDSON The voltage at pin OCSET is given as R 1= R 2 × VR E F V O U T R-V EF ...(18) IOCP × ROCP +VSW When the voltage is below zero, the over current where R2 is part of the compensator, and the value occurs as shown in figure below. of R1 value can be set by voltage divide r. vbus Mode Selection I OCP 24uA NX2139A can be operated in PFM mode, ultrasonic PFM mode, CCM mode and shutdown mode by applying different voltage on ENS W/MODE pin. When VCC applied to ENS W /MODE pin, OCP R OCP OCP comparator SW NX2139A is In PFM mode. The low side MOSFET emulates the function of diode when discontinuous continuous mode happens, often in light load condition. During that time, the inductor current crosses the zero ampere border and becomes negative current. When the inductor current reaches negative territory, the low side MOSFET is turned off and it takes longer time for Figure 12 - Over Voltage Protection The over current limit can be set by the following equation. ISET = IOCP × ROCP /RDSON If the low side MOSFETRDSON=10mΩ at the OCP the output voltage to drop, the high side MOSFET waits occuring moment, and the current limit is set at 12A, longer to be turned on. At the same time, no matter then light load and heavy load, the on time of high side ISET × RDSON 12A × 10m Ω MOSFET keeps the same. Therefore the lightier load, the lower the switching frequency will be. In ultrosonic PFM mode, the lowest frequency is set to be 25kHz to R OCP = IOCP = 24uA = 5k Ω Choose ROCP=5kΩ avoid audio frequency modulation. This kind of reduc- Rev. 2.4 06/13/12 14 NX2139A Power Good Output Power good output is open drain output, a pull up resistor is needed. Typically when softstart is finised and FB pin voltage is over 90% of V REF, the PGOOD pin is pulled to high after a 1.6ms dela y. Smart Over Output Voltage Protection Active loads in some applications can leak current from a higher voltage thanVOUT, cause output volt- PLOSS = (VLDOIN − VLDOOUT ) × I LOAD = (1.8V − 1.5V) × 2A = 0.6W Select MOSFET SI4800 with 33m Ω RDSON is sufficient. LDO Compensation The diagram of LDO controller including VCC regulator is shown in the following figure. age to rise. When the FB pin voltage is sensed over LDO input and low side MOSFET will be turned on to discharge the VOUT. NX2139A resumes its switching operation after FB pin voltage drops to V REF. + 112% of VREF, the high side MOSFET will be turned off Vref Rf1 LDODRV LDOFB Rb Rf2 If FB pin voltage keeps rising and is sensed over Cb Rc Cc 125% of VREF, the low side MOSFET will be latched to ESR Rload Co be on to discharge the output voltage and over voltage protection is triggered. To resume the switching operation, resetting voltage on pin VCC or pin EN is necessary. Under Output Voltage Protection Typically when the FB pin voltage is under 70% of VREF, the high side and low side MOSFET will be turned off. To resume the switching operation, VCC or ENSW has to be reset. LDO Selection Guide NX2139A offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. The MOSFET has to be logic level MOSFET and its Rdson at 4.5V should meet the dropout requirement. For example. VLDOIN =1.8V VLDOOUT =1.5V ILoad =2A The maximum Rdson of MOSFET should be R RDSON = (VLDOIN − VLDOOUT ) × I LOAD = (1.8V − 1.5V) / 2A = 0.15Ω Most of MOSFE Ts can meet the requirement. More important is that MOSFET has to be selected right package to handle the thermal capability. For LDO, maximum power dissipation is given as Rev. 2.4 06/13/12 Figure 13 - NX2139 A LDO controller. Rb and Cb have fixed value which is used to compensate the comparater of the LDO controller. Set Rb=50ohm, Cb=33nF. For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows. CC = g × ESR 1 × m 2 × π × FO × R f1 1+gm × ESR where FO is the desired crossover frequenc y. Typically, when the POSCAP and electrical ca- pacitor is chosen as output capacito r, crossover frequency FO has to be 2 to 3 times higher than zero caused by ESR. In this example, we select Fo=150kHz. gm is the forward trans-conductance of MOSFET. For SI4800, g m=19. Select Rf1= 7.5kohm. Output capacitor is Sanyo POSCAP 4TPE150MI with 150uF, ESR=18mohm. 1 19S × 18m Ω CC = × =36pF 2 × π × 150kHz × 7.5kΩ 1+19S × 18m Ω Typically CC is chosen to be 1 to 1.5 times smaller than calculated value to compensate parasitic effect. 15 NX2139A Here CC is chosen to be 33p F. For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage. Rf1 × VREF Rf2 = VLDOOUT − VREF 70% of VREF, the IC goes into latch mode. The IC will turn off all the channel until VCC or ENS W resets. Power Good for LDO Power good output is open drain output, a pull up resistor is needed. Typically when softstart is 7.5kΩ × 0.75V 1.5V − 0.75V =7.5kΩ = finised and LDOFB pin voltage is over 90% of V REF, the LDOPGOOD pin is pulled to high. Choose Rf2=7.5kΩ. When ceramic capacitors or some low ESR bulk capacitors are chosen as LDO output capacitors, the zero caused by output capacitor ESR is so high that crossover frequency FO has to be chosen much higher Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with than zero caused by RC and CC and much lower than less than expected results. used as output capacito r. We select Fo= 300kHz, the layout which are power components and small sig- zero caused by ESR . For example, 10uF ceramic is Rf1=7.5kohm and select MOSFET SI4800(gm=19). RC and CC can be calculated as follows. 2 × π × FO × CO RC =Rf1 × × gm VOUT IOUT V gm × OUT IOUT 1+gm × 1.5V 1+19S × 2 × π × 300kHz × 20uF 2A =7.5kΩ × × 1.5V 19S 19S × 2A =14.9kΩ Typically RC is chosen to be 1 to 1.5 times smaller There are two sets of components considered in nal components. Power components usually consist of input capacitors, high-side MOSFE T, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching powe r. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps than calculated value to compensate parasitic effect. to reduce the EMI radiated by the power loop due to Choose RC=20kΩ. the high switching currents through them. CC = 10 × CO R C × gm 10 × 20uF = 20kΩ × 19S =0.53nF Choose CC=1000pF. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practi- cally touching the drain pin of the upper MOSFE T, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. Current Limit for LDO Current limit of LDO is achieved by sensing the LDO feedback voltage. When LDO_FB pin is below Rev. 2.4 06/13/12 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane and as close as possible. A snubber needs to be placed as close to this junction as possible. 16 NX2139A 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divide r. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals, should be kept away from the inductor and other noise sources. The resistor divider must be located as close as possible to the FB pin of the device. 9. All GNDs need to go directly thru via to GND plane. 10. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. Rev. 2.4 06/13/12 17 NX2139A Demoboard Schematic BUS 1 CIN3 BUS 4.7u/25V R7 1M 5 100k 5V 9 BST PGOOD VCCP 14 LIN_EN LDOIN C7 10u C3 10u R19 7.5k R18 50 C19 33n 7 OCP DL VOUT R17 20k 11 1 Lo VOUT OUT CO1 2R5TPE330MC 10k 8 2 DO5010H-152 R3 10 4 CO2 4.7u/6.3V R15 2.2 M2 AO4714 C9 1.5n GND 1 C15 330p C18 1n 6 R20 7.5k SW LIN_DRV LIN_FB GND LDOOUT LDODRV 17 LDOOUT 4 3 2 1 M3 SI4800 M1 IRF7807 8 7 6 5 EN 5 6 7 8 LDOIN 4 0 1 2 3 15 R2 12 10u/25V VCC C2 1u N X 2 1 3 9 /M L P Q -1 6 /3 x 3 2 CIN1 C17 1u DH VCC 10 4.7u/25V 2.2 LIN_PGOOD C16 1u R6 R4 8 7 6 5 4 100k R8 1 CIN2 13 1 2 3 R11 5V 1n TON U1 16 C6 FB R5 10.5k 3 R10 7.5k Figure 14 - NX2139A schematic for the demoboard layout Rev. 2.4 06/13/12 18 NX2139A Demoboard Layout Figure 15 Top layer Figure 16 Ground layer Rev. 2.4 06/13/12 19 NX2139A Figure 17 Power layer Figure 18 Bottom layer Rev. 2.4 06/13/12 20 NX2139A MLPQ 16 PIN 3 x 3 PACKAGE OUTLINE DIMENSIONS SYMBOL NAME A A1 A3 B D D2 E E2 e L M Rev. 2.4 06/13/12 Dimensions In Millimeters MIN 0.700 0.000 0.180 2.950 1.600 2.950 1.600 0.325 0.203REF 0.50BSC 1.5REF Dimensions In Inches MAX 0.800 0.050 MIN 0.028 0.000 0.300 3.050 1.750 3.050 1.750 0.007 0.116 0.063 0.116 0.063 0.450 0.013 0.008REF 0.50BSC 0.059REF MAX 0.031 0.002 0.012 0.120 0.069 0.120 0.069 0.018 21