REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. Update boilerplate to current revision. - CFS 06-08-07 Thomas M. Hess B Make changes to IO(src), tDELAY, and ISU tests as specified under Table I. - ro 10-09-28 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY TOM HESS 05-08-30 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 TITLE SIZE CODE IDENT. NO. A REV AMSC N/A MICROCIRCUIT, DIGITAL-LINEAR, HIGH SPEED, PULSE WIDTH MODULATOR CONTROLLER, MONOLITHIC SILICON APPROVED BY RAYMOND MONNIN DWG NO. V62/05616 16236 B PAGE 1 OF 13 5962-V077-10 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance high speed, pulse width modulator (PWM) controller microcircuit, with an operating temperature range of -40C to +125C for device type 01, and -55 to +125C for device type 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05616 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UC2825A-EP High speed, PWM controller 02 UC2825A-EP High speed, PWM controller 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 16 JEDEC PUB 95 Package style MS-013 AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage range (VIN) ( VC and VCC pins ) ........................................................ 22 V Source or sink current, dc (IO) ( OUTA and OUTB pins ) ......................................... 0.5 A Source or sink current, pulse 0.5 s (IO) ( OUTA and OUTB pins ) .......................... 2.2 A Analog inputs: INV, NI, and RAMP pins ......................................................................................... -0.3 V to 7 V ILIM, and SS pins ................................................................................................... -0.3 V to 6 V Power ground ( PGND pin ) ...................................................................................... 0.2 V Clock output current ( ICLK ) ( CLK/LEB pins ) .......................................................... -5 mA Error amplifier output current ( IO(EA) ) ( EAOUT pin ) ............................................... 5 mA Soft start sink current ( ISS ) ( SS pin ) ...................................................................... 20 mA Oscillator charging current ( IOSC ) ( RT pin ) ............................................................ -5 mA Operating virtual junction temperature range ( TJ ) .................................................... -55C to +150C Storage temperature ( Tstg ) ...................................................................................... Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ............................... Storage temperature ( TSTG ) .................................................................................... Lead temperature 1.6 mm (1/16 inch) from cases for 10 seconds ............................. -65C to +150C -55C to +150C -65C to +150C +300C 1.4 Recommended operating conditions. 2/ Supply voltage range (VIN) ........................................................................................ 12 V Operating free-air temperature range (TA): Device type 01 ........................................................................................................ -40C to +125C Device type 02 ........................................................................................................ -55C to +125C 1/ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 2/ 1/ Temperature, TA Device type Limits Unit Min Max 5.05 5.15 V Reference, VREF section Output voltage range VO IO = 1 mA, TJ = 25C Line regulation LN Load regulation LD 25C All 12 V VCC 20 V 3/ All 15 mV 1 mA IO 10 mA 3/ All 20 mV Total output variation Line, load, temperature 3/ All 5.17 V Temperature stability 4/ T(min) TA T(max) 3/ All 0.4 mV/C Output noise voltage 4/ 10 Hz f 10 kHz 3/ All 125C All 3/ All 25C All Long term stability Short circuit current 4/ 1000 hours, TJ = 125C IOS VREF = 0 V fOSC TJ = 25C 5.03 50 typical VRMS 25 mV 30 90 mA 375 425 kHz 0.9 1.1 MHz 350 450 kHz 0.85 1.15 MHz Oscillator section Initial accuracy 4/ RT = 6.6 k, CT = 220 pF, TA = 25C Total variation 4/ Line, temperature 3/ All RT = 6.6 k, CT = 220 pF Voltage stability 12 V VCC 20 V 3/ All Temperature stability T(min) TA T(max) 3/ All High level output voltage, clock 3/ All Low level output voltage, clock 3/ All 4/ 1% 5% typical 3.7 V 0.2 V Ramp peak VRP 3/ All 2.6 3 V Ramp valley VRV 3/ All 0.7 1.25 V See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 2/ Temperature, TA 1/ Device type Limits Unit Min Max Oscillator section - continued. Ramp valley-to-peak Oscillator discharge current IOSC RT = open, VCT = 2 V 3/ All 1.6 2 V 3/ All 9 11 mA Error Amplifier section Input offset voltage VIO 3/ All 10 mV Input bias current IIB 3/ All 3 A Input offset current IIO 3/ All 1 A 1 V VO 4 V 3/ All 60 dB Open loop gain Common mode rejection ratio CMRR 1.5 V VCM 5.5 V 3/ All 75 dB Power supply rejection ratio PSRR 12 V VCC 20 V 3/ All 85 dB Output sink current IO(sink) VEAOUT = 1 V 3/ All 1 mA Output source current IO(src) VEAOUT = 4 V 3/ All High level output voltage VOH IEAOUT = -0.5 mA 3/ All Low level output voltage VOL IEAOUT = -1 mA 3/ f = 200 kHz -0.5 mA 4.5 5 V All 0 1 V 3/ All 6 MHz 3/ All 6 V/s 3/ All -8 Minimum duty cycle 3/ All 0% Maximum duty cycle 3/ All 85% Gain bandwidth product Slew rate 4/ SR PWM Comparator section Bias current, RAMP IBIAS VRAMP = 0 V A Leading edge blanking time tLEB RLEB = 2 k, CLEB = 470 pF 3/ All 300 450 ns Leading edge blanking resistance RLEB VCL / LEB = 3 V 3/ All 8.5 11.5 k See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 6 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 2/ Temperature, TA 1/ Device type Limits Unit Min Max 1.1 1.4 V 80 ns 20 A PWM Comparator section - continued Zero dc threshold, EAOUT VZDC Delay to output time 4/ tDELAY VRAMP = 0 V VEAOUT = 2.1 V, VILIM = 0 V to 2 V step 3/ All 3/ All 3/ All 8 3/ All 4.3 3/ All 100 3/ Current Limit/Start Sequence/Fault section Soft start charge current ISS Full soft start threshold voltage VSS Restart discharge current IDSCH Restart threshold voltage ISS ILIM bias current IBIAS Current limit threshold voltage ICL VSS = 2.5 V 350 A All 0.5 V 3/ All 15 A 3/ All 0.95 1.05 V 3/ All 1.14 1.26 V VILIM = 0 V to 2 V step 3/ All 80 ns IOUT = 20 mA 3/ All 0.4 V VSS = 2.5 V VILIM = 0 V to 2 V step Overcurrent threshold voltage Delay to output time, ILIM 4/ td V Output section Low level output saturation voltage 2.2 IOUT = 200 mA High level output saturation voltage All 3/ IOUT = 20 mA 4/ tr, tf V 3 IOUT = 200 mA Rise / fall time 2.9 All 3/ CL = 1 nF 45 ns See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 7 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 2/ Temperature, TA 1/ Device type Limits Unit Min Max Undervoltage Lockout (UVLO) section Start threshold voltage 3/ All 8.4 9.6 V OVLO hysteresis 3/ All 0.4 1.2 V 3/ All 300 A 3/ All 36 mA Supply Current section Startup current ISU Input current ICC VC = VCC = VTH(start) = -0.5 V 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VCC = 12, TA = TJ, RT = 3.65 k, and CT = 1 nF. 3/ For device type 01, TA = -40C to +125C. For device type 02, TA = -55C to +125C. 4/ Ensured by design. Not production tested. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 8 Case X FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 9 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.104 --- 2.65 A1 0.004 0.012 0.10 0.30 b 0.012 0.020 0.31 0.50 c 0.008 0.013 0.20 0.33 D 0.398 0.413 10.10 10.50 E 0.291 0.299 7.40 7.60 E1 0.393 0.419 9.97 10.63 e L 0.050 BSC 0.016 n 1.27 BSC 0.050 0.40 16 1.27 16 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inch (0.15 mm). 3. Falls within JEDEC MS-013 variation AA. FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 10 Device types 01 and 02 Case outlines X Terminal number Terminal symbol I/O 1 INV I Inverting input to the error amplifier. 2 NI I Non-inverting input to the error amplifier. 3 EAOUT O Output of the error amplifier for compensation. 4 CLK/LEB O Output of the internal oscillator. 5 RT I Timing resistor connection pin for oscillator frequency programming. I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. 6 CT Description 7 RAMP I Non-inverting input to the PWM comparator with 1.25 V internal input offset. In voltage mode operation, this serves as the input voltage feed forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. 8 SS I Soft start input pin which also doubles as the maximum duty cycle clamp. 9 ILIM I Input to the current limit comparator. 10 GND --- Analog ground return pin. 11 OUTA O High current totem pole output A of the on-chip drive stage. 12 PGND --- Ground return pin for the output driver stage. 13 VC --- Power supply pin for the output stage. This pin should be bypassed with 0.1 F monolithic ceramic low ESL capacitor with minimal trace lengths. 14 OUTB O High current totem pole output B of the on-chip drive stage. 15 VCC --- Power supply pin for the device. This pin should be bypassed with 0.1 F monolithic ceramic low ESL capacitor with minimal trace lengths. O 5.1 V reference. For stability, the reference should be bypassed with 0.1 F monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. 16 VREF FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 11 FIGURE 3. Logic diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Top-Side Marking Vendor part number V62/05616-01XE 01295 UC2825AQEP UC2825AQDWREP V62/05616-02XE 01295 UC2825AMEP UC2825AMDWREP 1/ 2/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available at www.ti.com/sc/package. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/05616 PAGE 13