REVISIONS
LTR
DESCRIPTION
DATE
APPROVED
A
Update boilerplate paragraphs to current
requirements. - CFS
09-01-27
Charles F. Saffle
B
Update boilerplate to current MIL-PRF-38535
requirements. - PHN
15-11-24
Thomas M. Hess
CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
CHECKED BY
TITLE
Phu H. Nguyen
YY MM DD
04-03-11
APPROVED BY
Thomas M. Hess
SIZE
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AMSC N/A
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990
CODE IDENT. NO.
MICROCIRCUIT, DIGITAL, DSP CONTROLLERS,
MONOLITHIC SILICON
DWG NO.
V62/04608
16236
B
PAGE
1
OF
39
5962-V008-16
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance DSP controllers microcircuit, with an operating
temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/04608
-
Drawing
number
1.2.1 Device type(s).
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1/
Device type
Generic
Circuit function
01
SM320LF2407A-EP
DSP controllers
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
JEDEC PUB 95
Package style
X
144
JEDEC MS-026
Plastic Quad flatpack
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
1.3 Absolute maximum ratings.
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
2/
Supply voltage range, (DVDD, PLLVCCA, VDDO, and VCCA) .........................................................
VCCP range, ...............................................................................................................................
Input voltage range, (VI) ...........................................................................................................
Output voltage range, (VO) .......................................................................................................
Input clamp current, (IIK) (VIN < 0 or VIN > VCC) .........................................................................
Output clamp current, (IOK) (VO < 0 or VO >VCC) .......................................................................
Operating case temperature ranges, (TC) M version .................................................................
Junction temperature range, (TJ) ..............................................................................................
Storage temperature range, (TSTG)............................................................................................
-0.3 V to +4.6 V 3/
-0.3 V to +5.5 V
-0.3 V to +4.6 V
-0.3 V to +4.6 V
±20 mA
±20 mA
-55°C to +125°C 4/ 5/
-55°C to +130°C 5/
-65°C to +150°C 4/
__________
1/
2/
3/
4/
5/
Users are cautioned to review the manufacturers data manual for additional user information relating to this device.
Clamp current stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
All voltage values are with respect to VSS.
Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a
reduction of overall device life. See manufacturer handout for additional information on enhanced plastic packaging.
See manufacturer handout for device operating life for important information on temperature ranges.
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1.4 Recommended operating conditions.
6/ 7/ 8/
Supply voltage, (VDD/VDDO) (VDDO = VDD ± 0.3 V) .......................................................
Supply ground, (VSS) ..................................................................................................
PLL supply voltage, (PLLVCCA) ...................................................................................
ADC supply voltage, (VCCA) ........................................................................................
Flash programming supply voltage, (VCCP) .................................................................
Device clock frequency (system clock), (fCLKOUT) .......................................................
High level input voltage, (VIH): 10/
XTAL1/CLKIN .......................................................................................................
All other inputs ......................................................................................................
Low level input voltage, (VIL) ......................................................................................
High level output source current, VOH = 2.4 V (IOH):
Output pins group 1 ..............................................................................................
Output pins group 2 ..............................................................................................
Output pins group 3 ..............................................................................................
Low level output current, VOL = VOL Max, (IOL):
Output pins group 1 ..............................................................................................
Output pins group 2 ..............................................................................................
Output pins group 3 ..............................................................................................
Operating case temperature (TC) M version ...............................................................
Junction temperature (TJ) ...........................................................................................
Flash endurance for the array (Write/erase cycles), (Nf) (-40°C to +85°C) ................
Junction to air (RθJA) ...................................................................................................
Junction to case (RθJC) ...............................................................................................
+3.0 V to +3.6 V
0V
+3.0 V to +3.6 V
+3.0 V to +3.6 V 9/
+4.75 V to +5.25 V
2 MHz to 40 MHz
+2.2 V to VDD+0.3 V
+2.0 V to VDD+0.3 V
+0.8 V maximum
-2 mA maximum
-4 mA maximum
-8 mA maximum
11/
11/
11/
2 mA maximum 11/
4 mA maximum 11/
8 mA maximum 11/
-55°C to +125°C
-40°C to +130°C
10K Typical cycles
44°C/W
13°C/W
10-bit analog to digital converter (ADC)
Analog supply voltage, (VCCA) ....................................................................................
Analog ground, (VSSA) ................................................................................................
Analog supply reference source, (VREFHI) 12/ ...........................................................
Analog ground reference source, (VREFLO) 12/ .........................................................
Analog input voltage, ADCIN00-ADCIN07, (VAI) ........................................................
+3.0 V to +3.6 V
0V
VREFLO to VCCA
VSSA to VREFHI
VREFLO to VREFHI
__________
6/
7/
8/
9/
10/
11/
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
Refer to the mechanical data package page for thermal resistance values, θJA (junction to ambient) and θJC (junction to case).
The drive strength of the EVA PWM pins and the EVB PWM pins are not identical.
VCCA should not differ from VDD by more than 0.3 V.
The input buffers used in 240x/240xA are not 5 V compatible.
Primary signals and their groupings:
Group 1:
PWM1-PWM6, T1PWM, T2PWM, CAP1-CAP6, TCLKINA, IOPC1, TCK, TDI, TMS, XF, A0-A15.
Group 2:
12/
PS / DS / IS , RD , W/ R , VIS _ OE , D0-D15, T3PWM, T4PWM, PWM7-PWM12, CANTX, CANRX, SPICLK,
SPISOMI, SPISIMO, SPISTE , EMU0, EMU1, TDO, TMS2.
Group 3:
TDIRA, TDIRB, SCIRX, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB.
VREFHI and VREFLO must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
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PAGE
3
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington,
VA 22201-3834 or online at http://www.jedec.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as specified in figure 3.
3.5.4 Load circuit. The load circuit shall be as specified in figure 4.
3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 5-23.
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TABLE I. Electrical performance characteristics.
Test
High level output voltage
Low level output voltage
VOL
Input current (low level)
IIL
Input current (high level)
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Symbol
VOH
1/
VDD = 3.0 V,
IOH = IOH Max
Limits
Min
Max
2.2
VDDO
2.4
VDDO
SPISOMI
All other outputs
All outputs at 50 µA
Unit
V
VDDO-0.2
IOL = IOL Max
2/
0.9
All other outputs
0.4
With pull up
VDD = 3.3 V, VIN = 0 V
-9
±2
With pull up
±2
IIH
VDD = 3.3 V, VIN = VDD
Output current, high impedance state (offstate)
IOZ
VO = VDD or 0 V
Input capacitance
CI
2 Typ
Output capacitance
CO
3 Typ
With pull down
µA
-40
With pull down
9
40
±2
pF
Current consumption by power-supply pins at 40 MHz CLOCKOUT
Operational current
IDD
ADC module current
3/
All I/O pins are floating.
4/
120
ICCA
mA
20
Current consumption by power supply pins during low power modes at 40 MHz CLOCKOUT
Mode: LPM0
5/
Mode: LPM1
6/
Mode: LPM2
7/ 8/
Operational current
ADC module current
Operational current
ADC module current
Operational current
ADC module current
IDD
3/
80
ICCA
IDD
3/
45
ICCA
IDD
mA
20
0
3/
ICCA
400
µA
0
mA
See notes at end of table.
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PAGE
5
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Limits
Unit
Min
Max
Resonator
4
13
Crystal
4
20
CLKIN
4
20
EXTERNAL REFERENCE CRYSTAL/CLOCK WITH PLL CIRCUIT ENABLED
Timings with the PLL circuit enabled
Input clock frequency
fx
9/
MHz
Switching characteristics [H = 0.5 tc(CO)]
Cycle time, CLKOUT
PLL mode: x4 mode
9/
tc(CO)
See figure 5
25
ns
Fall time, CLKOUT
tf(CO)
4 Typ
Rise time, CLKOUT
tr(CO)
4 Typ
Pulse duration, CLKOUT low
tW(COL)
H-3
Pulse duration, CLKOUT high
tW(COH)
H-3
Transition time, PLL synchronized after RS pin high
H+3
H+3
4096tc(CI)
tt
Timing requirements
Cycle time, XTAL1/CLKIN
tc(CI)
See figure 5
250
Fall time, XTAL1/CLKIN
tf(CI)
5
Rise time, XTAL1/CLKIN
tr(CI)
5
Pulse duration, XTAL1/CLKIN low as percentage of tc(CI)
tW(CIL)
40
60
Pulse duration, XTAL1/CLKIN high as percentage of tc(CI)
tW(CIH)
40
60
ns
%
RS TIMINGS
Timing requirements for a reset [H = 0.5tc(CO)]
Pulse duration, stable CLKIN to RS high
tW(RSL)
Pulse duration, RS low
tW(RSL2)
PLL lock up time
See figure 6
8tc(CI)
8tc(CI)
tp
Delay time, reset vector executed after PLL lock time
cycles
4096tc(CI)
td(EX)
ns
36H Typ
Switching characteristics for a reset [H = 0.5tc(CO)]
Pulse duration, RS low
10/
Delay time, reset vector executed after PLL lock time
PLL lock time (input cycles)
tW(RSL1)
See figure 7
128tc(CI)
td(EX)
ns
36H
tp
4096tc(CI)
See notes at end of table.
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PAGE
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
LOW POWER MODE TIMINGS
Switching characteristics [H = 0.5tc(CO)]
Low power modes
Delay time, CLKOUT switching to program execution
resume
td(WAKE-A)
Delay time, Idle instruction executed to CLKOUT high
See
figure 8
IDLE1
LPM0
12 x tc(CO) Typ
IDLE2
LPM1
15 x tc(CO) Typ
td(IDLE-COH)
IDLE2
LPM1
4tc(CO) Typ
Delay time, wake interrupt asserted to oscillator running
td(WAKE-OSC)
ms
td(IDLE-OSC)
HALT
{PLL/OSC
power down}
11/
Delay time, idle instruction executed to oscillator power
off
LPM2
4tc(CO) Typ
ns
td(EX)
Delay time, reset vector executed after RS high
ns
36H
LPM2 WAKEUP TIMINGS
Switching characteristics
td(PDP-PWM)HZ
Delay time, PDPINTx low to PWM high impedance
state
Delay time, INT low/high to interrupt vector fetch
See figure 9
12
12/
td(INT)
ns
10tc(CO)
Timing requirements
Pulse duration, PDPINTx input
low
If bit 6 of SCSR2 = 0
If bit 6 of SCSR2 = 1
tW(PDP-WAKE)
13/
PLL lock up time
See figure 9
6tc(CO)
ns
12tc(CO)
tp
4096tc(CI)
XF, BIO , AND MP/ MC TIMINGS
Switching characteristics
Delay time, CLKOUT high to XF high/low
td(XF)
See figure 10
-7
7
Setup time, BIO or MP/ MC low before CLKOUT low
tsu(BIO)CO
See figure 10
12
12/
Hold time, BIO or MP/ MC low after CLKOUT low
th(BIO)CO
ns
Timing requirements
ns
22
See notes at end of table.
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PAGE
7
TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
TIMING EVENT MANAGER INTERFACE
PWM TIMINGS
Switching characteristics for PWM timing [H = 0.5tc(CO)]
Pulse duration, PWMx output high/low
tW(PWM)
Delay time, CLKOUT low to PWMx output switching
Timing requirements [H = 0.5tc(CO)]
14/
See figure 11
2H-2
ns
td(PWM)CO
18
15/
Pulse duration, TMRDIR low/high
tW(TMRDIR)
Pulse duration, TMRCLK low as a percentage of
TMRCLK cycle time
tW(TMRCLK)
40
60
Pulse duration, TMRCLK high as a percentage of
TMRCLK cycle time
tWh(TMRCLK)
40
60
tc(TMRCLK)
4 x tc(CO)
ns
6tc(CO)
ns
Cycle time, TMRCLK
See figure 11
4H+5
Ns
%
CAPTURE AND QEP TIMINGS
Timing requirements
Pulse duration, CAPx input
low/high
If bit 6 of SCSR2 = 0
tW(CAP)
13/
See figure 12
if bit 6 of SCSR2 = 1
12tc(CO)
INTERRUPT TIMINGS
16/
Switching characteristics
Delay time, PDPINTx low to PWM high impedance
state
td(PDP-PWM)HZ
Delay time, INT low/high to interrupt vector fetch
See figure 13
12
12/
td(INT)
ns
10tc(CO)
Timing requirements
Pulse duration, INT input
low/high
If bit 6 of SCSR2 = 0
Pulse duration, PDPINTx
input low
If bit 6 of SCSR2 = 0
tW(INT)
13/
See figure 13
6tc(CO)
if bit 6 of SCSR2 = 1
ns
12tc(CO)
tW(PDP)
13/
6tc(CO)
if bit 6 of SCSR2 = 1
12tc(CO)
GENERAL PURPOSE INPUT/OUTPUT TIMINGS
Switching characteristics
Delay time, CLKOUT low to GPIO low/high
td(GPIO)CO
Rise time, GPIO switching low to high
tr(GPIO)
Fall time, GPIO switching high to low
tf(GPIO)
All GPIOs
See figure 14
9
ns
8
6
Timing requirements [H = 0.5tc(CO)]
Pulse duration, GPI high/low
tW(GPI)
See figure 14
2H+15
ns
See notes at end of table.
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PAGE
8
TABLE I. Electrical performance characteristics - Continued.
No.
Test
Symbol
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
1/
Limits
SPI when
(SPIBRR +1) is even
or SPIBRR = 0 or 2
Min
Unit
SPI when
(SPIBRR +1) is odd
and SPIBRR > 3
Max
Min
Max
4tc(CO)
128tc(CO)
5tc(CO)
127tc(CO)
SPI MASTER MODE TIMING PARAMETERS
SPI master mode external timing parameters (clock phase = 0) 17/ 18/
1
Cycle time, SPICLK
2
Pulse duration, SPICLK high
(clock parity = 0)
tW(SPCH)M
20/
21/
22/
23/
19/
Pulse duration, SPICLK low
(clock parity = 1)
tW(SPCL)M
20/
21/
22/
23/
3
Pulse duration, SPICLK low
(clock parity = 0)
tW(SPCL)M
20/
21/
24/
25/
19/
Pulse duration, SPICLK high
(clock parity = 1)
tW(SPCH)M
20/
21/
24/
25/
Delay time, SPICLK high to
SPISIMO valid
(clock polarity = 0)
td(SPCH-SIMO)M
-10
10
-10
10
Delay time, SPICLK low to
SPISIMO valid
(clock polarity = 1)
td(SPCL-SIMO)M
-10
10
-10
10
Valid time, SPISIMO data valid
after SPICLK low
(clock polarity = 0)
tv(SPCL-SIMO)M
20/
24/
Valid time, SPISIMO data valid
after SPICLK high
(clock polarity = 1)
tv(SPCH-SIMO)M
20/
24/
8
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
tsu(SOMI-SPCL)M
0
0
19/
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
tsu(SOMI-SPCH)M
0
0
Valid time, SPISOMI data valid
after SPICLK low
(clock polarity = 0)
tv(SPCL-SOMI)M
26/
22/
Valid time, SPISOMI data valid
after SPICLK high
(clock polarity = 1)
tv(SPCH-SOMI)M
26/
22/
4
19/
5
19/
9
19/
tc(SPC)M
See figure 15
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
No.
Test
Symbol
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
1/
Limits
SPI when
(SPIBRR +1) is even
or SPIBRR = 0 or 2
Min
Unit
SPI when
(SPIBRR +1) is odd
and SPIBRR > 3
Max
Min
Max
4tc(CO)
128tc(CO)
5tc(CO)
127tc(CO)
SPI MASTER MODE TIMING PARAMETERS – (CONTINUED)
SPI master mode external timing parameters (clock phase = 1) 18/ 27/
1
Cycle time, SPICLK
2
Pulse duration, SPICLK high
(clock parity = 0)
tW(SPCH)M
20/
21/
22/
23/
19/
Pulse duration, SPICLK low
(clock parity = 1)
tW(SPCL)M
20/
21/
22/
23/
3
Pulse duration, SPICLK low
(clock parity = 0)
tW(SPCL)M
20/
21/
24/
25/
19/
Pulse duration, SPICLK high
(clock parity = 1)
tW(SPCH)M
20/
21/
24/
25/
Setup time, SPISIMO data valid
before SPICLK low
(clock polarity = 0)
tsu(SIMO-SPCH)M
20/
20/
Setup time, SPISIMO data valid
after SPICLK low
(clock polarity = 1)
tsu(SIMO-SPCL)M
20/
20/
Valid time, SPISIMO data valid
after SPICLK high
(clock polarity = 0)
tv(SPCH-SIMO)M
20/
20/
Valid time, SPISIMO data valid
after SPICLK low
(clock polarity = 1)
tv(SPCL-SIMO)M
20/
20/
10
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
tsu(SOMI-SPCH)M
0
0
19/
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
tsu(SOMI-SPCL)M
0
0
Valid time, SPISOMI data valid
after SPICLK high
(clock polarity = 0)
tv(SPCH-SOMI)M
26/
20/
Valid time, SPISOMI data valid
after SPICLK low
(clock polarity = 1)
tv(SPCL-SOMI)M
26/
20/
6
19/
7
19/
11
19/
tc(SPC)M
See figure 15
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
No.
Test
Symbol
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Limits
Unit
Min
Max
SPI SLAVE MODE TIMING PARAMETERS
SPI slave mode external timing parameters (clock phase = 0) 18/ 28/
12
Cycle time, SPICLK
13
Pulse duration , SPICLK high (clock
polarity = 0)
tc(SPC)S
See figure 16
4tc(CO)
18/
ns
tW(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
19/
Pulse duration , SPICLK low (clock
polarity = 1)
tW(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
14
Pulse duration , SPICLK low (clock
polarity = 0)
tW(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
19/
Pulse duration , SPICLK high (clock
polarity = 1)
tW(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
15
Delay time, SPICLK high to
SPISOMI valid (clock parity = 0)
td(SPCH-SOMI)S
0.375tc(SPC)S - 10
19/
Delay time, SPICLK low to SPISOMI
valid (clock parity = 1)
td(SPCL-SOMI)S
0.375tc(SPC)S - 10
16
Valid time, SPISOMI data valid after
SPICLK low (clock parity = 0)
tv(SPCL-SOMI)S
0.75tc(SPC)S - 10
19/
Valid time, SPISOMI data valid after
SPICLK high (clock parity = 1)
tv(SPCH-SOMI)S
0.75tc(SPC)S - 10
19
Setup time, SPISIMO before SPCLK
low (clock polarity = 0)
tsu(SIMO-SPCL)S
0
19/
Setup time, SPISIMO before SPCLK
high (clock polarity = 1)
tsu(SIMO-SPCH)S
0
20
Valid time, SPISIMO data valid after
SPICLK low (clock parity = 0)
tv(SPCL-SIMO)S
0.5tc(SPC)S
19/
Valid time, SPISIMO data valid after
SPICLK high (clock parity = 1)
tv(SPCH-SIMO)S
0.5tc(SPC)S
See notes at end of table.
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11
TABLE I. Electrical performance characteristics - Continued.
No.
Test
Symbol
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Limits
Unit
Min
Max
SPI SLAVE MODE TIMING PARAMETERS – (CONTINUED)
SPI slave mode external timing parameters (clock phase = 1) 18/ 29/
12
Cycle time, SPICLK
13
Pulse duration , SPICLK high (clock
polarity = 0)
tc(SPC)S
See figure 16
8tc(CO)
ns
tW(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
19/
Pulse duration , SPICLK low (clock
polarity = 1)
tW(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
14
Pulse duration , SPICLK low (clock
polarity = 0)
tW(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
19/
Pulse duration , SPICLK high (clock
polarity = 1)
tW(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
17
Setup time, SPISOMI before SPCLK
high (clock polarity = 0)
tsu(SOMI-SPCH)S
0.125tc(SPC)S
19/
Setup time, SPISIMO before SPCLK
low (clock polarity = 1)
tsu(SOMI-SPCL)S
0.125tc(SPC)S
18
Valid time, SPISOMI data valid after
SPICLK high (clock parity = 0)
tv(SPCH-SOMI)S
0.75tc(SPC)S
19/
Valid time, SPISOMI data valid after
SPICLK low (clock parity = 1)
tv(SPCL-SOMI)S
0.75tc(SPC)S
21
Setup time, SPISIMO before SPCLK
high (clock polarity = 0)
tsu(SIMO-SPCH)S
0
19/
Setup time, SPISIMO before SPCLK
low (clock polarity = 1)
tsu(SIMO-SPCL)S
0
22
Valid time, SPISIMO data valid after
SPICLK high (clock parity = 0)
tv(SPCH-SIMO)S
0.5tc(SPC)S
19/
Valid time, SPISIMO data valid after
SPICLK low (clock parity = 1)
tv(SPCL-SIMO)S
0.5tc(SPC)S
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
EXTERNAL MEMORY INTERFACE READ TIMINGS
Switching characteristics for an external memory interface read at 40 MHz [H = 0.5tc(CO)]
Delay time, CLKOUT low to control valid
td(COL-CNTL)
See figure 17
4
Delay time, CLKOUT low to control inactive
td(COL-CNTH)
5
Delay time, CLKOUT low to address valid
td(COL-A)RD
8
Delay time, CLKOUT high to RD strobe active
td(COH-RDL)
5
Delay time, CLKOUT low to RD strobe inactive high
td(COL-RDH)
Delay time, CLKOUT low to STRB strobe active low
td(COL-SL)
5
Delay time, CLKOUT low to STRB strobe inactive high
td(COL-SH)
6
-8
1
td(WRN)
5
Delay time, W/ R going low to R/ W rising
Hold time, address valid after CLKOUT low
th(A)COL
-1
Setup time, address valid before RD strobe active low
tsu(A)RD
H-7
Hold time, address valid after RD strobe inactive high
Timing requirements [H = 0.5tc(CO)]
th(A)RD
0
Access time, read data from address valid
ta(A)
Access time, read data from RD low
ta(RD)
ns
See figure 17
2H-10
ns
H-7
Setup time, read data before RD strobe inactive high
tsu(D)RD
8
Hold time, read data after RD strobe inactive high
th(D)RD
0
12/
Hold time, read data after address invalid
th(AIV-D)
0
12/
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
EXTERNAL MEMORY INTERFACE WRITE TIMINGS
Switching characteristics for an external memory interface write at 40 MHz [H = 0.5tc(CO)]
Delay time, CLKOUT high to control valid
td(COH-CNTL)
Delay time, CLKOUT high to control inactive
See figure 18
4
ns
td(COH-CNTH)
5
Delay time, CLKOUT high to address valid
td(COH-A)W
10
Delay time, CLKOUT high to R/ W low
td(COH-RWL)
6
Delay time, CLKOUT high to R/ W high
td(COH-RWH)
6
Delay time, CLKOUT low to WE strobe active low
td(COL-WL)
6
Delay time, CLKOUT low to WE strobe inactive high
Enable time, data bus driven from CLKOUT low
td(COL-WH)
6
Delay time, CLKOUT low to STRB active low
td(COL-SL)
6
Delay time, CLKOUT low to STRB inactive high
td(COL-SH)
6
td(WRN)
5
Delay time, W/ R going low to R/ W rising
Hold time, address valid after CLKOUT low
ten(D)COL
-3
th(A)COLW
-5
Setup time, address valid before WE strobe active low
tsu(A)W
H-9
Setup time, write data before WE strobe inactive high
tsu(D)W
2H-17
Hold time, write data after WE strobe inactive high
th(D)W
2 12/
tdis(W-D)
Disable time, data bus high impedance from WE high
EXTERNAL MEMORY INTERFACE READY ON READ TIMINGS
Switching characteristics for an external memory interface ready on read
Delay time, CLKOUT low to address valid
td(COL-A)RD
5
See figure 19
8
ns
Timing requirements for an external memory interface ready on read
Hold time, READY after CLKOUT high
th(RDY)COH
See figure 19
-3
tsu(D)RD
Setup time, read data before RD strobe inactive high
Valid time, READY after address valid on read
tv(RDY)ARD
Setup time, READY before CLKOUT high
tsu(RDY)COH
12/
ns
8
-2
12/
22
Timing requirements for an external memory interface ready on read with one software wait state and one external wait state
Hold time, READY after CLKOUT high
th(RDY)COH
Setup time, READY before CLKOUT high
tsu(RDY)COH
Delay time, CLKOUT low to address valid
td(COL-A)RD
See figure 20
H-2.5
ns
H-9.5
8
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-55°C ≤ TC ≤+125°C
3.0 V ≤ VDD/VDDO ≤ 3.6 V
4.75 V ≤ VCCP ≤ 5.25 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
EXTERNAL MEMORY INTERFACE READY ON WRITE TIMINGS
Switching characteristics for an external memory interface ready on write
Delay time, CLKOUT high to address valid
td(COH-A)W
See figure 21
10
ns
Timing requirements for an external memory interface ready on write [H = 0.5tc(CO)]
Hold time, READY after CLKOUT high
Setup time, write data before WE strobe inactive high
Valid time, READY after address valid on write
Setup time, READY before CLKOUT high
th(RDY)COH
See figure 21
-3
tsu(D)W
ns
2H-17
tv(RDY)AW
-3
tsu(RDY)COH
12/
22
Timing requirements for an external memory interface ready on write with one software wait state and one external wait state
Hold time, READY after CLKOUT high
th(RDY)COH
Setup time, READY before CLKOUT high
tsu(RDY)COH
Delay time, CLKOUT high to address valid
td(COH-A)W
See figure 22
H-2.5
ns
H-9.5
10
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition 30/
-55°C ≤ TC ≤+125°C
3.0 V ≤ VCCA ≤ 3.60 V
unless otherwise noted
Symbol
Limits
Unit
Min
Max
4
30
MHz
20
mA
1
µA
IADREFHI
1.5
mA
IADCIN
1
µA
10 BIT ANALOG TO DIGITAL CONVERTER (ADC)
ADC oprating frequency (LF240xA)
ADC operating frequency
Operating characteristics
31/
Analog supply current
ICCA
VCCA = 3.3 V
PLL or OSC power
down
VCCA = VREFHI = 3.3 V
VREFHI input current
Analog input leakage
Analog input capacitance
Cai
Delay time, power up to ADC valid
td(PU)
Analog input source impedance
ZAI
Typical capacitive load
on analog input pin
Non sampling
10 Typ
Sampling
30 Typ
pF
pF
Time to stabilize analog stage after power up
32/
10
µs
10
Ω
±2 Typ
Zero offset error
LSB
EDNL and EINL for LF2407A
Differential nonlinearity error
Integral nonlinearity error
33/
EDNL
35/
Internal ADC module timings
CLKOUT = 30 MHz,
34/
EINL
±3
LSB
±3
LSB
36/
Cycle time, ADC prescaled clock
tc(AD)
Pulse duration, total sample/hold and
conversion time 37/
tw(SHC)
Pulse duration, sample and hold time
tw(SH)
Pulse duration, total conversion time
See figure 23
33.3
ns
500
2tc(AD)
38/
tw(C)
10tc(AD)
td(SOC-SH)
2tc(CO)
Delay time, end of conversion to data
loaded into result register
td(EOC)
2tc(CO)
Delay time, ADC flag to ADC interrupt
td(ADCINT)
2tc(CO)
Delay time, start of conversion to beginning
of sample and hold
Flash parameter at 40 MHz CLOCKOUT
Time/Word (16-bit)
Time/4K Sector
Time/12K Sector
Time/4K Sector
39/
Clear/
Programming
time 40/
Erase time
40/
Time/12K Sector
Indicates the typical/maximum current
consumption during the Clear-Erase
program (C-EP) cycle
32tc(AD)
30 Typ
µs
130 Typ
ms
400 Typ
ms
350 Typ
ms
1 Typ
s
ICCP
(VCCP pin current)
15
mA
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
1/
2/
3/
4/
5/
6/
7/
8/
9/
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may
not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
A[15:0], PWM1-PWM12, T1PWM, T2PWM, TCLKINA, W/ R , XINT1, XINT2.
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
A test code running in B0 RAM does the following:
1. Enables clock to all peripherals.
2. Toggles all PWM outputs at 20 kHz.
3. Performs a continuous conversion of all ADC channels.
4. An infinite loop which transmits a character out of SCI and executes MACD instructions.
Clock to all peripherals is enabled. No I/O pins are switching.
Clock to all peripherals is disabled. No I/O pins are switching.
Clock to all peripherals is disabled. Flash is powered down. Input clock is disabled.
If a quartz crystal or ceramic resonator is used as the clock source, the PLM2 mode shuts down the internal oscillator.
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz
minimum.
10/
11/
12/
13/
14/
15/
The parameter tw(RSL1) refers to the RS is an output.
OSC start up and PLL lock time.
Not verified; for information purposes only.
This is different from 240x devices.
PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.
Parameter TMDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
16/
17/
18/
19/
20/
21/
22/
23/
24/
25/
26/
27/
28/
29/
30/
INT refers to XINT1 and XINT2. PDP refers to PDPINTx .
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/CLKOUT = tc(CO).
The active edge of the SPICKLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
0.5tc(SPC)M-10
0.5tc(SPC)M
0.5tc(SPC)M-0.5tc(CO)-10
0.5tc(SPC)M-0.5tc(CO)
0.5tc(SPC)M+0.5tc(CO)-10
0.5tc(SPC)M+0.5tc(CO)
0.25tc(SPC)M-10
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
ADC specifications conditions:
Resolution .................................................................... 10 bit (1024 values)
Monotonic ................................................................... 000h to 3FFh (00h for VI ≤ VREFLO; 3FFh for VI ≥ VREFHI)
Minimum conversion time (including sample time) ...... 500 ns.
Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases,
or both, the LSB size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs
increase.
Analog input source impedance needed for conversions to remain within specifications at min tw(SH).
Difference between the actual step width and the ideal value.
Test conditions: VREFHI = VCCA, VREFLO = VSSA.
Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error.
The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the manufacturer
TMS320FL/LC240xA DSP controllers reference guide: System and peripherals (literature number SPRU357) for more
details.
31/
32/
33/
34/
35/
36/
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TABLE I. Electrical performance characteristics - Continued.
37/
38/
39/
40/
1/
The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC).
Can be varied by ACQ prescalar bits in the ADCCTRL1 register.
Manufacturer releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change.
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on
chip RAM. The values specified are when VDD = 3.3 V and VCCP = 5.0 V, and any deviation from these values could affect the
timing parameters. Aging and process variance could also impact the timing parameters.
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Notes:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Fall within JEDEC MS-026.
FIGURE 1. Case outlines.
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Millimeters
Symbol
Min
Max
A
1.60
A1
1.35
b
0.17
1.45
0.27
c
0.13 NOM
D/E
21.80
22.20
D1/E1
19.80
20.20
D2/E2
17.50 TYP
e
0.50 TYP
K
0.45
0.75
FIGURE 1. Case outlines - Continued.
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1/
Pin
No.
1
Signal Name
Pin
No.
Signal Name
TCLKINA/IOPB7
Pin
No.
73
TRST
37
2
TDIRB/IOPF4
38
PWM12/IOPE6
74
3
VSSO
39
A13
4
VDDO
40
5
D7
6
T4PWM/T4CMP/IOPF3
7
8
PDPINTA
T3PWM/T3CMP/IOPF2
9
D8
10
Signal Name
Signal Name
CLKOUT/IOPE0
Pin
No.
109
A2
110
ADCIN01
75
CAP3/IOPA5
111
ADCIN09
PWM6/IOPB3
76
VSSO
112
ADCIN00
41
VSSO
77
VDDO
113
ADCIN08
42
VDDO
78
A1
114
VREFLO
43
A12
79
CAP2/QEP2/IOPA4
115
VREFHI
44
PWM5/IOPB2
80
A0
116
VCCA
45
A11
81
CAP5/QEP1/IOPA3
117
VSSA
PLLF2
46
PWM11/IOPE5
82
IS
118
MP/ MC
11
PLLF
47
PWM4/IOPB1
83
CAP1/QEP1/IOPA3
119
BIO /IOPC1
12
PLLVCCA
48
A10
84
PS
120
READY
13
D9
49
VSS
85
VSS
121
BOOT _ EN /XF 1/
14
TDIRA/OPB6
50
VDD
86
VDD
122
ENA_144
15
D10
51
A9
87
DS
123
XTAL1/CLKIN
16
T1PWM/T1CMP/IOPB4
52
PWM3/IOPB0
88
CAP4/QEP3/IOPE7
124
XTAL2
17
D11
53
A8
89
125
VSSO
18
T2PWM/T2CMP/IOPB5
54
PWM2/IOPA7
90
WE
EMU0
126
TCLKINB/IOPF5
19
W/ R /IOPC0
55
PWM10/IOPE4
91
EMU1/ OFF
127
D0
20
D12
56
PWM1/IOPA6
92
R/ W
128
VSS
21
XINT2/ADCSOC/IOPD0
57
A7
93
129
VDD
22
D13
58
VCCP
94
RD
VSSO
130
D1
23
XINT1/IOPA2
59
PWM9/IOPE3
95
VDDO
131
IOPF6
24
D14
60
TP1
96
STRB
132
D2
25
SCITXD/IOPA0
61
A6
97
VIS _ OE
133
RS
26
SCIRXD/IOPA1
62
PWM8/IOPE2
98
ADCIN15
134
D3
27
D15
63
TP2
99
ADCIN07
135
TCK
28
VSS
64
A5
100
ADCIN06
136
D4
29
VDD
65
PWM7/IOPE1
101
ADCIN14
137
30
SPISIMO/IOPC2
66
VSSO
102
ADCIN05
138
PDPINTB
D5
31
A15
67
VDDO
103
ADCIN04
139
TDI
32
SPISOMI/IOPC3
68
A4
104
ADCIN13
140
VSSO
33
SPISTE /IOPC5
69
CAP6/IOPF1
105
ADCIN03
141
VDDO
34
A14
70
CANRX/IOPC7
106
ADCIN12
142
TDO
35
SPICLK/IOPC4
71
A3
107
ADCIN02
143
D6
36
TMS2
72
CANTX/IOPC6
108
ADCIN11
144
TMS
ADCIN10
BOOT _ EN is available on flash devices.
FIGURE 2. Terminal connections.
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FIGURE 3. Block diagram.
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Where:
IOL
IOH
VLoad
CT
= 2.0 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
= 50 pF typical load circuit capacitance.
FIGURE 4. Load circuit.
FIGURE 5. Timing waveforms.
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Notes:
1.
2.
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
tOSCST is the oscillator start up time, which is dependent on crystal/resonator and board design.
FIGURE 6. Timing waveforms - Continued.
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Notes:
1.
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
FIGURE 7. Timing waveforms - Continued.
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Notes:
1.
WAKE INT can be any valid interrupt or RESET.
FIGURE 8. Timing waveforms - Continued.
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Notes:
1.
2.
3.
4.
tOSC is the oscillator start-up time.
CLKOUT frequency after LPM2 wake up will be the same as that upon entering LPM2 (x4 shown as an example).
PDPINTx interrupt vector, if PDPINTx interrupt is enabled.
If PDPINTx interrupt is disabled.
FIGURE 9. Timing waveforms - Continued.
FIGURE 10. Timing waveforms - Continued.
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Note:
1. Parameter TMRDIR is equal to the pin TDIRx.
FIGURE 11. Timing waveforms - Continued.
FIGURE 12. Timing waveforms - Continued.
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Note:
1.
PWM refers to all PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is
taken high depends on the state of the FCOMPOE bit.
FIGURE 13. Timing waveforms - Continued.
FIGURE 14. Timing waveforms - Continued.
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Note:
1.
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active
until the SPI communication stream is complete.
FIGURE 15. Timing waveforms - Continued.
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Note:
1.
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active
until the SPI communication stream is complete.
FIGURE 16. Timing waveforms - Continued.
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FIGURE 17. Timing waveforms - Continued.
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Note:
1.
VIS _ OE will be visible at pin 97 of LF2407A when ENA_144 is low along with BVIS bits (10, 9 of WSGR register – FFFFh
@I/O) set to 10 or 11. CLKOUT and VIS _ OE indicate internal memory write cycles(program/data). During VIS _ OE
cycles, the external bus will be driven. CLKOUT is to be used along with VIS _ OE for trace capabilities.
FIGURE 18. Timing waveforms - Continued.
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Note:
1. The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more
details.
FIGURE 19. Timing waveforms - Continued.
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FIGURE 20. Timing waveforms - Continued.
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FIGURE 21. Timing waveforms - Continued.
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FIGURE 22. Timing waveforms - Continued.
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FIGURE 23. Timing waveforms - Continued.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
1/
Vendor item drawing administrative
control number 1/
Device manufacturer
CAGE code
Vendor part number
V62/04608-01XE
01295
SM320LF2407APGEMEP
The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
CAGE code
01295
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
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