LMH0026 SD SDI Reclocker with Dual Differential Outputs General Description Features The LMH0026 SD SDI Reclocker retimes serial digital video data conforming to the SMPTE 259M (C) standard. The LMH0026 operates at the serial data rate of 270 Mbps and also supports DVB-ASI operation at 270 Mbps. The LMH0026 retimes the incoming data to suppress accumulated jitter. The LMH0026 recovers the serial data-rate clock and optionally provides it as an output. The LMH0026 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, SD indicator output, lock detect output, auto/manual data bypass, and output mute. The serial data inputs, outputs, and serial data-rate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible. The LMH0026 is powered from a single 3.3V supply. Power dissipation is typically 330 mW. The device is housed in a 20pin e-TSSOP package. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Supports SMPTE 259M (C) serial digital video standard Supports 270 Mbps serial data rate operation Supports DVB-ASI at 270 Mbps Single 3.3V supply operation 330 mW typical power consumption Two differential, reclocked outputs Choice of second reclocked output or low-jitter, differential, data-rate clock output Single 27 MHz external crystal or reference clock input Lock Detect indicator output Output mute function for data and clock Auto/Manual reclocker bypass Differential LVPECL compatible serial data inputs and outputs LVCMOS control inputs and indicator outputs 20-Pin e-TSSOP package Industrial temperature range: -40°C to +85°C Footprint compatible with the LMH0046 and LMH0346 Applications ■ SDTV serial digital video interfaces for: — — — — Digital video routers and switchers Digital video processing and editing equipment DVB-ASI equipment Video standards and format converters Typical Application 30001801 © 2009 National Semiconductor Corporation 300018 www.national.com LMH0026 SD SDI Reclocker with Dual Differential Outputs October 6, 2009 LMH0026 Block Diagram 30001803 Connection Diagram 30001802 The exposed die attach pad is the negative electrical terminal for this device. It must be connected to the negative power supply voltage. 20-Pin e-TSSOP Order Number LMH0026MH See NS Package Number MXA20A www.national.com 2 LMH0026 Pin Descriptions Pin Name Description 1 LF1 Loop Filter. 2 LF2 Loop Filter. 3 NC No Connect. Not bonded internally. 4 RSVD Reserved. Do not connect or connect to ground. 5 SDI Data Input true. 6 SDI Data Input complement. 7 VCC Positive power supply input. 8 BYPASS/AUTO BYPASS Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has an internal pulldown. 9 OUTPUT MUTE Data and Clock Output Mute input. Mutes the output when low. This pin has an internal pullup. 10 XTAL IN/EXT CLK Crystal or External Oscillator input. 11 XTAL OUT Crystal Oscillator output. 12 LOCK DETECT PLL Lock Detect output (active high). 13 SCO/SDO2 Serial Clock or Serial Data Output 2 complement. 14 SCO/SDO2 Serial Clock or Serial Data Output 2 true. 15 VCCO Positive power supply input (Output Driver). 16 SDO Data Output complement. 17 SDO Data Output true. 18 VCCO Positive power supply input (output driver). 19 SD SD indicator output. Output is high when locked to 270 Mbps. 20 SCO_EN Serial Clock or Serial Data 2 Output select. Sets second output to output the clock when high and the data when low. This pin has an internal pulldown. VEE Connect exposed DAP to negative power supply (ground). DAP 3 www.national.com LMH0026 Storage Temp. Range Junction Temperature Lead Temperature (Soldering 4 Sec) ESD Rating (HBM) ESD Rating (MM) ESD Rating (CDM) Absolute Maximum Ratings (Note 1) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC–VEE) Logic Supply Voltage (Vi) 4.0V VEE−0.15V to VCC +0.15V Logic Input Current (single input): Vi = VEE−0.15V Vi = VCC+0.15V Logic Output Voltage (Vo) Logic Output Source/Sink Current Serial Data Input Voltage (VSDI) Serial Data Output Sink Current (ISDO) Package Thermal Resistance, TSSOP −65°C to +150°C +150°C +260°C (Pb-free) 7 kV 350V 1250V Recommended Operating Conditions Supply Voltage (VCC–VEE) Logic Input Voltage Differential Serial Input Voltage Serial Data or Clock Output Sink Current (ISO) Operating Free Air Temperature (TA) −5 mA +5 mA VEE−0.15V to VCC +0.15V ±8 mA VCC to VCC−2.0V 3.3V ±5% VEE to VCC 800 mV ±10% 16 mA max. −40°C to +85°C 24 mA θJA 26.6°C/W θJC 2.4°C/W DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2, Note 3) Symbol Parameter Conditions VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VCC IIL Input Current Low Level VIL = VEE VOH Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level IOL = +2 mA VSDID Serial Input Voltage, Differential VCMI Input Common Mode Voltage VSDID = 200 mV VSDOD Serial Output Voltage, Differential 100Ω differential load VCMO Output Common Mode Voltage 100Ω differential load Power Supply Current, 3.3V supply, Total 270 Mbps ICC www.national.com Reference Min Max Units Logic level inputs 2 VCC V VEE 0.8 V 47 65 µA −18 −25 µA All logic level outputs SDI SDO, SCO Typ 2 V VEE + 0.6 V 200 1600 mVP-P VEE+1.2 VCC−0.2 V 880 mVP-P 720 800 VCC− VSDOD 100 4 V mA Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 3) Symbol Parameter Conditions Reference BRSD Serial Data Rate SMPTE 259M-C SDI, SDO TOLJIT Serial Input Jitter Tolerance 270 Mbps, (Note 7, Note 8, Note 9) SDI TOLJIT Serial Input Jitter Tolerance 270 Mbps, (Note 7, Note 8, Note 10) Serial Data Output Jitter 270 Mbps, (Note 8, Note 11) Loop Bandwidth 270 Mbps, <0.1dB Peaking FCO Serial Clock Output Frequency 270 Mbps data rate tJIT Serial Clock Output Jitter tJIT BWLOOP Min Typ >0.6 UIP-P 0.02 SCO 0.08 UIP-P 300 kHz 270 MHz 3 psRMS 40 60 % 45 55 % 15 ms 2 Serial Clock Output Duty Cycle Mbps UIP-P SCO SDO, SCO Units >6 SDO Serial Clock Output Alignment with respect to Data Interval Max 270 TACQ Acquisition Time (Note 4, Note 6) tr, tf Input rise/fall time 10%–90% Logic inputs tr, tf Input rise/fall time 20%–80% SDI tr, tf Output rise/fall time 10%–90% Logic outputs tr, tf Output rise/fall time 20%–80%, (Note 5) SDO, SCO FREF Reference Clock Frequency 27 MHz FTOL Reference Clock Frequency Tolerance ±50 ppm 1.5 3 ns 1500 ps 1.5 3 ns 90 130 ps Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts). Note 3: Typical values are stated for: VCC = +3.3V, TA = +25°C. Note 4: Specification is guaranteed by design. Note 5: RL = 100Ω differential. Note 6: Measured from first SDI transition until Lock Detect (LD) output goes high (true). Note 7: Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. Note 8: This parameter is guaranteed by characterization over voltage and temperature limits. Note 9: Refer to “A1” in Figure 1 of SMPTE RP 184-1996. Note 10: Refer to “A2” in Figure 1 of SMPTE RP 184-1996. Note 11: Serial Data Output Jitter is total output jitter with 0.2 UIP-P input jitter. 5 www.national.com LMH0026 AC Electrical Characteristics LMH0026 compatible. The input is intended to be DC interfaced to devices such as the LMH0074 adaptive cable equalizer. The input is not internally terminated or biased. The input may be AC-coupled if a suitable input bias voltage is provided. Figure 1 shows the equivalent input circuit for SDI and SDI. The LMH0026 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0001 or LMH0002 cable driver. Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial datarate clock output. Figure 2 shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2. The SCO_EN input controls the operating mode for the SCO/ SDO2 output. When the SCO_EN input is high the SCO/ SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the OUTPUT MUTE input is a logic low level. SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are suitable for driving AC or DCcoupled, 100Ω center-tapped, AC grounded or 100Ω uncenter-tapped, differentially terminated networks. Device Description The LMH0026 SD SDI Reclocker is used in many types of digital video signal processing equipment. The LMH0026 supports the SMPTE 259M (C) serial digital video standard, with a corresponding serial data rate of 270 Mbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0026 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial data-rate clock or second serial data output select, SD indicator output, lock detect output, auto/manual data bypass, and output mute. Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω differential loads. The differential output level is 800 mVP-P ±10% into 100Ω AC or DC-coupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is an e-TSSOP20 with an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the negative electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differential serial data input, SDI, accepts 270 Mbps serial digital video data. The serial data input is differential LVPECL 30001808 FIGURE 1. Equivalent SDI input Circuit (SDI, SDI) www.national.com 6 LMH0026 30001809 FIGURE 2. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2) to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being received. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 1. SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 10% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. If an unsupported data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the output is invalid. OUTPUT MUTE The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to LD, then the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see Table 1. OUTPUT MUTE has an internal pull-up device to enable the output by default. BYPASS/AUTO BYPASS The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 1. BYPASS/AUTO BYPASS has an internal pull-down device. Control Inputs and Indicator Outputs LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be connected TABLE 1. Control Functionality LOCK DETECT OUTPUT MUTE BYPASS/AUTO BYPASS DEVICE STATUS 0 1 X PLL unlocked, reclocker bypassed 1 1 0 PLL locked to supported data rate, reclocker not bypassed X 0 X Outputs muted 0 LOCK DETECT X Outputs muted 1 LOCK DETECT 0 PLL locked to supported data rate, reclocker not bypassed is locked and the Lock Detect output is high. When the PLL is not locked (the Lock Detect output is low), the SD output defaults to low. The SD output is undefined for a short time after lock detect assertion or de-assertion due to a data change on SDI. See Figure 3 for a timing diagram showing the relationship between SDI, Lock Detect, and SD. SD The SD output indicates that the LMH0026 is locked and processing SD data rates. It may be used to control another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270 Mbps. The SD output is a registered function and is only valid when the PLL 7 www.national.com LMH0026 30001805 FIGURE 3. SDI, Lock Detect, and SD Timing SCO_EN Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output. TABLE 2. Crystal Parameters Parameter CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0026 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins. Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a suitable crystal are given in Table 2. www.national.com 8 Value Frequency 27 MHz Frequency Stability ±50 ppm @ recommended drive level Operating Mode Fundamental mode, Parallel Resonant Load Capacitance 20 pF Shunt Capacitance 7 pF Series Resistance 40Ω max. Recommended Drive Level 100 µW Maximum Drive Level 500 µW Operating Temperature Range −10°C to +60°C LMH0026 Application Information Figure 4 shows an application circuit for the LMH0026 along with the LMH0074 SMPTE 259M / 344M Adaptive Cable Equalizer and LMH0001 SMPTE 259M / 344M Cable Driver. 30001804 FIGURE 4. Application Circuit The LMH0026 inputs are LVPECL compatible. The LMH0026 has a wide input common mode range and in most cases the input should be DC coupled. For DC coupling, the inputs must be kept within the common mode range specified in DC Electrical Characteristics. Figure 4 shows an example of a DC coupled interface between the LMH0074 cable equalizer and the LMH0026. The LMH0074 output common mode voltage and voltage swing are within the range of the input common mode voltage and voltage swing of the LMH0026. All that is required is a 100Ω differential termination as shown. The resistor should be placed as close to the LMH0026 input as possible. If desired, this network may be terminated with two 50Ω resisters and a center tap capacitor to ground in place of the single 100Ω resistor. The LMH0026 outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second output that may be set as the serial clock or a second data output. Both outputs are always active. The LMH0026 output should be 9 www.national.com LMH0026 DC coupled to the input of the receiving device as long as the common mode ranges of both devices are compatible. Figure 4 shows an example of a DC coupled interface between the LMH0026 and LMH0001 cable driver. All that is required is a 100Ω differential termination as shown. The resistor should be placed as close to the LMH0001 input as possible. If desired, this network may be terminated with two 50Ω resisters and a center tap capacitor to ground in place of the single 100Ω resistor. The external loop filter capacitor (between LF1 and LF2) should be 56 nF. This is the only supported value; the loop filter capacitor should not be changed. BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be pulled high to force the LMH0026 to bypass all data. OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the outputs. The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal should www.national.com match the parameters described in Table 2. Alternately, a 27MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is locked. The SD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0002) in order to properly set the cable driver’s edge rate for SMPTE compliance. It defaults to low when the LMH0026 is not locked. SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled high to set the second output as a serial clock. The ground connection for the LMH0026 is through the large exposed DAP. The DAP must be connected to ground for proper operation of the LMH0026. 10 LMH0026 Physical Dimensions inches (millimeters) unless otherwise noted 20-Pin TSSOP Order Number LMH0026MH NS Package Number MXA20A 11 www.national.com LMH0026 SD SDI Reclocker with Dual Differential Outputs Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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