IRF IRLMS1902

PD - 91540C
IRLMS1902
HEXFET® Power MOSFET
l
l
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Generation V Technology
Micro6 Package Style
Ultra Low RDS(on)
N-Channel MOSFET
Description
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET® power MOSFETs are well known for,
provides the designer with an extremely efficient and
reliable device for use in a wide variety of applications.
A
D
D
1
6
D
2
5
D
G
3
4
S
VDSS = 20V
RDS(on) = 0.10Ω
Top View
The Micro6 package with its customized leadframe
produces a HEXFET® power MOSFET with RDS(on)
60% less than a similar size SOT-23. This package is
ideal for applications where printed circuit board space
is at a premium. It's unique thermal design and RDS(on)
reduction enables a current-handling increase of nearly
300% compared to the SOT-23.
Micro6
Absolute Maximum Ratings
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
VGS
dv/dt
TJ, TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 4.5V
Continuous Drain Current, VGS @ 4.5V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ‚
Junction and Storage Temperature Range
3.2
2.6
18
1.7
13
± 12
5.0
-55 to + 150
Units
A
W
mW/°C
V
V/ns
°C
Thermal Resistance Ratings
Parameter
RθJA
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Maximum Junction-to-Ambient „
Min.
Typ.
Max
Units
–––
–––
75
°C/W
1
3/18/04
IRLMS1902
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
IGSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
Conditions
20 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.032 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 0.10
VGS = 4.5V, ID = 2.2A ƒ
Ω
––– ––– 0.17
VGS = 2.7V, ID = 1.1A ƒ
0.70 ––– –––
V
VDS = VGS, ID = 250µA
3.2 ––– –––
S
VDS = 10V, ID = 1.1A
––– ––– 1.0
VDS = 16V, VGS = 0V
µA
––– ––– 25
VDS = 16V, VGS = 0V, TJ = 125°C
––– ––– 100
VGS = 12V
nA
––– ––– -100
VGS = -12V
––– 4.7 7.0
ID = 2.2A
––– 0.97 1.5
nC VDS = 16V
––– 1.8 2.6
VGS = 4.5V, See Fig. 6 and 9 ƒ
––– 7.0 –––
VDD = 10V
––– 11 –––
ID = 2.2A
ns
––– 12 –––
RG = 6.0Ω
––– 4.0 –––
RD = 4.4Ω, See Fig. 10 ƒ
––– 300 –––
VGS = 0V
––– 120 –––
pF
VDS = 15V
––– 50 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
1.7
–––
–––
18
–––
–––
–––
–––
40
37
1.2
60
55
A
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 2.2A, VGS = 0V ‚
TJ = 25°C, IF = 2.2A
di/dt = 100A/µs ‚
D
S
Notes:
 Repetitive rating; pulse width limited by
ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.
‚ ISD ≤ 2.2A, di/dt ≤ 110A/µs, VDD ≤ V(BR)DSS,
„ Surface mounted on FR-4 board, t ≤ 5sec.
max. junction temperature. ( See fig. 11 )
TJ ≤ 150°C
2
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IRLMS1902
100
100
VGS
7.50V
5.00V
4.00V
3.50V
3.00V
2.50V
2.00V
BOTTOM 1.75V
10
1
20µs PULSE WIDTH
TJ = 25 °C
1.75V
0.1
0.1
1
10
1
1.75V
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
2.0
TJ = 25 ° C
TJ = 150 ° C
1
V DS = 10V
20µs PULSE WIDTH
2.5
3.0
3.5
4.0
4.5
5.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
Fig 2. Typical Output Characteristics
100
2.0
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
20µs PULSE WIDTH
TJ = 150 °C
0.1
0.1
10
VDS , Drain-to-Source Voltage (V)
0.1
1.5
VGS
7.50V
5.00V
4.00V
3.50V
3.00V
2.50V
2.00V
BOTTOM 1.75V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
ID = 2.2A
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 4.5V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRLMS1902
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
500
400
Ciss
300
200
Coss
100
Crss
10
VGS , Gate-to-Source Voltage (V)
600
0
1
10
ID = 2.2A
VDS = 16V
8
6
4
2
FOR TEST CIRCUIT
SEE FIGURE 9
0
100
0
2
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
6
8
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
4
QG , Total Gate Charge (nC)
10
TJ = 150 ° C
TJ = 25 ° C
1
0.1
0.4
V GS = 0 V
0.6
0.8
1.0
1.2
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1.4
10
100us
1ms
1
10ms
TC = 25 ° C
TJ = 150 ° C
Single Pulse
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLMS1902
4.5V
QGS
RD
VDS
QG
VGS
QGD
D.U.T.
RG
+
- VDD
VG
4.5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Charge
Fig 9a. Basic Gate Charge Waveform
Fig 10a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
VDS
90%
50KΩ
.2µF
12V
.3µF
D.U.T.
+
V
- DS
10%
VGS
VGS
td(on)
3mA
IG
tr
t d(off)
tf
ID
Current Sampling Resistors
Fig 9b. Gate Charge Test Circuit
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJA )
D = 0.50
0.20
10
0.10
0.05
0.02
PDM
0.01
1
t1
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.00001
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJA + TA
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRLMS1902
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 12. For N-channel HEXFET® power MOSFETs
6
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IRLMS1902
Package Outline
Micro6ä
3.00 (.118 )
2.80 (.111 )
1.75 (.068 )
1.50 (.060 )
-A-
6
1
5
2
LEAD ASSIGNMENTS
4
3.00 (.118 )
2.60 (.103 )
3
0.95 ( .0375 )
6X
2X
RECOMMENDED FOOTPRINT
-B2X 0.95 (.0375 )
S
D
D
6
5
4
1
2
3
D
D
G
6X (1.06 (.042 )
2.20 (.087 )
0.50 (.019 )
0.35 (.014 )
6X 0.65 (.025 )
0.15 (.006 ) M C A S B S
O
O
0 -10
1.30 (.051 )
0.90 (.036 )
6X
1.45 (.057 )
0.90 (.036 )
-C-
0.10 (.004 )
6 SURFACES
0.15 (.006 )
MAX.
0.20 (.007 )
0.09 (.004 )
0.60 (.023 )
0.10 (.004 )
NOTES :
1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1982.
2. CONTROLLING DIMENSION : MILLIMETER.
3. DIMENSIONS ARE SHOW N IN MILLIMETERS (INCHES).
Part Marking Information
Micro6ä
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IRLMS1902
Tape & Reel Information
Micro6ä
8mm
FEED DIRECTION
4mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
178.00
( 7.008 )
MAX.
9.90 ( .390 )
8.40 ( .331 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/04
8
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