White Electronic Designs WV3EG6434S-BD4 ADVANCED* 256MB – 32Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DESCRIPTION The WV3EG6434S is a 32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of eight 32Mx8 DDR SDRAMs in BGA package mounted on a 200 Pin FR4 substrate. DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: 2.5V ± 0.20V Standard 200 pin SO-DIMM package Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. • Package height options: BD4: 31.75mm (1.25") NOTE: Consult factory for availability of: • Lead-Free or RoHS Products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 Clock Speed 166MHz 133MHz 133MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2.5-3-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED PIN CONFIGURATIONS PIN NAMES Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 51 VSS 101 A9 151 DQ42 2 VREF 52 VSS 102 A8 152 DQ46 3 VSS 53 DQ19 103 VSS 153 DQ43 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC *CK1# 8 DQ5 58 VCC 108 A4 158 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 *CK1 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 15 VSS 65 DQ26 115 A10/AP 165 DQ49 16 VSS 66 DQ30 116 BA1 166 DQ53 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC DQS6 19 DQ8 69 VCC 119 WE# 169 20 DQ12 70 VCC 120 CAS# 170 DM6 21 VCC 71 NC 121 CS0 171 DQ50 22 VCC 72 NC 122 *CS1# 172 DQ54 23 DQ9 73 NC 123 NC 173 VSS 24 DQ13 74 NC 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 *DQS8 127 DQ32 177 DQ56 28 VSS 78 *DM8 128 DQ36 178 DQ60 29 DQ10 79 NC 129 DQ33 179 VCC 30 DQ14 80 NC 130 DQ37 180 VCC DQ57 31 DQ11 81 VCC 131 VCC 181 32 DQ15 82 VCC 132 VCC 182 DQ61 33 VCC 83 NC 133 DQS4 183 DQS7 34 VCC 84 NC 134 DM4 184 DM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 *CK2 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 *CK2# 141 DQ40 191 VCC 42 DQ20 92 VCC 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 *CKE1 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 A12 149 VSS 199 NC 50 DQ22 100 A11 150 VSS 200 NC A0 – A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0 CK0# CKE0 CS0# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock input Clock input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect * These pins are not used in this module. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED FUNCTIONAL BLOCK DIAGRAM S0# CKE0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 BA0 - BA1 A0 - A12 S0# S1# S0# S1# CAS# CAS#: SDRAMs VCCSPD DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S0# S1# S0# S1# Serial PD BA0-BA1: DDR SDRAMs RAS#: SDRAMs VCC/VCCQ DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 SCL A0-A12: DDR SDRAMs RAS# WE# DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 SDA WP A0 A1 A2 SA0 SA1 SA2 WE#: SDRAMs SPD DDR SDRAM CK0 PLL CK0# VREF DDR SDRAM VSS DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM NOTE: All resistor values are 22 ohms unless otherwise specified. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 8 50 Units V V °C W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS TA = 0°C to 70°C Parameter Supply voltage(for device with a nominal VCC of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK# inputs Input Differential Voltage, CK and CK# inputs Input crossing point voltage, CK and CK# inputs Input leakage current Output leakage current Output High Current(Normal strengh driver); VOUT = VTT + 0.84V Output High Current(Normal strengh driver); VOUT = VTT - 0.84V Output High Current(Half strengh driver); VOUT = VTT + 0.45V Output High Current(Half strengh driver); VOUT = VTT - 0.45V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 VCCQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 VCCQ/2+50mV VREF+0.04 VCCQ+0.3 VREF-0.15 VCCQ+0.3 VCCQ+0.6 1.35 2 5 Unit V V V V V V V V V uA uA mA mA mA mA Note 1 2 4 4 3 5 Notes: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the dc level of the same. CAPACITANCE TA = 25°C, f = 1MHz, VCC = 2.5V, VREF =2.5V ± 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CK0,CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 21 21 21 3 12 10 21 10 Unit pF pF pF pF pF pF pF pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V Parameter Symbol Conditions DDR333@ CL=2.5 DDR266@ CL=2 DDR266@ CL=2.5 Max Max Max Units 720 640 640 mA Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 840 840 mA IDD1 One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN );tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. 920 Operating Current Precharge Power-Down Standby Current IDD2P All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) 24 24 24 mA 200 200 mA IDD2F CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. 240 Idle Standby Current 185 185 mA IDD2Q CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with keeping >= VIH(min) or = < VIL(max); VIN = VREF for DQ, DQS and DM 200 Precharge Quiet Standby Current Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; tCK(MIN); CKE=(low) 280 240 240 mA 440 360 360 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 1120 1120 mA IDD4R Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. 1280 Operating Current 1280 1080 1080 mA IDD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. Auto Refresh Current IDD5 tRC=tRC(MIN) 1360 1280 1280 mA Self Refresh Current IDD6 CKE ≤ 0.2V 24 24 24 mA 2080 2080 mA IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. 2240 Operating Current Operating Current Note: IDD speicification is based on Samsung components. Other DRAM manufacturers specification may be different. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : VCC=2.5V, T=25°C 1. Typical Case : VCC=2.5V, T=25°C 2. Worst Case : VCC=2.7V, T=10°C 2. Worst Case : VCC=2.7V, T=10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns : 4. Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 0°C ≤ TA ≤ 70°C, VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V Parameter Symbol Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD CL=2.0 CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK# Output data access time from CK/CK# Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time (fast) Address and Control Input hold time (fast) Address and Control Input setup time (slow) Address and Control Input hold time (slow) Data-out high impedence time from CK/CK# Data-out low impedence time from CK/CK# Input Slew Rate (for input only pins) Input Slew Rate (for I/O pins) Output Slew Rate (x4,x8) Output Slew Rate Matching Ratio (rise to fall) tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR 335 Min 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 262 Max 70K 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 1.1 +0.7 +0.7 4.5 1.5 Min 65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 265 Max 120K 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 1.1 +0.75 +0.75 4.5 1.5 Min 65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 Max 120K 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 1.1 +0.75 +0.75 4.5 1.5 Unit ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ns V/ns V/ns Note 5 5 5 2 6 6 6 6 6 7 Note: AC Timing Parameters are based on Samsung components. Other DRAM Manufacturers parameters may be different. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) 0°C ≤ TA ≤ 70°C, VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V Parameter Symbol Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH Clock half period tHP Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time 1. 2. 3. 4. 5. 6. tQHS tWPST tRAP tDAL 335 Min 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) 262 Max — — 0.55 0.6 Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 20 (tWR/tCK) + (tRP/tCK) 265 Max — — 0.75 0.6 Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 20 (tWR/tCK) + (tRP/tCK) Max Unit — ns ns ns ns ns ns ns tCK us ns — ns 0.75 0.6 ns tCK Note 7 7 4 1 5 3 tCK Maximum burst refresh cycle : 8 The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. A write command can be applied with tRCD satisfied after this command. For registered DIMMs, tCL and tCH are >_ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 ∆tIS (ps) 0 +50 +100 ∆tIH (ps) 0 +50 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 ∆tDS (ps) 0 +75 +150 ∆tDH (ps) 0 +75 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED ORDERING INFORMATION FOR BD4 Part Number Speed CAS Latency tRCD tRP Height* WV3EG6434S335BD4 166MHz/333Mb/s 2.5 3 3 31.75 (1.25") WV3EG6434S262BD4 133MHz/266Mb/s 2 2 2 31.75 (1.25") WV3EG6434S265BD4 133MHz/266Mb/s 2.5 3 3 31.75 (1.25") NOTES: • Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free, G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR BD4 67.56 (2.66) 63.60 (2.50) 4.00 ±0.10 (0.16 ±0.039) 31.75 (1.25) 20.00 (0.79) 6.00 (0.24) 1 2.15 (0.086) 2.54 (0 .100) MAX. Full R 2X 39 41 11.40 (0.456) 199 4.20 (0.17) 47.40 (1.896) 2- 1.80 (0.07) 3.98 (0.157) MIN. 1.0 ± 0.1 (0.039 ± 0.004) 2.40 (0.096) 1.80 (0.07) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) TOLERANCES: ± 0.15 (0.006) UNLESS OTHERWISE SPECIFIED White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED Document Title 256MB – 32Mx64 DDR SDRAM UNBUFFERED, w/PLL Revision History Rev # History Release Date Status Rev 0 Created 4-05 Advanced White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com