W3EG128M72ETSU-D3 -JD3 -AJD3 White Electronic Designs ADVANCED* 1GB – 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 The W3EG128M72ETSU is a 128Mx72 Double Data Rate SDRAM memory module based on 1Gb DDR SDRAM components. The module consists of nine 128Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. • JEDEC design specification Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. • VCC = VCCQ = +2.5V ± 0.2V (100, 133 and 166MHz) • VCC = VCCQ = +2.6V ± 0.1V (200MHz) JEDEC standard 184 pin DIMM package • Package height options: JD3: 30.48 mm (1.20”) AJD3: 28.70 mm (1.13”) NOTE: Consult factory for availability of: • Lead-free products • Vendor source control option • Industrial temperature option OPERATING FREQUENCIES DDR400@CL=3 DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2 Clock Speed 200MHz 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 3-3-3 2.5-3-3 2-2-2 2.5-3-3 2-2-2 January 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED PIN CONFIGURATION PIN NAMES PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VCCQ NC NC VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS NC NC VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ4 DQ5 VCCQ DQS9 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DQS10 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 A12 VSS DQ21 A11 DQS11 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 VSS DQS17 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# CS1# DQS14 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DQS15 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD January 2005 Rev. 0 A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS17 CK0 CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC RESET# 2 Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect Reset Enable White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG128M72ETSU-D3 -JD3 -AJD3 White Electronic Designs ADVANCED FUNCTIONAL BLOCK DIAGRAM S0# DQS0 DQS4 DM0 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DM1 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS2 DQS6 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS3 120 CK0 CK0# DDR SDRAM DQS7 DM3 120 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS8 CK1 CK1# DDR SDRAM 120 CK2 CK2# DDR SDRAM SERIAL PD DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0, BA1 A0-A12 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ SCL WP SA0 SA1 SA2 VCC 120 CK0 CK0A CK0# CK0A# FREQ_SEL PLL BA0, BA1: DDR SDRAMs SDA A0 A1 A2 DDR SDRAM VCCSPD SPD/EEPROM VCC DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS A0-A12: DDR SDRAMs RAS# RAS#: DDR SDRAMs CAS# CAS#: DDR SDRAMs CKE0 CKE0: DDR SDRAMs WE# WE#: DDR SDRAMs NOTE: All resistor values are 22 ohms unless otherwise specified January 2005 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG128M72ETSU-D3 -JD3 -AJD3 White Electronic Designs ADVANCED ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT – 0.5 ~ 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ –1.0 ~ 3.6 V TSTG – 55 ~ +150 °C Storage Temperature Power Dissipation PD 9 W Short Circuit Current IOS 50 mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V (100, 133 and 166MHz), VCCQ = 2.6V ± 0.1V (200MHz) Parameter Symbol Min Max Unit Supply Voltage VCC 2.3 2.7 V Supply Voltage VCCQ 2.3 2.7 V Reference Voltage VREF 1.15 1.35 V Termination Voltage VTT 1.15 1.35 V Input High Voltage VIH VREF + 0.15 VCCQ + 0.3 V Input Low Voltage VIL – 0.3 VREF – 0.15 V Output High Voltage VOH VTT + 0.76 — V Output Low Voltage VOL — VTT – 0.76 V CAPACITANCE TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V (100, 133 and 166MHz), VCCQ = 2.6V ± 0.1V (200MHz) Parameter Symbol Max Unit Input Capacitance (A0-A12) CIN1 29 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 29 pF Input Capacitance (CKE0,CKE1) CIN3 29 pF Input Capacitance (CK0,CK0#) CIN4 5.5 pF Input Capacitance (CS0#,CS1#) CIN5 29 pF Input Capacitance (DQM0-DQM8) CIN6 8 pF Input Capacitance (BA0-BA1) CIN7 29 pF Data input/output Capacitance (DQ0-DQ63)(DQS) COUT 8 pF Data input/output Capacitance (CB0-CB7) COUT 8 pF January 2005 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V ± 0.1V (200MHz) Parameter Symbol Conditions DDR400@ CL=3 DDR333@ CL=2.5 DDR266@ CL=2, 2.5 DDR200@ CL=2 Max Max Max Max Units Operating Current IDD0 One device bank; Active - Precharge; (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. TRC=TRC(MIN); TCK=TCK TBD TBD TBD TBD mA Operating Current IDD1 One device bank; ActiveRead-Precharge; Burst = 2; TRC=TRC(MIN);TCK=TCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. TBD TBD TBD TBD mA Precharge PowerDown Standby Current IDD2P All device banks idle; Power-down mode; TCK=TCK(MIN); CKE=(low) TBD TBD TBD TBD mA Idle Standby Current IDD2F CS# = High; All device banks idle; TCK=TCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. TBD TBD TBD TBD mA Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; TCK(MIN); CKE=(low) TBD TBD TBD TBD mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; TRC=TRAS(MAX); TCK=TCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. TBD TBD TBD TBD mA Operating Current IDD4R Burst = 2; Reads; Continous burst; One device bank active;Address andcontrol inputs changing once per clock cycle; TCK=TCK(MIN); IOUT = 0mA. TBD TBD TBD TBD mA Operating Current IDD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK=TCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. TBD TBD TBD TBD mA Auto Refresh Current IDD5 TRC=TRC(MIN) TBD TBD TBD TBD mA Self Refresh Current IDD6 CKE ≤ 0.2V TBD TBD TBD TBD mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with TRC=TRC (MIN); TCK=TCK(MIN); Address and control inputs change only during Active Read or Write commands TBD TBD TBD TBD mA January 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : VCC=2.5V, T=25°C 1. Typical Case : VCC=2.5V, T=25°C 2. Worst Case : VCC=2.7V, T=10°C 2. Worst Case : VCC=2.7V, T=10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns : 4. Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRCD=15*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 January 2005 Rev. 0 6 • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG128M72ETSU-D3 -JD3 -AJD3 White Electronic Designs ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 3 CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (1 V/ns) Address and control input setup time (1 V/ns) Address and control input hold time (0.5 V/ns) Address and control input setup time (0.5 V/ns) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time January 2005 Rev. 0 403 SYMBOL tAC tCH tCL tCK (3) tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tIHS tISS tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES MIN -0.7 0.45 0.45 5 6 7.5 0.4 0.4 1.75 -0.6 0.35 0.35 335 MAX +0.7 0.55 0.55 7.5 13 13 262 265 MIN -0.8 0.45 0.45 8 10 0.45 0.5 0.6 0.45 0.5 0.6 1.75 1.75 2 -0.60 +0.60 -0.75 +0.75 +0.75 -0.8 0.35 0.35 0.35 0.35 0.35 0.35 0.45 0.5 0.5 +0.8 0.72 1.28 0.2 0.2 tCH,tCL +0.70 -0.70 0.6 0.6 0.6 0.6 2.20 2 tHP - tQHS 0.50 40 70,000 15 55 0.75 1.25 0.2 0.2 tCH,tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 tHP - tQHS 0.60 42 70,000 15 60 0.75 1.25 0.2 0.2 tCH,tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP - tQHS 0.75 40 120,000 15 60 0.75 1.25 0.2 0.2 tCH,tCL +0.75 -0.75 0.90 1.1 0.90 1 1 2.2 15 tHP - tQHS 0.75 40 120,000 20 65 0.75 1.25 tCK 0.2 tCK 0.2 tCK tCH,tCL ns +0.8 ns -0.8 ns ns 12 ns 1.1 ns 1.1 ns 1.1 ns 2.2 ns 16 ns tHP ns - tQHS 1 ns 40 120,000 ns 20 ns 70 ns 70 15 15 0.9 0.4 10 0.25 0 72 15 15 0.9 0.4 12 0.25 0 75 15 15 0.9 0.4 15 0.25 0 72 20 20 0.9 0.4 15 0.25 0 75 20 20 0.9 0.4 15 0.25 0 0.40 1.1 0.6 7 MAX MIN MAX MIN +0.7 -0.75 +0.75 -0.75 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 13 7.5 13 7.5 13 7.5 13 7.5/10 202 MAX 0.75 0.55 0.55 13 13 +0.6 MIN -0.7 0.45 0.45 6 7.5 1.1 0.6 1.1 0.6 1.1 0.6 MAX UNITS NOTES 0.8 ns 0.55 tCK 25 0.55 tCK 25 13 ns 38, 43 13 ns 38, 43 ns 37, 42 ns 22, 26 ns 22, 26 ns 26 ns tCK tCK 0.6 ns 22 1.1 0.6 ns ns ns tCK tCK ns tCK ns 29 16, 36 16, 36 12 12 12 12 22 30 41 36 36 17, 19 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG128M72ETSU-D3 -JD3 -AJD3 White Electronic Designs ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) DDR400: VCC = VCCQ = +2.6V ± 0.1V AC CHARACTERISTICS PARAMETER DQS write postamble Write recovery time 403 SYMBOL MIN tWPST 0.4 tWR 15 Internal WRITE to READ command delay tWTR Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VCC Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command na tREFC tREFI tVTD tXSNR tXSRD January 2005 Rev. 0 355 MAX 0.6 2 MIN 0.4 15 262 MAX 0.6 1 tQH - tDQSQ 70.3 7.8 0 75 200 8 MIN 0.4 15 MAX 0.6 1 tQH - tDQSQ 70.3 7.8 0 75 200 tQH - tDQSQ 70.3 7.8 0 75 200 265 MIN 0.4 15 MAX 0.6 1 tQH - tDQSQ 202 MIN 0.4 15 MAX UNITS NOTES 0.6 tCK 17 ns 1 tCK tQH - tDQSQ 70.3 7.8 0 75 200 70.3 7.8 0 80 200 ns µs µs ns ns tCK 22 21 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 17. The intent of the Don’t Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high [above VIHDC (MIN)] then it must not transition low (below VIHDC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be as-serted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window, shows derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For 403, slew rates must be ≥ 0.5 V/ns. 28. VCC must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V mini-mum, whichever is more positive. VTT Output (VOUT) 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 50Ω Reference Point 30pF AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL (AC) and VIH (AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 265, 335 and CL = 3 for 403 with the outputs open. Enables on-chip refresh and address counters. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 25°C, VOUT (DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For 403, slew rates must be 0.5 V/ns. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). January 2005 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED 40. Random addressing changing and 50 percent of data changing at every transfer. 41. Random addressing changing and 100 percent of data changing at every transfer. 42. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 43. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 44. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 45. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 47. The 403 speed grade will operate with tRAS (MIN) = 40 ns and tRAS (MAX) = 120,000ns at any slower frequency. 33. The voltage levels used are derived from a mini-mum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 34. VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. VCC and VCCQ must track each other. 36. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 37. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 38. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0V, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin. 39. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. January 2005 Rev. 0 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED ORDERING INFORMATION FOR JD3 Part Number W3EG128M72ETSU403JD3 W3EG128M72ETSU335JD3 W3EG128M72ETSU262JD3 W3EG128M72ETSU265JD3 W3EG128M72ETSU202JD3 Speed 200MHz/400Mbps, CL=3 166MHz/333Mbps, CL=2.5 133MHz/266Mbps, CL=2 133MHz/266Mbps, CL=2.5 100MHz/200Mbps, CL=2 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") Commercial Operating Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 2.54 (0.100 MAX) 3.99 (0.157 (2x)) 30.48 (1.20 MAX) 17.78 (0.700) 10.0 (0.394) 6.36 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050) (± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) January 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED ORDERING INFORMATION FOR AJD3 Part Number W3EG128M72ETSU403AJD3 W3EG128M72ETSU335AJD3 W3EG128M72ETSU262AJD3 W3EG128M72ETSU265AJD3 W3EG128M72ETSU202AJD3 Speed 200MHz/400Mbps, CL=3 166MHz/333Mbps, CL=2.5 133MHz/266Mbps, CL=2 133MHz/266Mbps, CL=2.5 100MHz/200Mbps, CL=2 Height* 28.70 (1.13") MAX 28.70 (1.13") MAX 28.70 (1.13") MAX 28.70 (1.13") MAX 28.70 (1.13") MAX Commercial Operating Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options PACKAGE DIMENSIONS FOR AJD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 2.54 (0.100 MAX) 3.99 (0.157 (2x)) 28.70 (1.13 MAX) 17.78 (0.700) 10.0 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050) (± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) January 2005 Rev. 0 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED ORDERING INFORMATION FOR D3 Part Number W3EG128M72ETSU403D3 W3EG128M72ETSU335D3 W3EG128M72ETSU262D3 W3EG128M72ETSU265D3 W3EG128M72ETSU202D3 Speed 200MHz/400Mbps, CL=3 166MHz/333Mbps, CL=2.5 133MHz/266Mbps, CL=2 133MHz/266Mbps, CL=2.5 100MHz/200Mbps, CL=2 Height* 28.58 (1.125") MAX 28.58 (1.125") MAX 28.58 (1.125") MAX 28.58 (1.125") MAX 28.58 (1.125") MAX Commercial Operating Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options PACKAGE DIMENSIONS FOR D3 Note: D3 Not Recommended For New Designs D E D N 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) E M M O 17.78 (0.700) 10.0 (0.394) T O 6.35 (0.250) C E R 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 2.54 (0.100 MAX) 28.58 (1.125 MAX) 1.27 (0.050 TYP.) 1.78 (0.070) 2.31 (0.091) 3.99 (2x) (0.157) (MIN) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050) (± 0.004) N * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) January 2005 Rev. 0 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED Document Title 1GB – 128Mx72, DDR, SDRAM Unbuffered ECC, w/PLL Revision History Rev # History Release Date Status Rev 0 Created 1-04-05 Advanced January 2005 Rev. 0 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com