WL CS P6 OL-IP3319CX6 Wafer level chip-size package; 6 bumps (2 x 3) 8 February 2016 Package information 1. Package summary Terminal position code B (bottom) Package type descriptive code WLCSP Package type industry code WLCSP Package style descriptive code UC (uncased chip) Package style suffix code NA (not applicable) Package body material type X (other) Mounting method type S (surface mount) Issue date 11-6-2013 Table 1. Package summary Symbol Parameter Min Typ Nom Max Unit D package length 0.9 - 0.95 1 mm E package width 1.29 - 1.34 1.39 mm A seated height 0.54 - 0.57 0.6 mm e nominal pitch - - 0.4 - mm n2 actual quantity of termination - - 6 - OL-IP3319CX6 NXP Semiconductors Wafer level chip-size package; 6 bumps (2 x 3) 2. Package outline WLCSP6: wafer level chip-size package; 6 bumps (2 x 3) IP3319CX6 bump A1 index area D A1 E A detail X e b C e e1 B A 1 2 X 0 1 mm scale Dimensions (mm are the original dimensions) Unit A max 0.60 nom 0.57 min 0.54 mm A1 b D E e e1 0.38 0.37 0.36 0.31 0.26 0.21 1.00 0.95 0.90 1.39 1.34 1.29 0.42 0.40 0.38 0.84 0.80 0.76 ip3319cx6_po Outline version References IEC JEDEC JEITA European projection Issue date 13-06-07 13-06-10 IP3319CX6 Fig. 1. Package outline WLCSP (OL-IP3319CX6) OL-IP3319CX6 Package information All information provided in this document is subject to legal disclaimers. 8 February 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2/4 OL-IP3319CX6 NXP Semiconductors Wafer level chip-size package; 6 bumps (2 x 3) 3. Legal information Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. OL-IP3319CX6 Package information All information provided in this document is subject to legal disclaimers. 8 February 2016 © NXP Semiconductors N.V. 2016. All rights reserved 3/4 OL-IP3319CX6 NXP Semiconductors Wafer level chip-size package; 6 bumps (2 x 3) 4. Contents 1. Package summary........................................................ 1 2. Package outline............................................................ 2 3. Legal information......................................................... 3 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 February 2016 OL-IP3319CX6 Package information All information provided in this document is subject to legal disclaimers. 8 February 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4/4