P4 2 CS WL SOT1459-2 wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.5 mm (backside coating included) 12 May 2016 Package information 1. Package summary Terminal position code B (bottom) Package type descriptive code WLCSP Package type industry code WLCSP42 Package style descriptive code WLCSP (wafer level chip-size package) Package style suffix code NA (not applicable) Mounting method type S (surface mount) Issue date 26-4-2016 Table 1. Package summary Symbol Parameter Min Typ Nom Max Unit D package length 3.1 - 3.13 3.16 mm E package width 2.43 - 2.46 2.49 mm A seated height 0.46 - 0.5 0.54 mm A2 package height 0.275 - 0.3 0.325 mm e nominal pitch - - 0.4 - mm n2 actual quantity of termination - - 42 - SOT1459-2 NXP Semiconductors wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.5 mm (backside coating included) 2. Package outline WLCSP42: wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.50 mm ball A1 index area B E SOT1459-2 A A A2 D A1 detail X e1 C e ZD1 Øv Øw b G C A B C y e F E e2 D C B A ball A1 index area ZD2 1 2 3 4 5 6 ZE1 X ZE2 0 3 mm scale Dimensions (mm are the original dimensions) Unit mm A max 0.54 nom 0.50 min 0.46 A1 A2 0.23 0.20 0.17 0.325 0.300 0.275 b D E 0.29 3.16 2.49 0.26 3.13 2.46 0.23 3.10 2.43 e e1 e2 0.4 2.0 2.4 ZD1 ZD2 ZE1 0.365 0.365 0.245 ZE2 0.215 v w y 0.05 0.02 0.03 sot1459-2_po Outline version SOT1459-2 References IEC JEDEC JEITA European projection Issue date 16-02-25 16-03-01 --- Fig. 1. Package outline WLCSP42 (SOT1459-2) SOT1459-2 Package information All information provided in this document is subject to legal disclaimers. 12 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2/4 SOT1459-2 NXP Semiconductors wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.5 mm (backside coating included) 3. Legal information Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. SOT1459-2 Package information All information provided in this document is subject to legal disclaimers. 12 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved 3/4 SOT1459-2 NXP Semiconductors wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.5 mm (backside coating included) 4. Contents 1. Package summary........................................................ 1 2. Package outline............................................................ 2 3. Legal information......................................................... 3 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 May 2016 SOT1459-2 Package information All information provided in this document is subject to legal disclaimers. 12 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4/4