ATMEL AT90S8515-8PC

Features
• AVR - High Performance and Low Power RISC Architecture
• 118 Powerful Instructions - Most Single Clock Cycle Execution
• 8K bytes of In-System Reprogrammable Flash
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– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
512 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
512 bytes Internal SRAM
32 x 8 General Purpose Working Registers
32 Programmable I/O Lines
Programmable Serial UART
SPI Serial Interface
VCC: 2.7 - 6.0V
Fully Static Operation
– 0 - 8 MHz 4.0 - 6.0V,
– 0 - 4 MHz 2.7 - 4.0V
Up to 8 MIPS Throughput at 8 MHz
One 8-Bit Timer/Counter with Separate Prescaler
One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
Dual PWM
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Programming Lock for Software Security
Description
8-Bit
Microcontroller
with 8K bytes
In-System
Programmable
Flash
AT90S8515
Preliminary
The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR ®
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
(continued)
Pin Configurations
Rev. 0841D–06/98
1
Block Diagram
Figure 1. The AT90S8515 Block Diagram
The AT90S8515 provides the following features: 8K bytes
of In-System Programmable Flash, 512 bytes EEPROM,
512 bytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
2
AT90S8515
The device is manufactured using Atmel’s high density
non-volatile memory technology. The on-chip in-system
programmable Flash allows the program memory to be
reprogrammed in-system through an SPI serial interface or
by a conventional nonvolatile memory programmer. By
combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S8515 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The AT90S8515 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators, and evaluation kits.
AT90S8515
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data input/output
when using external SRAM.
ALE
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
first access cycle, and the AD0-7 pins are used for data
during the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2. Oscillator Connections
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features
of the AT90S8515 as listed on page 46.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port C also serves as Address output when using external
SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features
of the AT90S8515 as listed on page 52.
Figure 3. External Clock Drive Configuration
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP
ICP is the input pin for the Timer/Counter1 Input Capture
function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output
CompareB function
3
AT90S8515 Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect
address register pointers for Data Space addressing enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 4. The AT90S8515 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S8515 AVR Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 $1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
4
AT90S8515
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is
pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system programmable Flash
memory.
With the relative jump and call instructions, the whole 4K
address space is directly accessed. Most AVR instructions
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
AT90S8515
ize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 512 bytes data SRAM can be easily accessed through
the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector position. The lower the interrupt vector address the higher the
priority.
Figure 5. Memory Maps
The General Purpose Register File
Figure 6 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
$00
R1
$01
R2
$02
…
R13
$0D
General
R14
$0E
Purpose
R15
$0F
Working
R16
$10
Registers
R17
$11
…
R26
$1A
X-register low byte
R27
$1B
X-register high byte
R28
$1C
Y-register low byte
R29
$1D
Y-register high byte
R30
$1E
Z-register low byte
R31
$1F
Z-register high byte
All the register operating instructions in the instruction set
have direct and single cycle access to all registers. The
only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a
constant and a register and the LDI instruction for load
immediate constant data. These instructions apply to the
second half of the registers in the register file - R16..R31.
The general SBC, SUB, CP, AND and OR and all other
operations between two registers or on a single register
apply to the entire register file.
As shown in Figure 6, each register is also assigned a data
memory address, mapping them directly into the first 32
locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers,
as the X,Y and Z registers can be set to index any register
in the file.
5
The X-Register, Y-Register And Z-Register
The registers R26..R31 have some added functions to their
general purpose usage. These registers are address point-
ers for indirect addressing of the Data Space. The three
indirect address registers X, Y and Z are defined as:
Figure 7. The X, Y and Z Registers
15
X - register
0
7
0
7
R27 ($1B)
0
R26 ($1A)
15
Y - register
0
7
0
7
R29 ($1D)
0
R28 ($1C)
15
Z - register
0
7
0
R31 ($1F)
In the different addressing modes these address registers
have functions as fixed displacement, automatic increment
and decrement (see the descriptions for the different
instructions).
The ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations
are divided into three main categories - arithmetic, logical
and bit-functions.
The In-System Programmable Flash Program
Memory
The AT90S8515 contains 8K bytes on-chip In-System Programmable Flash memory for program storage. Since all
6
AT90S8515
7
0
R30 ($1E)
instructions are 16-or 32-bit words, the Flash is organized
as 4K x 16. The Flash memory has an endurance of at
least 1000 write/erase cycles. The AT90S8515 Program
Counter (PC) is 12 bits wide, thus addressing the 4096 program memory addresses.
See page 62 for a detailed description on Flash data downloading.
Constant tables must be allocated within the address 0-4K
(see the LPM - Load Program Memory instruction description).
See page 8 for the different program memory addressing
modes.
AT90S8515
The SRAM Data Memory - Internal and External
The following figure shows how the AT90S8515 SRAM
Memory is organized:
Figure 8. SRAM Organization
Register File
Data Address Space
R0
$0000
R1
$0001
R2
$0002
…
…
R29
$001D
R30
$001E
R31
$001F
I/O Registers
$00
$0020
$01
$0021
$02
$0022
…
…
$3D
$005D
$3E
$005E
$3F
$005F
Internal SRAM
$0060
$0061
…
$025E
$025F
External SRAM
$0260
$0261
…
$FFFE
$FFFF
The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The
first 96 locations address the Register File + I/O Memory,
and the next 512 locations address the internal data
SRAM. An optional external data SRAM can be placed in
the same SRAM memory space. This SRAM will occupy
the location following the internal SRAM and up to as much
as 64K - 1, depending on SRAM size.
When the addresses accessing the data memory space
exceeds the internal data SRAM locations, the external
data SRAM is accessed using the same instructions as for
the internal data SRAM access. When the internal data
space is accessed, the read and write strobe pins (RD and
WR) are inactive during the whole access cycle. External
SRAM operation is enabled by setting the SRE bit in the
MCUCR register. See page 21 for details.
Accessing external SRAM takes one additional clock cycle
per byte compared to access of the internal SRAM. This
means that the commands LD, ST, LDS, STS, PUSH and
POP take one additional clock cycle. If the stack is placed
in external SRAM, interrupts, subroutine calls and returns
take two clock cycles extra because the two-byte program
counter is pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is
used per byte. This has the following effect: Data transfer
instructions take two extra clock cycles, whereas interrupt,
subroutine calls and returns will need four clock cycles
more than specified in the instruction set manual.
The five different addressing modes for the data memory
cover: Direct, Indirect with Displacement, Indirect, Indirect
with Pre-Decrement and Indirect with Post-Increment. In
the register file, registers R26 to R31 feature the indirect
addressing pointer registers.
7
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features a 63
address locations reach from the base address given by
the Y or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O registers,
the 512 bytes of internal data SRAM, and the 64K bytes of
optional external data SRAM in the AT90S8515 are all
accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
Operands are contained in register r (Rr) and d (Rd). The
result is stored in register d (Rd).
I/O Direct
Figure 11. I/O Direct Addressing
The Program and Data Addressing Modes
The AT90S8515 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access
to the program memory (Flash) and data memory (SRAM,
Register File and I/O Memory). This section describes the
different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of
the instruction word. To simplify, not all figures show the
exact location of the addressing bits.
Operand address is contained in 6 bits of the instruction
word. n is the destination or source register address.
Data Direct
Figure 12. Direct Data Addressing
Register Direct, Single Register RD
Figure 9. Direct Single Register Addressing
A 16-bit Data Address is contained in the 16 LSBs of a twoword instruction. Rd/Rr specify the destination or source
register.
Data Indirect With Displacement
The operand is contained in register d (Rd).
Figure 13. Data Indirect with Displacement
Register Direct, Two Registers RD AND RR
Figure 10. Direct Register Addressing, Two Registers
Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the
instruction word.
8
AT90S8515
AT90S8515
Data Indirect
Constant Addressing Using The LPM Instruction
Figure 14. Data Indirect Addressing
Figure 17. Code Memory Constant Addressing
Operand address is the contents of the X, Y or the Z-register.
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 4K) and LSB,
select low byte if cleared (LSB = 0) or high byte if set (LSB
= 1).
Data Indirect With Pre-Decrement
Figure 15. Data Indirect Addressing With Pre-Decrement
Indirect Program Addressing, IJMP and ICALL
Figure 18. Indirect Program Memory Addressing
The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the
X, Y or the Z-register.
Program execution continues at address contained by the
Z-register (i.e. the PC is loaded with the contents of the Zregister).
Data Indirect With Post-Increment
Relative Program Addressing, RJMP and RCALL
Figure 16. Data Indirect Addressing With Post-Increment
Figure 19. Relative Program Memory Addressing
The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Zregister prior to incrementing.
Program execution continues at address PC + k + 1. The
relative address k is -2048 to 2047.
9
The EEPROM Data Memory
The AT90S8515 contains 512 bytes of data EEPROM
memory. It is organized as a separate data space, in which
single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The
access between the EEPROM and the CPU is described
on page 32 specifying the EEPROM address registers, the
EEPROM data register, and the EEPROM control register.
For the SPI data downloading, see page 62 for a detailed
description.
Memory Access Times and Instruction
Execution Timing
This section describes the general access timing concepts
for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly
generated from the external clock crystal for the chip. No
internal clock division is used.
Figure 20 shows the parallel instruction fetches and
instruction executions enabled by the Harvard architecture
and the fast-access register file concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 20. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 21 shows the internal timing concept for the register
file. In a single clock cycle an ALU operation using two reg-
ister operands is executed, and the result is stored back to
the destination register.
Figure 21. Single Cycle ALU Operation
T1
T2
T3
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
10
AT90S8515
T4
AT90S8515
Figure 22. On-Chip Data SRAM Access Cycles
T1
T2
T3
T4
System Clock Ø
Address
Prev. Address
Address
Write
Data
WR
Read
Data
RD
The external data SRAM access is performed in two System Clock cycles as described in Figure 22.
Figure 23. External Data SRAM Memory Cycles without Wait State
T1
T2
T3
System Clock Ø
ALE
Data / Address [7..0]
Prev. Address
Prev. Address
Address
Address
Data
Write
Address [15..8]
Address
Data / Address [7..0]
Prev. Address
Address
Read
WR
Address
Data
RD
The external data SRAM memory access cycle with the Wait State bit enabled (Wait State active) is shown in Figure 24.
Figure 24. External Data SRAM Memory Cycles with Wait State
T1
T2
T3
T4
System Clock Ø
ALE
Prev. Address
Address
Address
Data
Addr.
Write
Data / Address [7..0]
Prev. Address
Addr.
Read
Address [15..8]
WR
Data / Address [7..0]
Prev. Address
Address
Data
RD
11
I/O Memory
The I/O space definition of the AT90S8515 is shown in the following table:
Table 1. AT90S8515 I/O Space
12
Address Hex
Name
Function
$3F ($5F)
SREG
Status Register
$3E ($5E)
SPH
Stack Pointer High
$3D ($5D)
SPL
Stack Pointer Low
$3B ($5B)
GIMSK
General Interrupt Mask register
$3A ($5A)
GIFR
General Interrupt Flag Register
$39 ($59)
TIMSK
Timer/Counter Interrupt Mask register
$38 ($58)
TIFR
Timer/Counter Interrupt Flag register
$35 ($55)
MCUCR
MCU general Control Register
$33 ($53)
TCCR0
Timer/Counter0 Control Register
$32 ($52)
TCNT0
Timer/Counter0 (8-bit)
$2F ($4F)
TCCR1A
Timer/Counter1 Control Register A
$2E ($4E)
TCCR1B
Timer/Counter1 Control Register B
$2D ($4D)
TCNT1H
Timer/Counter1 High Byte
$2C ($4C)
TCNT1L
Timer/Counter1 Low Byte
$2B ($4B)
OCR1AH
Timer/Counter1 Output Compare Register A High Byte
$2A ($4A)
OCR1AL
Timer/Counter1 Output Compare Register A Low Byte
$29 ($49)
OCR1BH
Timer/Counter1 Output Compare Register B High Byte
$28 ($48)
OCR1BL
Timer/Counter1 Output Compare Register B Low Byte
$25 ($45)
ICR1H
T/C 1 Input Capture Register High Byte
$24 ($44)
ICR1L
T/C 1 Input Capture Register Low Byte
$21 ($41)
WDTCR
Watchdog Timer Control Register
$1F ($3E)
EEARH
EEPROM Address Register High Byte
$1E ($3E)
EEARL
EEPROM Address Register Low Byte
$1D ($3D)
EEDR
EEPROM Data Register
$1C ($3C)
EECR
EEPROM Control Register
$1B ($3B)
PORTA
Data Register, Port A
$1A ($3A)
DDRA
Data Direction Register, Port A
$19 ($39)
PINA
Input Pins, Port A
$18 ($38)
PORTB
Data Register, Port B
$17 ($37)
DDRB
Data Direction Register, Port B
$16 ($36)
PINB
Input Pins, Port B
$15 ($35)
PORTC
Data Register, Port C
$14 ($34)
DDRC
Data Direction Register, Port C
$13 ($33)
PINC
Input Pins, Port C
AT90S8515
AT90S8515
Table 1. AT90S8515 I/O Space (Continued)
Note:
Address Hex
Name
Function
$12 ($32)
PORTD
Data Register, Port D
$11 ($31)
DDRD
Data Direction Register, Port D
$10 ($30)
PIND
Input Pins, Port D
$0F ($2F)
SPDR
SPI I/O Data Register
$0E ($2E)
SPSR
SPI Status Register
$0D ($2D)
SPCR
SPI Control Register
$0C ($2C)
UDR
UART I/O Data Register
$0B ($2B)
USR
UART Status Register
$0A ($2A)
UCR
UART Control Register
$09 ($29)
UBRR
UART Baud Rate Register
$08 ($28)
ACSR
Analog Comparator Control and Status Register
reserved and unused locations are not shown in the table
All the different AT90S8515 I/Os and peripherals are
placed in the I/O space. The different I/O locations are
accessed by the IN and OUT instructions transferring data
between the 32 general purpose working registers and the
I/O space. I/O registers within the address range $00 - $1F
are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be
checked by using the SBIS and SBIC instructions. Refer to
the instruction set chapter for more details.
When using the I/O specific commands, IN, OUT,SBIS and
SBIC, the I/O addresses $00 - $3F must be used. When
addressing I/O registers as SRAM, $20 must be added to
this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses.
The different I/O and peripherals control registers are
explained in the following chapters.
The Status Register - SREG
The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:
Bit
7
6
5
4
3
2
1
0
$3F ($5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the
interrupts to be enabled. The individual interrupt enable
control is then performed in the interrupt mask registers GIMSK and TIMSK. If the global interrupt enable register is
cleared (zero), none of the interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts.
• Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit
STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the register file by the BLD
instruction.
• Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result after the different
SREG
• Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for
detailed information.
• Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative
flag N and the two’s complement overflow flag V. See the
Instruction Set Description for detailed information.
• Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
• Bit 2 - N: Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction
Set Description for detailed information.
arithmetic and logic operations. See the Instruction Set
Description for detailed information.
13
• Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic
operation. See the Instruction Set Description for detailed
information.
Bit
The Stack Pointer - SP
The general AVR 16-bit Stack Pointer is effectively built up
of two 8-bit registers in the I/O space locations $3E ($5E)
and $3D ($5D). As the AT90S8515 supports up to 64 kB
external SRAM, all 16-bits are used.
15
14
13
12
11
10
9
8
$3E ($5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
$3D ($5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Initial value
The Stack Pointer points to the data SRAM stack area
where the Subroutine and Interrupt Stacks are located.
This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer is decremented by
one when data is pushed onto the Stack with the PUSH
instruction, and it is decremented by two when data is
pushed onto the Stack with subroutine CALL and interrupt.
The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is
incremented by two when data is popped from the Stack
with return from subroutine RET or return from interrupt
IRET.
14
AT90S8515
Reset and Interrupt Handling
The AT90S8515 provides 12 different interrupt sources.
These interrupts and the separate reset vector, each have
a separate program vector in the program memory space.
All interrupts are assigned individual enable bits which
must be set (one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are
automatically defined as the Reset and Interrupt vectors.
The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts.
The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 - the
External Interrupt Request 0 etc.
AT90S8515
Table 2. Reset and Interrupt Vectors
Vector No.
Program Address
Source
Interrupt Definition
1
$000
RESET
Hardware Pin and Watchdog Reset
2
$001
INT0
External Interrupt Request 0
3
$002
INT1
External Interrupt Request 1
4
$003
TIMER1 CAPT
Timer/Counter1 Capture Event
5
$004
TIMER1 COMPA
Timer/Counter1 Compare Match A
6
$005
TIMER1 COMPB
Timer/Counter1 Compare Match B
7
$006
TIMER1 OVF
Timer/Counter1 Overflow
8
$007
TIMER0, OVF
Timer/Counter0 Overflow
9
$008
SPI, STC
Serial Transfer Complete
10
$009
UART, RX
UART, Rx Complete
11
$00A
UART, UDRE
UART Data Register Empty
12
$00B
UART, TX
UART, Tx Complete
13
$00C
ANA_COMP
Analog Comparator
The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
Address
Labels
Code
Comments
$000
rjmp
RESET
; Reset Handler
$001
rjmp
EXT_INT0
; IRQ0 Handler
$002
rjmp
EXT_INT1
; IRQ1 Handler
$003
rjmp
TIM1_CAPT
; Timer1 Capture Handler
$004
rjmp
TIM1_COMPA ; Timer1 CompareA Handler
$005
rjmp
TIM1_COMPB ; Timer1 CompareB Handler
$006
rjmp
TIM1_OVF
; Timer1 Overflow Handler
$007
rjmp
TIM0_OVF
; Timer0 Overflow Handler
$008
rjmp
SPI_STC
; SPI Transfer Complete Handler
$009
rjmp
UART_RXC
; UART RX Complete Handler
$00a
rjmp
UART_DRE
; UDR Empty Handler
$00b
rjmp
UART_TXC
; UART TX Complete Handler
$00c
rjmp
ANA_COMP
; Analog Comparator Handler
;
$00d
…
MAIN:
…
<instr>
…
xxx
; Main program start
…
Reset Sources
The AT90S8515 has three sources of reset:
• Power-On Reset. The MCU is reset when a supply
voltage is applied to the VCC and GND pins.
• External Reset. The MCU is reset when a low level is
present on the RESET pin for more than two XTAL
cycles.
• Watchdog Reset. The MCU is reset when the Watchdog
timer period expires and the Watchdog is enabled.
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000.
The instruction placed in address $000 must be an RJMP relative jump - instruction to the reset handling routine. If
the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can
be placed at these locations. The circuit diagram in Figure
25 shows the reset logic. Table 3 defines the timing and
electrical parameters of the reset circuitry.
15
Figure 25. Reset Logic
Table 3. Reset Characteristics (VCC = 5.0V)
Symbol
Parameter
Min
Typ
Max
Units
VPOT
Power-On Reset Threshold Voltage
1.8
2
2.2
V
VRST
RESET Pin Threshold Voltage
tPOR
Power-On Reset Period
2
3
4
ms
tTOUT
Reset Delay Time-Out Period FSTRT Unprogrammed
11
16
21
ms
tTOUT
Reset Delay Time-Out Period FSTRT Programmed
1.0
1.1
1.2
ms
Power-on Reset
A Power-On Reset (POR) circuit ensures that the device is
not started until VCC has reached a safe level. As shown in
Figure 25, an internal timer clocked from the Watchdog
timer oscillator prevents the MCU from starting until after a
certain period after VCC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time (see Figure 26 and Figure 27). The total reset period is the PowerOn Reset period - tPOR + the Delay Time-out period - tTOUT.
The FSTRT fuse bit in the Flash can be programmed to
VCC/2
give a shorter start-up time if a ceramic resonator or any
other fast-start oscillator is used to clock the MCU.
If the build-in start-up delay is sufficient, RESET can be
connected to VCC directly or via an external pull-up resistor.
By holding the pin low for a period after V CC has been
applied, the Power-On Reset period can be extended.
Refer to Figure 28 for a timing example on this.
Figure 26. MCU Start-Up, RESET Tied to VCC. Rapidly Rising VCC
16
AT90S8515
V
AT90S8515
Figure 27. MCU Start-Up, RESET Tied to VCC or Unconnected. Slowly Rising VCC
Figure 28. MCU Start-Up, RESET Controlled Externally
External Reset
An external reset is generated by a low level on the RESET
pin. The RESET pin must be held low for at least two crystal clock cycles. When the applied signal reaches the Reset
Threshold Voltage - V RST on its positive edge, the delay
timer starts the MCU after the Time-out period t TOUT has
expired.
17
Figure 29. External Reset During Operation
Watchdog Reset
When the Watchdog times out, it will generate a short reset
pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period
t TOUT . Refer to page 30 for details on operation of the
Watchdog.
Figure 30. Watchdog Reset During Operation
Interrupt Handling
The AT90S8515 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit
is cleared (zero) and all interrupts are disabled. The user
software must set (one) the I-bit to enable interrupts.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated
the interrupt. Some of the interrupt flags can also be
cleared by writing a logic one to the flag bit position(s) to be
cleared.
The General Interrupt Mask Register - GIMSK
Bit
7
6
5
4
3
2
1
$3B ($5B)
INT1
INT0
-
-
-
-
-
-
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status
Register (SREG) is set (one), the external pin interrupt is
activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR)
defines whether the external interrupt is activated on rising
18
AT90S8515
0
GIMSK
or falling edge of the INT1 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory
address $002. See also “External Interrupts”.
AT90S8515
• Bit 6 - INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status
Register (SREG) is set (one), the external pin interrupt is
activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR)
defines whether the external interrupt is activated on rising
or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is con-
figured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
• Bits 5..0 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and always
read as zero.
The General Interrupt Flag Register - GIFR
Bit
7
6
5
4
3
2
1
$3A ($5A)
INTF1
INTF0
-
-
-
-
-
-
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt
request, INTF1 becomes set (one). If the I-bit in SREG and
the INT1 bit in GIMSK are set (one), the MCU will jump to
the interrupt vector at address $002. The flag is cleared
when the interrupt routine is executed. Alternatively, the
flag can be cleared by writing a logical one to it.
• Bit 6 - INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt
request, INTF0 becomes set (one). If the I-bit in SREG and
0
GIFR
the INT0 bit in GIMSK are set (one), the MCU will jump to
the interrupt vector at address $001. The flag is cleared
when the interrupt routine is executed. Alternatively, the
flag can be cleared by writing a logical one to it.
• Bits 5..0 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and always
read as zero.
The Timer/counter Interrupt Mask Register - TIMSK
Bit
7
6
5
4
3
2
1
TOIE1
OCIE1A
OCIE1B
-
TICIE1
-
TOIE0
-
Read/Write
R/W
R/W
R/W
R
R/W
R
R/W
R
Initial value
0
0
0
0
0
0
0
0
$39 ($59)
• Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status
Register is set (one), the Timer/Counter1 Overflow interrupt
is enabled. The corresponding interrupt (at vector $006) is
executed if an overflow in Timer/Counter1 occurs. The
Overflow Flag (Timer/Counter1) is set (one) in the
Timer/Counter Interrupt Flag Register - TIFR. When
Timer/Counter1 is in PWM mode, the Timer Overflow flag
is set when the counter changes counting direction at
$0000.
• Bit 6 - OCE1A:Timer/Counter1 Output CompareA Match
Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status
Register is set (one), the Timer/Counter1 CompareA Match
interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if a CompareA match in Timer/Counter1
occurs. The CompareA Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register - TIFR.
• Bit 5 - OCIE1B:Timer/Counter1 Output CompareB Match
Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status
Register is set (one), the Timer/Counter1 CompareB Match
interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if a CompareB match in Timer/Counter1
0
TIMSK
occurs. The CompareB Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register - TIFR.
• Bit 4 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and always
reads zero.
• Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt
Enable
When the TICIE1 bit is set (one) and the I-bit in the Status
Register is set (one), the Timer/Counter1 Input Capture
Event Interrupt is enabled. The corresponding interrupt (at
vector $003) is executed if a capture-triggering event
oc cur s o n pin 31, ICP . Th e Input Capture Flag i n
Timer/Counter1 is set (one) in the Timer/Counter Interrupt
Flag Register - TIFR.
• Bit 2 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and always
reads zero.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status
Register is set (one), the Timer/Counter0 Overflow interrupt
is enabled. The corresponding interrupt (at vector $008) is
executed if an overflow in Timer/Counter0 occurs. The
19
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and always
reads zero.
Overflow Flag (Timer0) is set (one) in the Timer/Counter
Interrupt Flag Register - TIFR.
The Timer/Counter Interrupt Flag Register - TIFR
Bit
7
6
5
4
3
2
1
$38 ($58)
TOV1
OCF1A
OCIFB
-
ICF1
-
TOV0
-
Read/Write
R/W
R/W
R/W
R
R/W
R
R/W
R
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in
Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag.
When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the
Timer/Counter1 Overflow Interrupt is executed. In PWM
mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
• Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs
between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to
the flag. When the I-bit in SREG, and OCIE1A
(Timer/Counter1 Compare match InterruptA Enable), and
the OCF1A are set (one), the Timer/Counter1 Compare
match Interrupt is executed.
• Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs
between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic one to
the flag.. When the I-bit in SREG, and OCIE1B
(Timer/Counter1 Compare match InterruptB Enable), and
the OCF1B are set (one), the Timer/Counter1 Compare
match Interrupt is executed.
• Bit 4 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and always
reads zero.
• Bit 3 - ICF1: - Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred
to the input capture register - ICR1. ICF1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic
one to the flag.
• Bit 2 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and always
reads zero.
20
AT90S8515
0
TIFR
• Bit 1 - TOV: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in
Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and always
reads zero.
External Interrupts
The external interrupts are triggered by the INT1 and INT0
pins. Observe that, if enabled, the interrupts will trigger
even if the INT0/INT1 pins are configured as outputs. This
feature provides a way of generating a software interrupt.
The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the
specification for the MCU Control Register - MCUCR.
When the external interrupt is enabled and is configured as
level triggered, the interrupt will trigger as long as the pin is
held low.
The external interrupts are set up as described in the specification for the MCU Control Register - MCUCR.
Interrupt Response Time
The interrupt execution response for all the enabled AVR
interrupts is 4 clock cycles minimum. 4 clock cycles after
the interrupt flag has been set, the program vector address
for the actual interrupt handling routine is executed. During
this 4 clock cycle period, the Program Counter (2 bytes) is
pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is a relative jump to the interrupt
routine, and this jump takes 2 clock cycles. If an interrupt
occurs during execution of a multi-cycle instruction, this
instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a
subroutine call routine) takes 4 clock cycles. During these 4
clock cycles, the Program Counter (2 bytes) is popped
back from the Stack, and the Stack Pointer is incremented
by 2. When the AVR exits from an interrupt, it will always
return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register - SREG - is not handled by
the AVR hardware, neither for interrupts nor for subrou-
AT90S8515
tines. For the interrupt handling routines requiring a storage
of the SREG, this must be performed by user software.
For Interrupts triggered by events that can remain static
(E.g. the Output Compare Register1 A matching the value
of Timer/Counter1) the interrupt flag is set when the event
occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs
the next time.
MCU Control Register - MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
5
4
3
2
1
0
$35 ($55)
SRE
SRW
SE
SM
ISC11
ISC10
ISC01
ISC00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - SRE: External SRAM Enable
When the SRE bit is set (one), the external data SRAM is
enabled, and the pin functions AD0-7 (Port A), A8-15 (Port
C), WR and RD (Port D) are activated as the alternate pin
functions. Then the SRE bit overrides any pin direction settings in the respective data direction registers. See “The
SRAM Data Memory - Internal and External” for description
of the External SRAM pin functions. When the SRE bit is
cleared (zero), the external data SRAM is disabled, and the
normal pin and data direction settings are used.
• Bit 6 - SRW: External SRAM Wait State
When the SRW bit is set (one), a one cycle wait state is
inserted in the external data SRAM access cycle. When the
SRW bit is cleared (zero), the external data SRAM access
is executed with the normal three-cycle scheme. See Figure 23: External Data SRAM Memory Cycles without Wait
State and Figure 24: External Data SRAM Memory Cycles
with Wait State.
• Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the
sleep mode when the SLEEP instruction is executed. To
avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep
Enable SE bit just before the execution of the SLEEP
instruction.
• Bit 4 - SM: Sleep Mode
This bit selects between the two available sleep modes.
When SM is cleared (zero), Idle Mode is selected as Sleep
Mode. When SM is set (one), Power Down mode is
selected as sleep mode. For details, refer to the paragraph
“Sleep Modes” below.
• Bit 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and
external INT1 pin that activate the interrupt are defined in
the following table:
Table 4. Interrupt 1 Sense Control
ISC11
ISC10
0
0
The low level of INT1 generates an
interrupt request.
0
1
Reserved
1
0
The falling edge of INT1 generates an
interrupt request.
1
1
The rising edge of INT1 generates an
interrupt request.
Note:
Description
When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt Enable bit in the GIMSK
Register. Otherwise an interrupt can occur when the bits
are changed.
• Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and
bit 0
The External Interrupt 0 is activated by the external pin
INT0 if the SREG I-flag and the corresponding interrupt
mask is set. The level and edges on the external INT0 pin
that activate the interrupt are defined in the following table:
Table 5. Interrupt 0 Sense Control
ISC01
ISC00
0
0
The low level of INT0 generates an
interrupt request.
0
1
Reserved
1
0
The falling edge of INT0 generates an
interrupt request.
1
1
The rising edge of INT0 generates an
interrupt request.
bit 0
The External Interrupt 1 is activated by the external pin
INT1 if the SREG I-flag and the corresponding interrupt
mask in the GIMSK is set. The level and edges on the
MCUCR
Note:
Description
When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK
Register. Otherwise an interrupt can occur when the bits
are changed.
21
Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be
set (one) and a SLEEP instruction must be executed. If an
enabled interrupt occurs while the MCU is in a sleep mode,
the MCU awakes, executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
The contents of the register file, SRAM and I/O memory are
unaltered. If a reset occurs during sleep mode, the MCU
wakes up and executes from the Reset vector.
Idle Mode
When the SM bit is cleared (zero), the SLEEP instruction
forces the MCU into the Idle Mode stopping the CPU but
allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake
up from external triggered interrupts as well as internal
ones like Timer Overflow interrupt and watchdog reset. If
wakeup from the Analog Comparator interrupt is not
required, the analog comparator can be powered down by
setting the ACD-bit in the Analog Comparator Control and
The Timer/Counter Prescaler
Figure 31 shows the general Timer/Counter prescaler.
Figure 31. Timer/Counter Prescaler
The four different prescaled selections are: CK/8, CK/64,
CK/256 and CK/1024 where CK is the oscillator clock. For
the two Timer/Counters, added selections as CK, external
source and stop, can be selected as clock sources.
22
AT90S8515
Status register - ACSR. This will reduce power consumption in Idle Mode.
Power Down Mode
When the SM bit is set (one), the SLEEP instruction forces
the MCU into the Power Down Mode. In this mode, the
external oscillator is stopped. The user can select whether
the watchdog shall be enabled during power-down mode. If
the watchdog is enabled, it will wake up the MCU when the
Watchdog Time-out period expires. If the watchdog is disabled, only an external reset or an external level triggered
interrupt can wake up the MCU.
Timer / Counters
The AT90S8515 provides two general purpose
Timer/Counters - one 8-bit T/C and one 16-bit T/C. The
Timer/Counters have individual prescaling selection from
the same 10-bit prescaling timer. Both Timer/Counters can
either be used as a timer with an internal clock timebase or
as a counter with an external pin connection which triggers
the counting.
AT90S8515
The 8-Bit Timer/Counter0
Figure 32 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK,
prescaled CK, or an external pin. In addition it can be
s to p pe d a s de s c r i be d i n th e s p ec i f i c at io n fo r t h e
Timer/Counter0 Control Register - TCCR0. The overflow
status flag is found in the Timer/Counter Insterrupt Flag
Reg is te r - TIFR. Con tr ol s i gn al s ar e fo und i n th e
Timer/Counter0 Control Register - TCCR0. The interrupt
enable/disable settings for Timer/Counter0 are found in the
Timer/Counter Interrupt Mask Register - TIMSK.
When Timer/Counter0 is externally clocked, the external
signal is synchronized with the oscillator frequency of the
CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must
be at least one internal CPU clock period. The external
clock signal is sampled on the rising edge of the internal
CPU clock.
The 8-bit Timer/Counter0 features both a high resolution
and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make
the Timer/Counter0 useful for lower speed functions or
exact timing functions with infrequent actions.
Figure 32. Timer/Counter0 Block Diagram
The Timer/Counter0 Control Register - TCCR0
Bit
7
6
5
4
3
2
1
0
$33 ($53)
-
-
-
-
-
CS02
CS01
CS00
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
TCCR0
• Bits 7,6 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and always
read zero.
• Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0
The Clock Select0 bits 2,1 and 0 define the prescaling
source of Timer0.
23
Table 6. Clock 0 Prescale Select
CS02
CS01
CS00
Description
0
0
0
Stop, the Timer/Counter0 is stopped.
0
0
1
CK
0
1
0
CK / 8
0
1
1
CK / 64
1
0
0
CK / 256
1
0
1
CK / 1024
1
1
0
External Pin T0, falling edge
1
1
1
External Pin T0, rising edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from
the CK oscillator clock. If the external pin modes are used,
the corresponding setup must be performed in the actual
data direction control register (cleared to zero gives an
input pin).
The Timer Counter 0 - TCNT0
Bit
7
6
5
4
3
2
1
0
$32 ($52)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
The Timer/Counter0 is realized as an up-counter with read
and write access. If the Timer/Counter0 is written and a
clock source is present, the Timer/Counter0 continues
counting in the clock cycle following the write operation.
24
AT90S8515
TCNT0
AT90S8515
The 16-Bit Timer/Counter1
Figure 33 shows the block diagram for Timer/Counter1.
Figure 33. Timer/Counter1 Block Diagram
The 16-bit Timer/Counter1 can select clock source from
CK, prescaled CK, or an external pin. In addition it can be
s to p pe d a s de s c r i be d i n th e s p ec i f i c at io n fo r t h e
Time r/Co unte r1 Cont rol Re gis ters - TCCR1A an d
TCCR1B. The different status flags (overflow, compare
match and capture event) and control signals are found in
the Timer/Counter1 Control Registers - TCCR1A and
TCCR1B. The interrupt enable/disable settings for
Timer/Counter1 are found in the Timer/Counter Interrupt
Mask Register - TIMSK.
When Timer/Counter1 is externally clocked, the external
signal is synchronized with the oscillator frequency of the
CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must
be at least one internal CPU clock period. The external
clock signal is sampled on the rising edge of the internal
CPU clock.
The 16-bit Timer/Counter1 features both a high resolution
and a high accuracy usage with the lower prescaling oppor-
tunities. Similarly, the high prescaling opportunities makes
the Timer/Counter1 useful for lower speed functions or
exact timing functions with infrequent actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B OCR1A and OCR1B as the data sources to be compared
to the Timer/Counter1 contents. The Output Compare functions include optional clearing of the counter on compareA
match, and actions on the Output Compare pins on both
compare matches.
Timer/Counter1 can also be used as a 8, 9 or 10-bit Pulse
With Modulator. In this mode the counter and the
OCR1A/OCR1B registers serve as a dual glitch-free standalone PWM with centered pulses. Refer to page 33 for a
detailed description on this function.
The Input Capture function of Timer/Counter1 provides a
capture of the Timer/Counter1 contents to the Input Capture Register - ICR1, triggered by an external event on the
Input Capture Pin - ICP. The actual capture event settings
25
are defined by the Timer/Counter1 Control Register TCCR1B. In addition, the Analog Comparator can be set to
trigger the Input Capture. Refer to the section, “The Analog
Comparator”, for details on this. The ICP pin logic is shown
in Figure 34.
Figure 34. ICP Pin Schematic Diagram
If the noise canceler function is enabled, the actual trigger
condition for the capture event is monitored over 4 samples
before the capture is activated. The input pin signal is sampled at XTAL clock frequency.
The Timer/Counter1 Control Register A - TCCR1A
Bit
7
6
5
4
3
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
-
-
PWM11
PWM10
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$2F ($4F)
• Bits 7,6 - COM1A1, COM1A0: Compare Output Mode1A,
bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in
Timer/Counter1. Any output pin actions affect pin OC1A Output CompareA pin 1. Since this is an alternative function to an I/O port, the corresponding direction control bit
must be set (one) to control an output pin. The control configuration is shown in Table 7.
• Bits 5,4 - COM1B1, COM1B0: Compare Output Mode1B,
bits 1 and 0
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in
Timer/Counter1. Any output pin actions affect pin OC1B Output CompareB. The following control configuration is
given:
Table 7. Compare 1 Mode Select
COM1X1
COM1X0
Description
0
0
Timer/Counter1 disconnected from
output pin OC1X
0
1
Toggle the OC1X output line.
1
0
Clear the OC1X output line (to zero).
1
1
Set the OC1X output line (to one).
X = A or B
In PWM mode, these bits have a different function. Refer to
Table 11 for a detailed description.
When changing the COM1X1/COM1X0 bits, Output Compare Interrupts 1 must be disabled by clearing their Inter-
26
AT90S8515
TCCR1A
rupt Enable bits in the TIMSK Register. Otherwise an
interrupt can occur when the bits are changed.
• Bits 3..2 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and always
read zero.
• Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select
Bits
These bits select PWM operation of Timer/Counter1 as
specified in Table 8. This mode is described on page 29.
Table 8. PWM Mode Select
PWM11
PWM10
Description
0
0
PWM operation of Timer/Counter1 is
disabled
0
1
Timer/Counter1 is an 8-bit PWM
1
0
Timer/Counter1 is a 9-bit PWM
1
1
Timer/Counter1 is a 10-bit PWM
AT90S8515
The Timer/Counter1 Control Register B - TCCR1B
Bit
7
6
5
4
3
2
1
0
$2E ($4E)
ICNC1
ICES1
-
-
CTC1
CS12
CS11
CS10
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is
triggered at the first rising/falling edge sampled on the ICP input capture pin - as specified. When the ICNC1 bit is set
(one), four successive samples are measures on the ICP input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1
bit. The actual sampling frequency is XTAL clock frequency.
• Bit 6 - ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1
contents are transferred to the Input Capture Register ICR1 - on the falling edge of the input capture pin - ICP.
While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 on the rising edge of the input capture pin - ICP.
• Bits 5, 4 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and always
read zero.
• Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1
is reset to $0000 in the clock cycle after a compareA
match. If the CTC1 control bit is cleared, Timer/Counter1
continues counting and is unaffected by a compare match.
Since the compare match is detected in the CPU clock
cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer.
When a prescaling of 1 is used, and the compareA register
is set to C, the timer will count as follows i CTC1 is set:
TCCR1B
... | C-1 | C | C+1 | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count
like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C,
C, C, C | C+1, 0, 0, 0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has no effect.
• Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, bit 2,1 and 0
The Clock Select1 bits 2,1 and 0 define the prescaling
source of Timer/Counter1.
Table 9. Clock 1 Prescale Select
CS12
CS11
CS10
Description
0
0
0
Stop, the Timer/Counter1 is stopped.
0
0
1
CK
0
1
0
CK / 8
0
1
1
CK / 64
1
0
0
CK / 256
1
0
1
CK / 1024
1
1
0
External Pin T1, falling edge
1
1
1
External Pin T1, rising edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from
the CK oscillator clock. If the external pin modes are used,
the corresponding setup must be performed in the actual
direction control register (cleared to zero gives an input
pin).
The Timer/Counter1 - TCNT1H AND TCNT1L
Bit
$2D ($4D)
15
14
13
12
11
10
9
TCNT1H
LSB
$2C ($4C)
Read/Write
Initial value
8
MSB
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This 16-bit register contains the prescaled value of the 16bit Timer/Counter1. To ensure that both the high and low
bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an
8-bit temporary register (TEMP). This temporary register is
also used when accessing OCR1A, OCR1B and ICR1. If
the main program and also interrupt routines perform
TCNT1L
access to registers using TEMP, interrupts must be disabled during access from the main program.
• TCNT1 Timer/Counter1 Write:
When the CPU writes to the high byte TCNT1H, the
written data is placed in the TEMP register. Next, when
the CPU writes the low byte TCNT1L, this byte of data
is combined with the byte data in the TEMP register,
27
and all 16 bits are written to the TCNT1
Timer/Counter1 register simultaneously. Consequently, the high byte TCNT1H must be accessed first
for a full 16-bit register write operation.
• TCNT1 Timer/Counter1 Read:
When the CPU reads the low byte TCNT1L, the data of
the low byte TCNT1L is sent to the CPU and the data of
the high byte TCNT1H is placed in the TEMP register.
When the CPU reads the data in the high byte
TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be
accessed first for a full 16-bit register read operation.
The Timer/Counter1 is realized as an up or up/down (in
PWM mode) counter with read and write access. If
Timer/Counter1 is written to and a clock source is selected,
the Timer/Counter1 continues counting in the timer clock
cycle after it is preset with the written value.
Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL
Bit
$2B ($4B)
15
14
13
12
11
10
9
OCR1AH
LSB
$2A ($4A)
Read/Write
Initial value
8
MSB
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
8
OCR1AL
Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL
Bit
$29 ($49)
15
14
13
12
11
10
MSB
OCR1BH
LSB
$28 ($48)
Read/Write
Initial value
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain
the data to be continuously compared with Timer/Counter1.
Ac tion s o n c ompa re matc hes ar e s pec ifi ed i n th e
Timer/Counter1 Control and Status register.A compare
match does only occur if Timer/Counter1 counts to the
OCR value. A software write that sets TCNT1 and OCR1A
or OCR1B to the same value does not generate a compare
match.
A compare match will set the compare interrupt flag in the
CPU clock cycle following the compare event.
28
AT90S8515
OCR1BL
Since the Output Compare Registers - OCR1A and
OCR1B - are 16-bit registers, a temporary register TEMP is
used when OCR1A/B are written to ensure that both bytes
are updated simultaneously. When the CPU writes the high
byte, OCR1AH or OCR1BH, the data is temporarily stored
in the TEMP register. When the CPU writes the low byte,
OCR1AL or OCR1BL, the TEMP register is simultaneously
written to OCR1AH or OCR1BH. Consequently, the high
byte OCR1AH or OCR1BH must be written first for a full
16-bit register write operation.
The TEMP register is also used when accessing TCNT1,
and ICR1. If the main program and also interrupt routines
perform access to registers using TEMP, interrupts must
be disabled during access from the main program.
AT90S8515
The Timer/Counter1 Input Capture Register - ICR1H AND ICR1L
Bit
15
$25 ($45)
14
13
12
11
10
9
8
MSB
ICR1H
LSB
$24 ($44)
7
Read/Write
Initial value
6
5
4
3
2
1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The input capture register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture
pin - ICP - is detected, the current value of the
Timer/Counter1 is transferred to the Input Capture Register
- ICR1. At the same time, the input capture flag - ICF1 - is
set (one).
Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read
to ensure that both bytes are read simultaneously. When
the CPU reads the low byte ICR1L, the data is sent to the
CPU and the data of the high byte ICR1H is placed in the
TEMP register. When the CPU reads the data in the high
byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed
first for a full 16-bit register read operation.
The TEMP register is also used when accessing TCNT1,
OCR1A and OCR1B. If the main program and also interrupt
routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.
ICR1L
0
Table 11. Compare1 Mode Select in PWM Mode
COM1X1
COM1X0
0
0
Not connected
0
1
Not connected
1
0
Cleared on compare match,
upcounting. Set on compare match,
downcounting (non-inverted PWM).
1
1
Cleared on compare match,
downcounting. Set on compare
match, upcounting (inverted PWM).
Note:
Effect on OCX1
X = A or B
Note that in the PWM mode, the 10 least significant
OCR1A/OCR1B bits, when written, are transferred to a
temporary location. They are latched when Timer/Counter1
reaches the value TOP. This prevents the occurrence of
odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an
example.
Timer/Counter1 In PWM Mode
When the PWM mode is selected, Timer/Counter1 and the
Output Compare Register1A - OCR1A and the Output
Compare Register1B - OCR1B, form a dual 8, 9 or 10-bit,
free-running, glitch-free and phase correct PWM with outputs on the PD5(OC1A) and OC1B pins. Timer/Counter1
acts as an up/down counter, counting up from $0000 to
TOP (see Table 10) , when it turns and counts down again
to zero before the cycle is repeated. When the counter
value matches the contents of the 10 least significant bits
of OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set
or cleared according to the settings of the
COM1A1/COM1A0 or COM1B1/COM1B0 bits in the
Timer/Counter1 Control Register TCCR1A. Refer to Table
11 for details.
Table 10. Timer TOP Values and PWM Frequency
PWM Resolution
Timer TOP value
Frequency
8-bit
$00FF (255)
fTC1/510
9-bit
$01FF (511)
fTC1/1022
10-bit
$03FF(1023)
fTC1/2046
29
Figure 35. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation,
a read from OCR1A or OCR1B will read the contents of the
temporary location. This means that the most recently written value always will read out of OCR1A/B
When OCR1 contains $0000 or TOP, the output
OC1A/OC1B is held low or high according to the settings of
COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in
Table 12:
Table 12. PWM Outputs OCR1X = $0000 or TOP
COM1X1
COM1X0
OCR1X
Output OC1X
1
0
$0000
L
1
0
TOP
H
1
1
$0000
H
1
1
TOP
L
Note:
X = A or B
In PWM mode, the Timer Overflow Flag1, TOV1, is set
when the counter changes direction at $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter
mode, i.e. it is executed when TOV1 is set provided that
Timer Overflow Interrupt1 and global interrupts are
enabled. This does also apply to the Timer Output
Compare1 flags and interrupts.
The Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip
oscillator which runs at 1MHz This is the typical value at
VCC = 5V. See characterization data for typical values at
other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted from
16K to 2,048K cycles (nominally 16 - 2048 ms). The WDR Watchdog Reset - instruction resets the Watchdog Timer.
Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the AT90S8515 resets and exe-
30
AT90S8515
cutes from the reset vector. For timing details on the
Watchdog reset, refer to page 18.
To prevent unintentional disabling of the watchdog, a special turn-off secuence must be followed when the watchdog
is disabled.Refer to the description of the Watchdog Timer
Control Register for details.
Figure 36. Watchdog Timer
AT90S8515
The Watchdog Timer Control Register - WDTCR
Bit
7
6
5
4
3
2
1
0
$21 ($41)
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and will
always read as zero.
• Bit 4 - WDTOE: Watch Dog Turn-Off Enable
This bit must be set (one) when the WDE bit is cleared.
Otherwise, the watchdog will not be disabled. Once set,
hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a watchdog disable procedure.
• Bit 3 - WDE: Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is
enabled, and if the WDE is cleared (zero) the Watchdog
Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set(one). To disable an enabled watchdog
timer, the following procedure must be followed:
1. In the same operation, write a logical one to
WDTOE and WDE. A logcal one must be written to
WDE even though it is set to one before the disable
operation starts.
2. Within the next four clock cycles, write a logical 0 to
WDE. This disables the watchdog.
• Bits 2..0 - WDP2, WDP1, WDP0: Watch Dog Timer Prescaler
WDTCR
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O
space.
The write access time is in the range of 2.5 - 4ms, depending on the VCC voltages. A self-timing function, however,
lets the user software detect when the next byte can be
written. If the user code contains code that writes the
EEPROM, some precaution must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on
power-up/down. This causes the device for some period of
time to run at a voltage lower than specified as minimum for
the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write
code. To secure EEPROM integrity, the user is advised to
use an external under-voltage reset circuit in this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read or written, the CPU is halted for
two clock cycles before the next instruction is executed.
2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 13.
Table 13. Watch Dog Timer Prescale Select
WDP2
WDP1
WDP0
Timeout Period
0
0
0
16K cycles
0
0
1
32K cycles
0
1
0
64K cycles
0
1
1
128K cycles
1
0
0
256K cycles
1
0
1
512K cycles
1
1
0
1,024K cycles
1
1
1
2,048K cycles
31
The EEPROM Address Register - EEARH and EEARL
Bit
15
14
13
12
11
10
9
8
$1F ($3F)
-
-
-
-
-
-
-
EEAR8
EEARH
$1E ($3E)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
Read/Write
Initial value
The EEPROM Address Registers - EEARH and EEARL
specify the EEPROM address in the 512 bytes EEPROM
space. The EEPROM data bytes are addressed linearly
between 0 and 512.
The EEPROM Data Register - EEDR
Bit
7
6
5
4
3
2
1
0
$1D ($3D)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bits 7..0 - EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address
EEDR
given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the
EEPROM at the address given by EEAR.
The EEPROM Control Register - EECR
Bit
7
6
5
4
3
2
1
0
$1C ($3C)
-
-
-
-
-
EEMWE
EEWE
EERE
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bit 7..3 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and will
always read as zero.
• Bit 2 - EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one
causes the EEPROM to be written. When EEMWE is
set(one) setting EEWE will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will
have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for a EEPROM write
procedure.
• Bit 1 - EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write
strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value
into the EEPROM. The EEMWE bit must be set when the
logical one is written to EEWE, otherwise no EEPROM
write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and
3 is unessential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEARL and
EEARH (optional)
32
AT90S8515
EECR
3. Write new EEPROM data to EEDR (optional)
4. Write a logical one to the EEMWE bit in EECR
5. Within four clock cycles after setting EEMWE, write
a logical one to EEWE.
When the write access time (typically 2.5 ms at V CC = 5V or
4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared
(zero) by hardware. The user software can poll this bit and
wait for a zero before writing the next byte. When EEWE
has been set, the CPU is halted for two cycles before the
next instruction is executed.
• Bit 0 - EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read
strobe to the EEPROM. When the correct address is set up
in the EEAR register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is
found in the EEDR register. The EEPROM read access
takes one instruction and there is no need to poll the EERE
bit. When EERE has been set, the CPU is halted for two
cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read
operation. If a write operation is in progress when new data
or address is written to the EEPROM I/O registers, the
write operation will be interrupted, and the result is undefined.
AT90S8515
The Serial Peripheral Interface - SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8515 and peripheral
devices or between several AT90S8515 devices. The AT90S8515 SPI features include the following:
• Full-Duplex, 3-Wire Synchronous Data Transfer
• End of Transmission Interrupt Flag
• Master or Slave Operation
• Write Collision Flag Protection
• LSB First or MSB First Data Transfer
• Wakeup from Idle Mode (Slave Mode Only)
• Four Programmable Bit Rates
Figure 37. SPI Block Diagram
The interconnection between master and slave CPUs with
SPI is shown in Figure 38. The PB7(SCK) pin is the clock
output in the master mode and is the clock input in the
slave mode. Writing to the SPI data register of the master
CPU starts the SPI clock generator, and the data written
shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin
of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If
the SPI interrupt enable bit (SPIE) in the SPCR register is
set, an interrupt is requested. The Slave Select input,
PB4(SS), is set low to select an individual SPI device as a
slave. The two shift registers in the Master and the Slave
can be considered as one distributed 16-bit circular shift
register. This is shown in Figure 38. When data is shifted
from the master to the slave, data is also shifted in the
opposite direction, simultaneously. This means that during
one shift cycle, data in the master and the slave are interchanged.
33
Figure 38. SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and
double buffered in the receive direction. This means that
characters to be transmitted cannot be written to the SPI
Data Register before the entire shift cycle is completed.
When receiving data, however, a received character must
be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first character is lost.
When the SPI is enabled, the data direction of the MOSI,
MISO, SCK and SS pins is overriden according to the following table:
Table 14. SPI Pin Overrides
Pin
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
SS Pin Functionality
When the SPI is configured as a master (MSTR in SPCR is
set), the user can determine the direction of the SS pin. If
SS is configured as an output, the pin is a general output
pin which does not affect the SPI system. If SS is configured as an input, it must be hold high to ensure Master SPI
operation. If, in master mode, the SS pin is input, and is
34
AT90S8515
driven low by peripheral circuitry, the SPI system interpretes this as another master selecting the SPI as a slave
and starting to send data to it. To avoid bus contention, the
SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs.
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmittal is used in master mode, and there exists a possibility that SS is driven
low, the interrupt should always check that the MSTR bit is
still set. Once the MSTR bit has been cleared by a slave
select, it must be set by the user.
When the SPI is configured as a slave, the SS pin is always
input. When SS is held low, the SPI is activated and MISO
becomes an output if configured so by the user. All other
pins are inputs. When SS is driven high, all pins are inputs,
and the SPI is passive, which means that it will not receive
incoming data.
Data Modes
There are four combinations of SCK phase and polarity
with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are
shown in Figure 39 and Figure 40.
AT90S8515
Figure 39. SPI Transfer Format with CPHA = 0
Figure 40. SPI Transfer Format with CPHA = 1
The SPI Control Register - SPCR
Bit
7
6
5
4
3
2
1
0
$0D ($2D)
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
1
0
0
• Bit 7 - SPIE: SPI Interrupt Enable
This bit causes setting of the SPIF bit in the SPSR register
to execute the SPI interrupt provided that global interrupts
are enabled.
• Bit 6 - SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit
must be set to enable any SPI operations.
• Bit 5 - DORD: Data Order
When the DORD bit is set (one), the LSB of the data word
is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data
word is transmitted first.
• Bit 4 - MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and
Slave SPI mode when cleared (zero). If SS is configured as
an input and is driven low whil MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will
then have to set MSTR to re-enable SPI master mode.
• Bit 3 - CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When
CPOL is cleared (zero), SCK is low when idle. Refer to Figure 39 and Figure 40 for additional information.
SPCR
• Bit 2 - CPHA: Clock Phase
Refer to Figure 39 or Figure 40 for the functionality of this
bit.
• Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the
slave. The relationship between SCK and the Oscillator
Clock frequency fcl is shown in the following table:
Table 15. Relationship Between SCK and the Oscillator
Frequency
SPR1
SPR0
0
0
0
1
1
0
1
1
SCK Frequency
fcl / 4
fcl / 16
fcl / 64
fcl / 128
35
The SPI Status Register - SPSR
Bit
7
6
5
4
3
2
1
$0E ($2E)
SPIF
WCOL
-
-
-
-
-
-
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one)
and an interrupt is generated if SPIE in SPCR is set (one)
and global interrupts are enabled. If SS is an input and is
driven low when the SPI is in master mode, this will also set
the SPIF flag. SPIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively,
the SPIF bit is cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI Data Register (SPDR).
• Bit 6 - WCOL: Write Collision Flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. During data transfer, the result of
0
SPSR
reading the SPDR register may be incorrect, and writing to
it will have no effect. The WCOL bit (and the SPIF bit) are
cleared (zero) by first reading the SPI Status Register with
WCOL set (one), and then accessing the SPI Data Register.
• Bit 5..0 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and will
always read as zero.
The SPI interface on the AT90S8515 is also used for program memory and EEPROM downloading or uploading.
See page 62 for serial programming and verification.
The SPI Data Register - SPDR
Bit
7
6
5
4
3
2
1
0
$0F ($2F)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
The SPI Data Register is a read/write register used for data
transfer between the register file and the SPI Shift register.
Writing to the register initiates data transmission. Reading
the register causes the Shift Register Receive buffer to be
read.
36
AT90S8515
SPDR
AT90S8515
The UART
The AT90S8515 features a full duplex Universal Asynchronous Receiver and Transmitter (UART). The main features are:
• Baud rate generator generates any baud rate
• Overrun detection
• High baud rates at low XTAL frequencies
• Framing Error detection
• 8 or 9 bits data
• False Start Bit detection
• Noise filtering
• Three separate interrupts on TX Complete, TX Data
Register Empty and RX Complete
Data Transmission
A block schematic of the UART transmitter is shown in Figure 41.
Figure 41. UART Transmitter
Data transmission is initiated by writing the data to be
transmitted to the UART I/O Data Register, UDR. Data is
transferred from UDR to the Transmit shift register when:
• A new character has been written to UDR after the stop
bit from the previous character has been shifted out. The
shift register is loaded immediately.
• A new character has been written to UDR before the stop
bit from the previous character has been shifted out. The
shift register is loaded when the stop bit of the character
currently being transmitted has been shifted out.
If the 10(11)-bit Transmitter shift register is empty or when,
data is transferred from UDR to the shift register. At this
time the UDRE (UART Data Register Empty) bit in the
UART Status Register, USR, is set. When this bit is set
(one), the UART is ready to receive the next character. At
the same time as the data is transferred from UDR to the
10(11)-bit shift register, bit 0 of the shift register is cleared
(start bit) and bit 9 or 10 is set (stop bit). If 9 bit data word is
selected (the CHR9 bit in the UART Control Register, UCR
is set), the TXB8 bit in UCR is transferred to bit 9 in the
Transmit shift register.
37
On the Baud Rate clock following the transfer operation to
the shift register, the start bit is shifted out on the TXD pin.
Then follows the data, LSB first. When the stop bit has
been shifted out, the shift register is loaded if any new data
has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR
register to send when the stop bit is shifted out, the UDRE
flag will remain set until UDR is written again. When no new
data has been written, and the stop bit has been present on
TXD for one bit length, the TX Complete Flag, TXC, in USR
is set.
The TXEN bit in UCR enables the UART transmitter when
set (one). When this bit is cleared (zero), the PD1 pin can
be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PD1, which is forced to be
an output pin regardless of the setting of the DDD1 bit in
DDRD.
Data Reception
Figure 42 shows a block diagram of the UART Receiver.
Figure 42. UART Receiver
The receiver front-end logic samples the signal on the RXD
pin at a frequency 16 times the baud rate. While the line is
idle, one single sample of logical zero will be interpreted as
the falling edge of a start bit, and the start bit detection
sequence is initiated. Let sample 1 denote the first zerosample. Following the 1 to 0-transition, the receiver samples the RXD pin at samples 8, 9 and 10. If two or more of
these three samples are found to be logical ones, the start
bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0-transition.
38
AT90S8515
If however, a valid start bit is detected, sampling of the data
bits following the start bit is performed. These bits are also
sampled at samples 8, 9 and 10. The logical value found in
at least two of the three samples is taken as the bit value.
All bits are shifted into the transmitter shift register as they
are sampled. Sampling of an incoming character is shown
in Figure 43.
AT90S8515
Figure 43. Sampling Received Data
When the stop bit enters the receiver, the majority of the
three samples must be one to accept the stop bit. If two or
more samples are logical zeros, the Framing Error (FE) flag
in the UART Status Register (USR) is set. Before reading
the UDR register, the user should always check the FE bit
to detect Framing Errors.
Whether or not a valid stop bit is detected at the end of a
character reception cycle, the data is transferred to UDR
and the RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one
for received data. When UDR is read, the Receive Data
register is accessed, and when UDR is written, the Transmit Data register is accessed. If 9 bit data word is selected
(the CHR9 bit in the UART Control Register, UCR is set),
the RXB8 bit in UCR is loaded with bit 9 in the Transmit
shift register when data is transferred to UDR.
If, after having received a character, the UDR register has
not been read since the last receive, the OverRun (OR) flag
in UCR is set. This means that the last data byte shifted
into to the shift register could not be transferred to UDR
and has been lost. The OR bit is buffered, and is updated
when the valid data byte in UDR is read. Thus, the user
should always check the OR bit after reading the UDR register in order to detect any overruns.
When the RXEN bit in the UCR register is cleared (zero),
the receiver is disabled. This means that the PD0 pin can
be used as a general I/O pin. When RXEN is set, the UART
Receiver will be connected to PD0, which is forced to be an
input pin regardless of the setting of the DDD0 bit in DDRD.
When PD0 is forced to input by the UART, the PORTD0 bit
can still be used to control the pull-up resistor on the pin.
UART Control
The UART I/O Data Register - UDR
Bit
7
6
5
4
3
2
1
0
$0C ($2C)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When
UDR
reading from UDR, the UART Receive Data register is
read.
The UART Status Register - USR
Bit
7
6
5
4
3
2
1
$0B ($2B)
RXC
TXC
UDRE
FE
OR
-
-
-
Read/Write
R
R/W
R
R
R
R
R
R
Initial value
0
0
1
0
0
0
0
0
The USR register is a read-only register providing information on the UART Status.
• Bit 7 - RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is
set regardless of any detected framing errors. When the
RXCIE bit in UCR is set, the UART Receive Complete
interrupt will be executed when RXC is set(one). RXC is
cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine
must read UDR in order to clear RXC, otherwise a new
interrupt will occur once the interrupt routine terminates.
• Bit 6 - TXC : UART Transmit Complete
This bit is set (one) when the entire character (including the
stop bit) in the Transmit Shift register has been shifted out
0
USR
and no new data has been written to UDR. This flag is
especially useful in half-duplex communications interfaces,
where a transmitting application must enter receive mode
and free the communications bus immediately after completing the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes
the UART Transmit Complete interrupt to be executed.
TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC
bit is cleared (zero) by writing a logical one to the bit.
• Bit 5 - UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is
transferred to the Transmit shift register. Setting of this bit
indicates that the transmitter is ready to receive a new
character for transmission.
39
When the UDRIE bit in UCR is set, the UART Transmit
Complete interrupt to be executed as long as UDRE is set.
UDRE is cleared by writing UDR. When interrupt-driven
data transmittal is used, the UART Data Register Empty
Interrupt routine must write UDR in order to clear UDRE,
otherwise a new interrupt will occur once the interrupt routine terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
• Bit 4 - FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e.
when the stop bit of an incoming character is zero.
The FE bit is cleared when the stop bit of received data is
one.
• Bit 3 - OR: Overrun
This bit is set if an Overrun condition is detected, i.e. when
a character already present in the UDR register is not read
before the next character has been shifted into the
Receiver Shift register. The OR bit is buffered, which
means that it will be set once the valid data still in UDRE is
read.
The OR bit is cleared (zero) when data is received and
transferred to UDR.
• Bits 2..0 - Res: Reserved bits
These bits are reserved bits in the AT90S8515 and will
always read as zero.
The UART Control Register - UCR
Bit
7
6
5
4
3
2
1
0
$0A ($2A)
RXCIE
TXCIE
UDRIE
RXEN
TXEN
CHR9
RXB8
TXB8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
W
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR
will cause the Receive Complete interrupt routine to be
executed provided that global interrupts are enabled.
• Bit 6 - TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR
will cause the Transmit Complete interrupt routine to be
executed provided that global interrupts are enabled.
• Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in USR
will cause the UART Data Register Empty interrupt routine
to be executed provided that global interrupts are enabled.
• Bit 4 - RXEN: Receiver Enable
This bit enables the UART receiver when set (one). When
the receiver is disabled, the TXC, OR and FE status flags
cannot become set. If these flags are set, turning off RXEN
does not cause them to be cleared.
• Bit 3 - TXEN: Transmitter Enable
This bit enables the UART transmitter when set (one).
When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in
the shift register plus any following character in UDR has
been completely transmitted.
• Bit 2 - CHR9: 9 Bit Characters
When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is
read and written by using the RXB8 and TXB8 bits in UCR,
respectively. The 9th data bit can be used as an extra stop
bit or a parity bit.
• Bit 1 - RXB8: Receive Data Bit 8
When CHR9 is set (one), RXB8 is the 9th data bit of the
received character.
40
AT90S8515
UCR
• Bit 0 - TXB8: Transmit Data Bit 8
When CHR9 is set (one), TXB8 is the 9th data bit in the
character to be transmitted.
The BAUD Rate Generator
The baud rate generator is a frequency divider which generates baud-rates according to the following equation:
f CK
BAUD = ------------------------------------16(UBRR + 1)
• BAUD = Baud-Rate
• fck= Crystal Clock frequency
• UBRR= Contents of the UART Baud Rate register,
UBRR (0-255)
For standard crystal frequencies, the most commonly used
baud rates can be generated by using the UBRR settings in
Table 16. UBRR values which yield an actual baud rate differing less than 2% from the target baud rate, are bolded in
the table.
AT90S8515
Table 16. UBRR Settings at Various Crystal Frequencies
Baud Rate
1 MHz %Error 1.8432 MHz %Error
2 MHz %Error 2.4576 MHz %Error
2400 UBRR=
25
0.2 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
63
0.0
UBRR=
UBRR=
UBRR=
UBRR=
4800
12
0.2
23
0.0
25
0.2
31
0.0
6
7.5 UBRR=
9600 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
15
0.0
3
7.8 UBRR=
8
3.7 UBRR=
10
3.1
14400 UBRR=
7
0.0 UBRR=
2
7.8 UBRR=
6
7.5 UBRR=
19200 UBRR=
5
0.0 UBRR=
7
0.0
1
7.8 UBRR=
3
7.8 UBRR=
4
6.3
28800 UBRR=
3
0.0 UBRR=
1
22.9 UBRR=
2
7.8 UBRR=
38400 UBRR=
2
0.0 UBRR=
3
0.0
0
7.8 UBRR=
1
7.8 UBRR=
2
12.5
57600 UBRR=
1
0.0 UBRR=
0
22.9 UBRR=
1
33.3 UBRR=
1
22.9 UBRR=
76800 UBRR=
1
0.0
0
84.3 UBRR=
0
7.8 UBRR=
0
25.0
115200 UBRR=
0
0.0 UBRR=
Baud Rate 3.2768 MHz %Error 3.6864 MHz %Error
4 MHz %Error
4.608 MHz %Error
2400 UBRR=
84
0.4 UBRR=
95
0.0 UBRR= 103
0.2 UBRR= 119
0.0
4800 UBRR=
42
0.8 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0
9600 UBRR=
20
1.6 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
29
0.0
UBRR=
UBRR=
UBRR=
16
2.1
UBRR=
14400
13
1.6
15
0.0
19
0.0
10
3.1 UBRR=
19200 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
14
0.0
8
3.7 UBRR=
28800 UBRR=
6
1.6 UBRR=
7
0.0 UBRR=
9
0.0
4
6.3 UBRR=
6
7.5 UBRR=
7
6.7
38400 UBRR=
5
0.0 UBRR=
3
12.5 UBRR=
3
7.8 UBRR=
57600 UBRR=
3
0.0 UBRR=
4
0.0
UBRR=
2
12.5
UBRR=
UBRR=
2
7.8
UBRR=
3
6.7
76800
2
0.0
1
12.5 UBRR=
1
7.8 UBRR=
2
20.0
115200 UBRR=
1
0.0 UBRR=
Baud Rate 7.3728 MHz %Error
8 MHz %Error
9.216 MHz %Error 11.059 MHz %Error
2400 UBRR= 191
0.0 UBRR= 207
0.2 UBRR= 239
0.0 UBRR= 287
4800 UBRR=
95
0.0 UBRR= 103
0.2 UBRR= 119
0.0 UBRR= 143
0.0
9600 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0 UBRR=
71
0.0
14400 UBRR=
31
0.0 UBRR=
34
0.8 UBRR=
39
0.0 UBRR=
47
0.0
19200 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
29
0.0 UBRR=
35
0.0
16
2.1 UBRR=
28800 UBRR=
15
0.0 UBRR=
19
0.0 UBRR=
23
0.0
38400 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
14
0.0 UBRR=
17
0.0
8
3.7 UBRR=
57600 UBRR=
7
0.0 UBRR=
9
0.0 UBRR=
11
0.0
6
7.5 UBRR=
7
6.7 UBRR=
76800 UBRR=
5
0.0 UBRR=
8
0.0
3
7.8 UBRR=
115200 UBRR=
3
0.0 UBRR=
4
0.0 UBRR=
5
0.0
The UART BAUD Rate Register - UBRR
Bit
7
6
5
4
3
2
1
0
$09 ($29)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
UBRR
The UBRR register is an 8-bit read/write register which specifies the UART Baud Rate according to the equation on the
previous page.
41
The Analog Comparator
The analog comparator compares the input values on the
positive pin PB2 (AIN0) and negative pin PB3 (AIN1).
When the voltage on the positive pin PB2 (AIN0) is higher
than the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input
Capture function. In addition, the comparator can trigger a
separate interrupt, exclusive to the Analog Comparator.
The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator
and its surrounding logic is shown in Figure 44.
Figure 44. Analog Comparator Block Diagram
The Analog Comparator Control And Status Register - ACSR
Bit
7
6
5
4
3
2
1
0
$08 ($28)
ACD
-
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bit 7 - ACD: Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off
the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit,
the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur
when the bit is changed.
• Bit 6 - Res: Reserved bit
This bit is a reserved bit in the AT90S8515 and will always
read as zero.
• Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The
Analog Comparator Interrupt routine is executed if the
ACIE bit is set (one) and the I-bit in SREG is set (one). ACI
is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by
writing a logic one to the flag.
42
AT90S8515
ACSR
• Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status
Register is set (one), the analog comparator interrupt is
activated. When cleared (zero), the interrupt is disabled.
• Bit 2 - ACIC: Analog Comparator Input Capture Enable
When set (one), this bit enables the Input Capture function
in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the
comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
cleared (zero), no connection between the analog comparator and the Input Capture function is given. To make the
comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register
(TIMSK) must be set (one).
AT90S8515
• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode
Select
These bits determine which comparator events that trigger
the Analog Comparator interrupt. The different settings are
shown in Table 17.
Table 17. ACIS1/ACIS0 Settings
ACIS1
ACIS0
0
0
Comparator Interrupt on Output Toggle
0
1
Reserved
1
0
Comparator Interrupt on Falling Output
Edge
1
1
Comparator Interrupt on Rising Output
Edge
Note:
Interrupt Mode
When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an
interrupt can occur when the bits are changed.
Three data memory address locations are allocated for the
Port A, one each for the Data Register - PORTA, $1B($3B),
Data Direction Register - DDRA, $1A($3A) and the Port A
Input Pins - PINA, $19($39). The Port A Input Pins address
is read only, while the Data Register and the Data Direction
Register are read/write.
All port pins have individually selectable pull-up resistors.
The PORT A output buffers can sink 20mA and thus drive
LED displays directly. When pins PA0 to PA7 are used as
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
The PORT A pins have alternate functions related to the
optional external data SRAM. PORT A can be configured to
be the multiplexed low-order address/data bus during
accesses to the external data memory. In this mode, PORT
A has internal pull-up resistors.
When PORT A is set to the alternate function by the SRE External SRAM Enable - bit in the MCUCR - MCU Control
Register, the alternate settings override the data direction
register.
I/O-Ports
Port A
PORT A is an 8-bit bi-directional I/O port.
The Port A Data Register - PORTA
Bit
7
6
5
4
3
2
1
0
$1B ($3B)
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
PORTA
The Port A Data Direction Register - DDRA
Bit
7
6
5
4
3
2
1
0
$1A ($3A)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
DDRA
The Port A Input Pins Address - PINA
Bit
7
6
5
4
3
2
1
0
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Read/Write
R
R
R
R
R
R
R
R
Initial value
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
$19 ($39)
The Port A Input Pins address - PINA - is not a register,
and this address enables access to the physical value on
each Port A pin. When reading PORTA the PORTA Data
Latch is read, and when reading PINA, the logical values
present on the pins are read.
PINA
is configured as an input pin. If PORTAn is set (one) when
the pin configured as an input pin, the MOS pull up resistor
is activated. To switch the pull up resistor off, the PORTAn
has to be cleared (zero) or the pin has to be configured as
an output pin.
Port A As General Digital I/O
All 8 bits in PORT A are equal when used as digital I/O
pins.
PAn, General I/O pin: The DDAn bit in the DDRA register
selects the direction of this pin, if DDAn is set (one), PAn is
configured as an output pin. If DDAn is cleared (zero), PAn
43
Table 18. DDAn Effects on PORT A Pins
DDAn
PORTAn
I/O
Pull up
Comment
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PAn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
n: 7,6…0, pin number.
Port A Schematics
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Figure 45. PORTA Schematic Diagrams (Pins PA0 - PA7)
Port B
Port B is an 8-bit bi-directional I/O port.
Three data memory address locations are allocated for the
Port B, one each for the Data Register - PORTB, $18($38),
Data Direction Register - DDRB, $17($37) and the Port B
Input Pins - PINB, $16($36). The Port B Input Pins address
is read only, while the Data Register and the Data Direction
Register are read/write.
All port pins have individually selectable pull-up resistors.
The Port B output buffers can sink 20mA and thus drive
LED displays directly. When pins PB0 to PB7 are used as
44
AT90S8515
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
The Port B pins with alternate functions are shown in the
following table:
AT90S8515
Table 19. Port B Pins Alternate Functions
Port Pin
Alternate Functions
PB0
T0 (Timer/Counter 0 external counter input)
PB1
T1 (Timer/Counter 1 external counter input)
PB2
AIN0 (Analog comparator positive input)
PB3
AIN1 (Analog comparator negative input)
PB4
SS (SPI Slave Select input)
PB5
MOSI (SPI Bus Master Output/Slave Input)
PB6
MISO (SPI Bus Master Input/Slave Output)
PB7
SCK (SPI Bus Serial Clock)
When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate
function description.
The Port B Data Register - PORTB
Bit
7
6
5
4
3
2
1
0
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$18 ($38)
PORTB
The Port B Data Direction Register - DDRB
Bit
7
6
5
4
3
2
1
0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$17 ($37)
DDRB
The Port B Input Pins Address - PINB
Bit
7
6
5
4
3
2
1
0
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R
R
R
R
R
R
R
R
Initial value
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
$16 ($36)
The Port B Input Pins address - PINB - is not a register,
and this address enables access to the physical value on
each Port B pin. When reading PORTB, the PORTB Data
Latch is read, and when reading PINB, the logical values
present on the pins are read.
PortB As General Digital I/O
All 8 bits in port B are equal when used as digital I/O pins.
PINB
PBn, General I/O pin: The DDBn bit in the DDRB register
selects the direction of this pin, if DDBn is set (one), PBn is
configured as an output pin. If DDBn is cleared (zero), PBn
is configured as an input pin. If PORTBn is set (one) when
the pin configured as an input pin, the MOS pull up resistor
is activated. To switch the pull up resistor off, the PORTBn
has to be cleared (zero) or the pin has to be configured as
an output pin.
Table 20. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
Pull up
Comment
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PBn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
n: 7,6…0, pin number.
45
Alternate Functions of PortB
The alternate pin configuration is as follows:
SCK - PORTB, Bit 7
SCK: Master clock output, slave clock input pin for SPI
channel. When the SPI is enabled as a slave, this pin is
configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a master, the data direction of
this pin is controlled by DDB7. When the pin is forced to be
an input, the pull-up can still be controlled by the PORTB7
bit. See the description of the SPI port for further detatils.
MISO - PORTB, Bit 6
MISO: Master data input, slave data output pin for SPI
channel. When the SPI is enabled as a master, this pin is
configured as an input regardless of the setting of DDB6.
When the SPI is enabled as a slave, the data direction of
this pin is controlled by DDB6. When the pin is forced to be
an input, the pull-up can still be controlled by the PORTB6
bit. See the description of the SPI port for further detatils.
MOSI - PORTB, Bit 5
MOSI: SPI Master data output, slave data input for SPI
channel. When the SPI is enabled as a slave, this pin is
configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a master, the data direction of
this pin is controlled by DDB5. When the pin is forced to be
an input, the pull-up can still be controlled by the PORTB5
bit. See the description of the SPI port for further detatils.
SS - PORTB, Bit 4
SS: Slave port select input. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the
setting of DDB5. As a slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a master, the
46
AT90S8515
data direction of this pin is controlled by DDB5. When the
pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI
port for further detatils.
AIN1 - PORTB, Bit 3
AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is cleared (zero)) and with the
internal MOS pull up resistor switched off (PB3 is cleared
(zero)), this pin also serves as the negative input of the onchip analog comparator.
AIN0 - PORTB, Bit 2
AIN0, Analog Comparator Positive Input. When configured
as an input (DDB2 is cleared (zero)) and with the internal
MOS pull up resistor switched off (PB2 is cleared (zero)),
this pin also serves as the positive input of the on-chip analog comparator.
T1 - PORTB, Bit 1
T1, Timer/Counter1 counter source. See the timer description for further details
T0 - PORTB, Bit 0
T0: Timer/Counter0 counter source. See the timer description for further details.
Port B Schematics
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
AT90S8515
Figure 46. PORTB Schematic Diagram (Pins PB0 and PB1)
Figure 47. PORTB Schematic Diagram (Pins PB2 and PB3)
47
Figure 48. PORTB Schematic Diagram (Pin PB4)
RD
MOS
PULLUP
RESET
Q
D
DDB4
C
DATA BUS
WD
RESET
Q
D
PORTB4
C
PB4
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
MSTR:
SPE:
MSTR
SPE
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI MASTER ENABLE
SPI ENABLE
SPI SS
Figure 49. PORTB Schematic Diagram (Pin PB5)
RD
MOS
PULLUP
RESET
Q
R
D
DDB5
WD
RESET
R
Q
D
PORTB5
PB5
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI MASTER
OUT
SPI SLAVE
IN
48
AT90S8515
AT90S8515
Figure 50. PORTB Schematic Diagram (Pin PB6)
RD
MOS
PULLUP
RESET
R
Q
D
DDB6
WD
RESET
R
Q
D
PORTB6
PB6
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI SLAVE
OUT
SPI MASTER
IN
Figure 51. PORTB Schematic Diagram (Pin PB7)
RD
MOS
PULLUP
RESET
Q
R
D
DDB7
WD
RESET
R
Q
D
PORTB7
PB7
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI ClLOCK
OUT
SPI CLOCK
IN
49
Port C
PORT C is an 8-bit bi-directional I/O port.
Three data memory address locations are allocated for the
Port C, one each for the Data Register - PORTC, $15($35),
Data Direction Register - DDRC, $14($34) and the Port C
Input Pins - PINC, $13($33). The Port C Input Pins address
is read only, while the Data Register and the Data Direction
Register are read/write.
All port pins have individually selectable pull-up resistors.
The PORT C output buffers can sink 20mA and thus drive
LED displays directly. When pins PC0 to PC7 are used as
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
The PORT C pins have alternate functions related to the
optional external data SRAM. PORT C can be configured
to be the high-order address byte during accesses to external data memory.
When PORT C is set to the alternate function by the SRE External SRAM Enable - bit in the MCUCR - MCU Control
Register, the alternate settings override the data direction
register.
The Port C Data Register - PORTC
Bit
7
6
5
4
3
2
1
0
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$15 ($35)
PORTC
The Port C Data Direction Register - DDRC
Bit
7
6
5
4
3
2
1
0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$14 ($34)
DDRC
The Port C Input Pins Address - PINC
Bit
7
6
5
4
3
2
1
0
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
R
R
R
R
R
R
R
R
Initial value
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
$13 ($33)
The Port C Input Pins address - PINC - is not a register,
and this address enables access to the physical value on
each Port C pin. When reading PORTC, the PORTC Data
Latch is read, and when reading PINC, the logical values
present on the pins are read.
PortC As General Digital I/O
All 8 bits in PORT C are equal when used as digital I/O
pins.
Table 21. DDCn Effects on PORT C Pins
50
PCn, General I/O pin: The DDCn bit in the DDRC register
selects the direction of this pin, if DDCn is set (one), PCn is
configured as an output pin. If DDCn is cleared (zero), PCn
is configured as an input pin. If PORTCn is set (one) when
the pin configured as an input pin, the MOS pull up resistor
is activated. To switch the pull up resistor off, PORTCn has
to be cleared (zero) or the pin has to be configured as an
output pin.
DDCn
PORTCn
I/O
Pull up
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PCn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
n: 7…0, pin number
AT90S8515
PINC
Comment
AT90S8515
Port C Schematics
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Figure 52. PORTC Schematic Diagram (Pins PC0 - PC7)
Port D
Port D is an 8 bit bi-directional I/O port with internal pull-up
resistors.
Three data memory address locations are allocated for the
Port D, one each for the Data Register - PORTD, $12($32),
Data Direction Register - DDRD, $11($31) and the Port D
Input Pins - PIND, $10($30). The Port D Input Pins address
is read only, while the Data Register and the Data Direction
Register are read/write.
The Port D output buffers can sink 20 mA. As inputs, Port D
pins that are externally pulled low will source current if the
pull-up resistors are activated.
Some Port D pins have alternate functions as shown in the
following table:
Table 22. Port D Pins Alternate Functions
Port Pin
Alternate Function
PD0
RDX (UART Input line )
PD1
TDX (UART Output line)
PD2
INT0 (External interrupt 0 input)
PD3
INT1 (External interrupt 1 input)
PD5
OC1A (Timer/Counter1 Output compareA match output)
PD6
WR (Write strobe to external memory)
PD7
RD (Read strobe to external memory)
When the pins are used for the alternate function the
DDRD and PORTD register has to be set according to the
alternate function description.
51
The Port D Data Register - PORTD
Bit
7
6
5
4
3
2
1
0
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$12 ($32)
PORTD
The Port D Data Direction Register - DDRD
Bit
7
6
5
4
3
2
1
0
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$11 ($31)
DDRD
The Port D Input Pins Address - PIND
Bit
7
6
5
4
3
2
1
0
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
R
R
R
R
R
R
R
R
Initial value
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
$10 ($30)
The Port D Input Pins address - PIND - is not a register,
and this address enables access to the physical value on
each Port D pin. When reading PORTD, the PORTD Data
Latch is read, and when reading PIND, the logical values
present on the pins are read.
PIND
PortD As General Digital I/O
PDn, General I/O pin: The DDDn bit in the DDRD register
selects the direction of this pin. If DDDn is set (one), PDn is
configured as an output pin. If DDDn is cleared (zero), PDn
is configured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull up resistor is activated.
To switch the pull up resistor off the PDn has to be cleared
(zero) or the pin has to be configured as an output pin.
Table 23. DDDn Bits on Port D Pins
DDDn
PORTDn
I/O
Pull up
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PDn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
n: 7,6…0, pin number.
Alternate Functions Of PORTD
RD - PORTD, Bit 7
RD is the external data memory read control strobe.
WR - PORTD, Bit 6
WR is the external data memory write control strobe.
OC1- PORTD, Bit 5
OC1, Output compare match output: The PD5 pin can
serve as an external output when the Timer/Counter1 compare matches. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. See the
Timer/Counter1 description for further details, and how to
enable the output. The OC1 pin is also the output pin for
the PWM mode timer function.
INT1 - PORTD, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve
as an external interrupt source to the MCU. See the inter-
52
AT90S8515
Comment
rupt description for further details, and how to enable the
source.
INT0 - PORTD, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve
as an external interrupt source to the MCU. See the interrupt description for further details, and how to enable the
source.
TXD - PORTD, Bit 1
Transmit Data (Data output pin for the UART). When the
UART transmitter is enabled, this pin is configured as an
output regardless of the value of DDRD1.
RXD - PORTD, Bit 0
Receive Data (Data input pin for the UART). When the
UART receiver is enabled this pin is configured as an output regardless of the value of DDRD0. When the UART
forces this pin to be an input, a logical one in PORTD0 vill
turn on the internal pull-up.
AT90S8515
PortD Schematics
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 53. PORTD Schematic Diagram (Pin PD0)
RD
MOS
PULLUP
RESET
Q
D
DDD0
C
DATA BUS
WD
RESET
Q
D
PORTD0
C
PD0
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
RXD:
RXEN:
RXEN
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART RECEIVE DATA
UART RECEIVE ENABLE
RXD
Figure 54. PORTD Schematic Diagram (Pin PD1)
RD
MOS
PULLUP
RESET
Q
R
D
DDD1
C
DATA BUS
WD
RESET
R
Q
D
PORTD1
PD1
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
TXD:
TXEN:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART TRANSMIT DATA
UART TRANSMIT ENABLE
TXEN
TXD
53
Figure 55. PORTD Schematic Diagram (Pins PD2 and PD3)
Figure 56. PORTD Schematic Diagram (Pin PD4)
54
AT90S8515
AT90S8515
Figure 57. PORTD Schematic Diagram (Pin PD5)
Figure 58. PORTD Schematic Diagram (Pin PD6)
55
Figure 59. PORTD Schematic Diagram (Pin PD7)
Memory Programming
Program Memory Lock Bits
The AT90S8515 MCU provides two lock bits which can be
left unprogrammed (‘1’) or can be programmed (‘0’) to
obtain the additional features listed in Table 24.
Table 24. Lock Bit Protection Modes
Program Lock Bits
Protection Type
Mode
LB1
LB2
1
1
1
No program lock features
2
0
1
Further programming of the Flash
and EEPROM is disabled
3
0
0
Same as mode 2, but verify is also
disabled.
Note:
The Lock Bits can only be erased with the Chip Erase
operation.
Fuse Bits
The AT90S8515 has two fuse bits, SPIEN and FSTRT.
• When SPIEN is programmed (‘0’), Serial Program
Downloading is enabled. Default value is programmed
(‘0’).
• When FSTRT is programmed (‘0’), the short start-up
time is selected. Default value is unprogrammed (‘1’).
56
AT90S8515
Parts with this bit pre-programmed (‘0’) can be delivered
on demand.
These bits are not accessible in Serial Programming Mode
and are not affected by a chip erase.
Signature Bytes
All Atmel microcontrollers have a three-byte signature code
which identifies the device. This code can be read in both
seria(1)land parallel mode. The three bytes reside in a separate address space, and for the AT90S8515 they are:
1. $00: $1E (indicates manufactured by Atmel)
2. $01: $93 (indicates 8kB Flash memory)
3. $02: $01 (indicates 90S8515 device when $01 is
$93)
Note:
1.
When both lock bits are programmed (lock mode 3),
the signature bytes can not be read in serial mode
Programming the Flash and EEPROM
Atmel’s AT90S8515 offers 8K bytes of in-system reprogrammable Flash Program memory and 512 bytes of
EEPROM Data memory.
The AT90S8515 is normally shipped with the on-chip Flash
Program and EEPROM Data memory arrays in the erased
state (i.e. contents = $FF) and ready to be programmed.
This device supports a High-Voltage (12V) Parallel programming mode and a Low-Voltage Serial programming
AT90S8515
mode. The +12V is used for programming enable only, and
no current of significance is drawn by this pin. The serial
programming mode provides a convenient way to download the Program and Data into the AT90S8515 inside the
user’s system.
The Program and Data memory arrays on the AT90S8515
are programmed byte-by-byte in either programming
modes. For the EEPROM, an auto-erase cycle is provided
with the self-timed programming operation in the serial programming mode.
Parallel Programming
This section describes how to parallel program and verify
Flash Program memory, EEPROM Data memory + Program Memory Lock bits and Fuse bits in the AT90S8515.
Figure 60. Parallel Programming
The XA1/XA0 bits determine the action taken when the
XTAL1 pin is given a positive pulse. The bit settings are
shown in the following table:
Table 26. XA1 and XA0 Coding
XA1
XA0
Action when XTAL1 is Pulsed
0
0
Load Flash or EEPROM Address (High or Low
address byte for Flash determined by BS)
0
1
Load Data (High or Low data byte for Flash
determined by BS)
1
0
Load Command
1
1
No Action, Idle
When pulsing WR or OE, the command loaded determines
the action on input or output. The command is a byte where
the different bits are assigned functions as shown in the following table:
Table 27. Command Byte Bit Coding
Bit#
Signal Names
In this section, some pins of the AT908515 are referenced
by signal names describing their functionality during parallel programming rather than their pin names. Pins not
described in the following table are referenced by pin
names.
Table 25. Pin Name Mapping
Signal Name in
Programming
Mode
Pin
Name
I/O
Function
RDY / BSY
PD1
O
0: Device is busy
programming, 1: Device is
ready for new command
OE
PD2
I
Output Enable (Active Low)
WR
PD3
I
Write Pulse (Active Low)
BS
PD4
I
Byte Select
XA0
PD5
I
XTAL Action Bit 0
XA1
PD6
I
XTAL Action Bit 1
Meaning when Set
7
Chip Erase
6
Write Fuse Bits. Located in the data byte at the
following bit positions: D5–SPIEN Fuse, D0–FSTRT
Fuse (Note: Write ‘0’ to program, ‘1’ to erase)
5
Write Lock Bits. Located in the data byte at the
following bit positions: D1–LB1, D0: LB2 (Note:
write ‘0’ to program)
4
Write Flash or EEPROM (determined by bit 0)
3
Read signature row
2
Read Lock and Fuse Bits. Located in the data byte
at the following bits positions: D7–LB1, D6–LB2,
D5–SPIEN Fuse, D0: FSTRT Fuse (Note: ‘0’
means programmed)
1
Read from Flash or EEPROM (determined by bit 0)
0
0: Flash Access, 1: EEPROM Access
Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 4.5 - 5.5 V between VCC and GND.
2. Set RESET and BS pins to ‘0’ and wait at least
100 ns.
3. Apply 11.5 - 12.5V to RESET. Any activity on BS
within 100 ns after +12V has been applied to
RESET will cause the device to fail entering programming mode.
57
Chip Erase
The chip erase will erase the Flash and EEPROM memories plus Lock bits. The lock bits are not reset until the program memory has been completely erased. The Fuse bits
are not changed. A chip erase must be performed before
the Flash is programmed.
Load Command “Chip Erase”
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set BS to ‘0’.
3. Set PB(7:0) to ‘1000 0000’. This is the command for
Chip erase.
4. Give XTAL1 a positive pulse. This loads the command, and starts the erase of the Flash and
EEPROM arrays. After pulsing XTAL1, give WR a
negative pulse to enable lock bit erase at the end of
the erase cycle, then wait for at least 10 ms. Chip
erase does not generate any activity on the
RDY/BSY pin.
Programming The Flash
Load Command “Program Flash”
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set BS to ‘0’
3. Set PB(7:0) to ‘0001 0000’. This is the command for
Flash programming.
4. Give XTAL1 a positive pulse. This loads the command.
Load Address Low byte
1. Set XA1, XA0 to ‘00’. This enables address loading.
2. Set BS to ‘0’. This selects Low address.
3. Set PB(7:0) = Address Low byte ($00 - $FF)
4. Give XTAL1 a positive pulse. This loads the Address
Low byte.
58
AT90S8515
Load Address High byte
1. Set XA1, XA0 to ‘00’. This enables address loading.
2. Set BS to ‘1’. This selects High address.
3. Set PB(7:0) = Address High byte ($00 - $0F)
4. Give XTAL1 a positive pulse. This loads the Address
High byte.
Load Data byte
1. Set XA1, XA0 to ‘01’. This enables data loading.
2. Set PB(7:0) = Data Low byte ($00 - $FF)
3. Give XTAL1 a positive pulse. This loads the Data
byte.
Write Data Low byte
1. Set BS to (‘0’).
2. Give WR a negative pulse. This starts programming
of the data byte. RDY/BSY goes low.
3. Wait until RDY/BSY goes high to program the next
byte.
Load Data byte
1. Set XA1, XA0 to ‘01’. This enables data loading.
2. Set PB(7:0) = Data High byte ($00 - $FF)
3. Give XTAL1 a positive pulse. This loads the Data
byte.
Write Data High byte
1. Set BS to ‘1’.
2. Give WR a negative pulse. This starts programming
of the data byte. RDY / BSY goes low.
3. Wait until RDY / BSY goes high to program the next
byte.
The loaded command and address are retained in the
device during programming. To simplify programming, the
following should be considered.
• The command for Flash programming needs only be
loaded before programming of the first byte.
• Address High byte needs only be loaded before
programming a new 256 word page in the Flash.
AT90S8515
Figure 61. Programming Flash Low Byte
PB0 - PB7
$10
ADDR. LOW
ADDR. HIGH
DATA LOW
XA1
XA2
BS
XTAL 1
WR
RDY/BSY
RESET +12V
OE
Figure 62. Programming Flash High Byte
PB0 - PB7
DATA HIGH
XA1
XA0
BS
XTAL1
WR
RDY/BSY
RESET
+12V
OE
59
Programming The EEPROM
The programming algorithm for the EEPROM data memory
is as follows (refer to Flash Programming for details on
Command, Address and Data loading):
1. Load Command ‘0001 0001’.
2. Load Low EEPROM Address ($00 - $FF)
3. Load High EEPROM Address ($00 - $01)
4. Load Low EEPROM Data ($00 - $FF)
5. Give WR a negative pulse and wait for RDY/BSY to
go high.
The Command needs only be loaded before programming
the first byte.
Reading The Flash
The algorithm for reading the Flash memory is as follows
(refer to Flash Programming for details on Command,
Address and Data loading):
1. Load Command ‘0000 0010’.
2. Load Low Address ($00 - $FF)
3. Load High Address ($00 - $0F)
4. Set OE to ‘0’, and BS to ‘0’. The Low Data byte can
now be read at PB(7:0)
5. Set BS to ‘1’. The High Data byte can now be read
from PB(7:0)
6. Set OE to ‘1’.
The Command needs only be loaded before reading the
first byte.
Reading The EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Flash Programming for details on Command,
Address and Data loading):
1. Load Command ‘0000 0011’.
2. Load Low EEPROM Address ($00 - $FF)
3. Load High EEPROM Address ($00 - $01)
4. Set OE to ‘0’, and BS to ‘0’. The EEPROM Data
byte can now be read at PB(7:0)
5. Set OE to ‘1’.
The Command needs only be loaded before reading the
first byte.
Programming The Fuse Bits
The algorithm for programming the Fuse bits is as follows
(refer to Flash Programming for details on Command,
Address and Data loading):
60
AT90S8515
1. Load Command ‘0100 0000’.
2. Load Data.
Bit 5 = ‘0’ programs the SPIEN Fuse bit. Bit 5 = ‘1’
erases the SPIEN Fuse bit.
Bit 0 = ‘0’ programs the FSTRT fuse bit. Bit 5 = ‘1’
erases the FSTRT fuse bit.
3. Give WR a negative pulse and wait for RDY/BSY to
go high.
Programming The Lock Bits
The algorithm for programming the Lock bits is as follows
(refer to Flash Programming for details on Command,
Address and Data loading):
1. Load Command ‘0010 0000’.
2. Load Data.
Bit 2 = ’0’ programs Lock Bit2
Bit 1 = ’0’ programs Lock Bit1
3. Give WR a negative pulse and wait for RDY/BSY to
go high.
The lock bits can only be cleared by executing a chip
erase.
Reading The Fuse And Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to Flash Programming for details on Command,
Address and Data loading):
1. Load Command ‘0000 0100’.
2. Set OE to ‘0’, and BS to ‘1’. The Status of Fuse and
Lock bits can now be read at PB(7:0)
Bit 7: Lock Bit1 (‘0’ means programmed)
Bit 6: Lock Bit2 (‘0’ means programmed)
Bit 5: SPIEN Fuse (‘0’ means programmed, ‘1’
means erased)
Bit 0: FSTRT Fuse (‘0’ means programmed, ‘1’
means erased)
3. Set OE to ‘1’.
Observe especially that BS needs to be set to ‘1’.
Reading The Signature Bytes
The algorithm for reading the Signature Bytes bits is as follows (refer to Flash Programming for details on Command,
Address and Data loading):
1. Load Command ‘0000 1000’.
2. Load Low address ($00 - $02)
3. Set OE to ‘0’, and BS to ‘0’. The Selected Signature
byte can now be read at PB(7:0)
4. Set OE to ‘1’.
The command needs only be programmed before reading
the first byte.
AT90S8515
Parallel Programming Characteristics
Figure 63. Parallel Programming Timing
tXHXL
XTAL1
tXHDX tBVWL
tDVXH
tWLWH
tXLWL
WR
Write
Data & Contol
(PB0-7, XA0/1, BS)
tWHRL
RDY/BSY
OE
tXLOL
Read
tWLRH
tOLDV
Data
Table 28. Parallel Programming Characteristics
TA = 21°C to 27°C, VCC = 4.5 - 5.5V
Symbol
Parameter
Min
tDVXH
Data and Control Setup before XTAL1 High
67
ns
tXHXL
XTAL1 Pulse Width High
67
ns
tXLDH
Data and Control Hold after XTAL1 High
67
ns
tBVWL
BS Valid to WR Low
67
ns
tWLWH
WR Pulse Width Low
67
ns
(1)
tWHRL
WR High to RDY/BSY Low
tXLOL
XTAL1 Low to OE Low
tOLDV
OE Low to Data Valid
tWLRH
Note:
Typ
Max
20
ns
67
ns
20
(1)
WR Low to RDY/BSY High
0.5
Units
0.7
ns
0.9
ms
1. If tWPWL is held longer than tWLRH, no RDY/BSY pulse will be seen.
61
Serial Downloading
Both the Program and Data memory arrays can be programmed using the serial SPI bus while RESET is pulled to
GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed.
When programming the EEPROM, an auto-erase cycle is
built into the self-timed programming operation (in the
serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the
content of every memory location in both the Program and
EEPROM arrays into $FF.
The Program and EEPROM memory arrays have separate
address spaces:
$0000 to $0FFF for Program memory and $0000 to $01FF
for EEPROM memory.
Either an external system clock is supplied at pin XTAL1 or
a crystal needs to be connected across pins XTAL1 and
XTAL2.The minimum low and high periods for the serial
clock (SCK) input are defined as follows:
Low:> 2 XTAL1 clock cycle
High:> 2 XTAL1 clock cycles
Data Polling
When a new byte has been written and is being programmed into the Flash or EEPROM, reading the address
location being programmed will give the value $7F. At the
time the device is ready for a new byte, the programmed
value will read correctly. This is used to determine when
the next byte can be written. This will not work for the value
$7F, so when programming this value, the user will have to
wait for at least 4 ms before programming the next byte. As
a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can
be skipped. This does not apply if the EEPROM is re-programmed without chip-erasing the device. In this case,
data polling cannot be used for the values $7F and $FF,
and the user will have to wait at least 4ms before programming the next byte.
Serial Programming Algorithm
To program and verify the AT90S8515 in the serial programming mode, the following sequence is recommended
(See four byte instruction formats in Table 29):
1. Power-up sequence:
Apply power between VCC and GND while RESET and
SCK are set to ‘0’. If a crystal is not connected across
pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer can not
guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to
‘0’.
62
AT90S8515
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial
instruction to pin MOSI/PB5.
3. When issuing the third byte in Programming Enable,
the value sent as byte number two ($53), will echo
back during transmission of byte number three. In
any case, all four bytes in programming enable must
be transmitted. If the $53 did not echo back, give
SCK a positive pulse and issue a new Programming
Enable command. If the $53 is not seen within 32
attempts, there is no functional device connected.
4. If a chip erase is performed (must be done to erase
the Flash), wait 10 ms, give RESET a positive
pulse, and start over from Step 2.
5. The Flash or EEPROM array is programmed one
byte at a time by supplying the address and data
together with the appropriate Write instruction. An
EEPROM memory location is first automatically
erased before new data is written. Use Data Polling
to detect when the next byte in the Flash or
EEPROM can be written. In a chip erased device,
no $FFs in the data file(s) need to be programmed.
When programming locations with $7F, wait 4 ms
before writing the next byte.
6. Any memory location can be verified by using the
Read instruction which returns the content at the
selected address at serial output MISO/PB6.
7. At the end of the programming session, RESET can
be set high to commence normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to ‘0’ (if a crystal is not used).
Set RESET to ‘1’.
Turn VCC power off
AT90S8515
Table 29. Serial Programming Instruction Set
Instruction
Instruction Format
Operation
Byte 1
Byte 2
Byte 3
Byte4
Programming Enable
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
Enable Serial Programming after
RESET goes low.
Chip Erase
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Chip erase both 8K & 512byte
memory arrays
0010 H000
xxxx aaaa
bbbb bbbb
oooo oooo
Write Program Memory
0100 H000
xxxx aaaa
bbbb bbbb
iiii iiii
Write H(high or low) data i to Program
memory at word address a:b
Read EEPROM
Memory
1010 0000
xxxx xxx0
bbbb bbbb
oooo oooo
Read data o from EEPROM memory
at address a:b
Write EEPROM
Memory
1100 0000
xxxx xxx0
bbbb bbbb
iiii iiii
Write data i to EEPROM memory at
address a:b
Write Lock Bits
1010 1100
111x x21x
xxxx xxxx
xxxx xxxx
Write lock bits. Set bits 1,2=’0’ to
program lock bits.
Read Device Code
0011 0000
xxxx xxxx
xxxx xxbb
oooo oooo
Read Device Code o at address b
Read Program Memory
Note:
a = address high bits
b = address low bits
H = 0 - Low byte, 1 - High Byte
o = data out
Read H(high or low) data o from
Program memory at word address
a:b
i = data in
x = don’t care
1 = lock bit 1
2 = lock bit 2
Figure 64. Serial Programming and Verify
When writing serial data to the AT90S8515, data is clocked
on the rising edge of CLK.
When reading data from the AT90S8515, data is clocked
on the falling edge of CLK. See Figure 65 for an explanation.
63
Figure 65. Serial Programming Waveforms
Serial Programming Characteristics
Figure 66. Serial Programming Timing
MOSI
tSHOX
tOVSH
SCK
tSLSH
tSHSL
MISO
tSLIV
Table 30. Serial Programming Characteristics
TA = -40°C to 85°C, VCC = 2.7 - 6.0V (Unless otherwise noted)
Symbol
Parameter
Min
1/tCLCL
Oscillator Frequency (VCC = 2.7 - 4.0V)
tCLCL
Oscillator Period (VCC = 2.7 - 4.0V)
1/tCLCL
Oscillator Frequency (VCC = 4.0 - 6.0V)
tCLCL
Oscillator Period (VCC = 4.0 - 6.0V)
tSHSL
Typ
0
Max
Units
4
MHz
250
ns
0
8
MHz
125
ns
SCK Pulse Width High
2 tCLCL
ns
tSLSH
SCK Pulse Width Low
2 tCLCL
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2 tCLCL
ns
tSLIV
SCK Low to MISO Valid
10
16
32
ns
Absolute Maximum Ratings*
Operating Temperature ................................. -40°C to +105°C
Storage Temperature .................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ......................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
I/O Pin Maximum Current ........................................... 40.0 mA
Maximum Current VCC and GND .............................. 140.0 mA
64
AT90S8515
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT90S8515
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
Parameter
Condition
Min
VIL
Input Low Voltage
VIH
Input High Voltage
(Except XTAL1, RESET)
VIH1
Input High Voltage
(XTAL1, RESET)
VOL
Output Low Voltage(1)
(Ports B,C,D)
IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 2.7V
VOH
Output High Voltage
(Ports B,C,D)
IHI = 10 mA, VCC = 5V
IHI = 5 mA, VCC = 2.7V
IOH
Output Source Current
(Ports B,C,D)
VCC = 5V
VCC = 2.7V
10
5
mA
IOL
Output Sink Current
(Port B,C,D)
VCC = 5V
VCC = 2.7V
20
10
mA
RRST
Reset Pulldown Resistor
10
50
kΩ
RI/O
I/O Pin Pull-Up Resistor
35
120
kΩ
ICC
Power Supply Current
Max
Units
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.5
V
ICC
Power Down Mode(2)
VACIO
Analog Comparator
Input Offset Voltage
IACLK
Analog Comparator
Input Leakage Current
tACPD
Analog Comparator
Propagation Delay
4.5
Active Mode, 3V, 4MHz
Notes:
Typ
V
3.5
mA
1000
µA
WDT enabled, 3V
50
µA
WDT disabled, 3V
<1
µA
Idle Mode 3V, 4MHz
VCC = 5V
1
VCC = 2.7V
VCC = 4.0V
5
750
500
20
mV
10
nA
ns
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum total IOL for all output pins: 80 mA
Port A: 26 mA
Ports A, B, D: 15 mA
Maximum total IOL for all output pins: 70 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink current greater than the listed test conditions.
2. Minimum VCC for Power Down is 2V.
65
External Clock Drive Waveforms
External Clock Drive
VCC = 2.7V to 6.0V
Symbol
Parameter
1/tCLCL
Oscillator Frequency
tCLCL
Clock Period
tCHCX
VCC = 4.0V to 6.0V
Min
Max
Min
Max
Units
0
4
0
8
MHz
250
125
ns
High Time
0
0
ns
tCLCX
Low Time
0
0
ns
tCLCH
Rise Time
1.6
0.5
µs
tCHCL
Fall Time
1.6
0.5
µs
Figure 67. External RAM Timing
T1
T2
T3
T4
0
System Clock O
1
4
7
Address [15..8] Prev. Address
Address
Data / Address [7..0]
Prev. Address
15
13
Data
Address
3a
WR
16
6
Prev. Address
RD
T3 is only present when wait-state is enabled.
66
AT90S8515
Address
Data
5
10
8
Addr.
11
3b
Data / Address [7..0]
Addr.
14
Write
2
Read
ALE
9
12
AT90S8515
External Data Memory Timing
Table 31. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State
8 MHz Oscillator
Min
Variable Oscillator
Symbol
Parameter
Max
Min
Max
Unit
0
1/tCLCL
Oscillator Frequency
0.0
8.0
MHz
1
tLHLL
ALE Pulse Width
32.5
0.5tCLCL-30.0
ns
2
tAVLL
Address Valid A to ALE Low
22.5
0.5tCLCL-40.0
ns
3a
tLLAX_ST
Address Hold After ALE Low,
ST/STD/STS Instructions
67.5
0.5tCLCL+5.0
ns
3b
tLLAX_LD
Address Hold after ALE Low,
LD/LDD/LDS Instructions
15.0
15.0
4
tAVLLC
Address Valid C to ALE Low
22.5
0.5t CLCL-40.0
ns
5
tAVRL
Address Valid to RD Low
95.0
1.0tCLCL-30.0
ns
6
tAVWL
Address Valid to WR Low
157.5
1.5tCLCL-30.0
ns
7
tLLWL
ALE Low to WR Low
105.0
145
1.0tCLCL-20.0
1.0tCLCL+20.0
ns
8
tLLRL
ALE Low to RD Low
42.5
82.5
0.5tCLCL-20.0
0.5tCLCL+20.0
ns
9
tDVRH
Data Setup to RD High
60.0
10
tRLDV
Read Low to Data Valid
11
tRHDX
Data Hold After RD High
12
tRLRH
13
ns
60.0
70.0
ns
1.0tCLCL-55.0
ns
0.0
0.0
ns
RD Pulse Width
105.0
1.0tCLCL-20.0
ns
tDVWL
Data Setup to WR Low
27.5
0.5tCLCL-35.0
ns
14
tWHDX
Data Hold After WR High
0.0
0.0
ns
15
tDVWH
Data Valid to WR High
95.0
1.0tCLCL-30.0
ns
16
tWLWH
WR Pulse Width
42.5
0.5tCLCL-20.0
ns
Table 32. External Data Memory Characterizatics, 4.0 - 6.0 Volts, 1 Cycle Wait State
8 MHz Oscillator
Min
Max
Variable Oscillator
Symbol
Parameter
Min
Max
Unit
0
1/tCLCL
Oscillator Frequency
0.0
8.0
MHz
10
tRLDV
Read Low to Data Valid
12
tRLRH
RD Pulse Width
230.0
2.0tCLCL-20.0
ns
15
tDVWH
Data Valid to WR High
220.0
2.0tCLCL-30.0
ns
16
tWLWH
WR Pulse Width
167.5
1.5tCLCL-20.0
ns
195.0
2.0tCLCL-55.0
ns
67
Table 33. External Data Memory Characteristics, 2.7 - 6.0 Volts, No Wait State
8 MHz Oscillator
Min
Variable Oscillator
Symbol
Parameter
Max
Min
Max
Unit
0
1/tCLCL
Oscillator Frequency
0.0
4.0
MHz
1
tLHLL
ALE Pulse Width
70.0
0.5tCLCL-55.0
ns
2
tAVLL
Address Valid A to ALE Low
60.0
0.5tCLCL-65.0
ns
3a
tLLAX_ST
Address Hold After ALE Low,
ST/STD/STS Instructions
130.0
0.5tCLCL+5.0
ns
3b
tLLAX_LD
Address Hold after ALE Low,
LD/LDD/LDS Instructions
15.0
15.0
4
tAVLLC
Address Valid C to ALE Low
60.0
0.5t CLCL-65.0
ns
5
tAVRL
Address Valid to RD Low
200.0
1.0tCLCL-50.0
ns
6
tAVWL
Address Valid to WR Low
325.0
1.5tCLCL-50.0
ns
7
tLLWL
ALE Low to WR Low
230.0
270.0
1.0tCLCL-20.0
1.0tCLCL+20.0
ns
8
tLLRL
ALE Low to RD Low
105.0
145.0
0.5tCLCL-20.0
0.5tCLCL+20.0
ns
9
tDVRH
Data Setup to RD High
95.0
10
tRLDV
Read Low to Data Valid
11
tRHDX
Data Hold After RD High
12
tRLRH
13
ns
95.0
170.0
ns
1.0tCLCL-80.0
ns
0.0
0.0
ns
RD Pulse Width
230.0
1.0tCLCL-20.0
ns
tDVWL
Data Setup to WR Low
70.0
0.5tCLCL-55.0
ns
14
tWHDX
Data Hold After WR High
0.0
0.0
ns
15
tDVWH
Data Valid to WR High
210.0
1.0tCLCL-40.0
ns
16
tWLWH
WR Pulse Width
105.0
0.5tCLCL-20.0
ns
Table 34. External Data Memory Characteristics, 2.7 - 6.0 Volts, 1 Cycle Wait State
8 MHz Oscillator
Symbol
Parameter
0
1/tCLCL
Oscillator Frequency
10
tRLDV
Read Low to Data Valid
12
tRLRH
RD Pulse Width
480.0
2.0tCLCL-20.0
ns
15
tDVWH
Data Valid to WR High
460.0
2.0tCLCL-40.0
ns
16
tWLWH
WR Pulse Width
355.0
1.5tCLCL-20.0
ns
68
AT90S8515
Min
Max
Variable Oscillator
Min
Max
Unit
0.0
8.0
MHz
420.00
2.0tCLCL-80.0
ns
AT90S8515
POWER DOWN SUPPLY CURRENT vs. VCC
ACTIVE SUPPLY CURRENT vs. FREQUENCY
WATCHDOG TIMER DISABLED
TA = 25˚C
12
25
VCC = 6.0V
VCC = 5.5V
10
20
TA = 85˚C
8
ICC (µA)
ICC (mA)
VCC = 5.0V
VCC = 4.5V
15
VCC = 4.0V
10
VCC = 3.6V
6
TA = 70˚C
4
VCC = 3.3V
VCC = 3.0V
5
2
VCC = 2.7V
TA = 45˚C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
2
15
4
5
VCC (V)
Frequency (MHz)
POWER DOWN SUPPLY CURRENT vs. VCC
IDLE SUPPLY CURRENT vs. FREQUENCY
WATCHDOG TIMER ENABLED
TA = 25˚C
140
12
120
VCC = 6.0V
10
ICC (µA)
8
VCC = 5.0V
6
TA = 85˚C
100
VCC = 5.5V
ICC (mA)
TA = 25˚C
TA = -40˚C
6
0
0
VCC = 4.5V
80
TA = 25˚C
60
VCC = 4.0V
4
40
VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
VCC = 2.7V
2
20
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
2.5
3
15
3.5
4
4.5
5
5.5
6
VCC (V)
Frequency (MHz)
ANALOG COMPARATOR SUPPLY CURRENT vs. VCC
ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.8
FREQUENCY = 4 MHz
14
0.7
TA = -40˚C
12
TA = -40˚C
0.6
0.5
ICC (mA)
ICC (mA)
10
TA = 85˚C
8
TA = 85˚C
0.4
6
0.3
4
0.2
2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
0
2
6
3
4
5
6
VCC (V)
VCC (V)
IDLE SUPPLY CURRENT vs. SUPPLY VOLTAGE
RC OSCILLATOR FREQUENCY vs. VCC
FREQUENCY = 4 MHz
1600
4
1400
3.5
TA = 25˚C
TA = -40˚C
1200
2.5
FRC (kHz)
ICC (mA)
3
TA = 85˚C
2
1.5
1000
TA = 85˚C
800
600
400
1
200
0.5
0
2
2.5
3
3.5
4
VCC (V)
4.5
5
5.5
6
2
3
4
5
6
VCC (V)
69
ANALOG COMPARATOR
INPUT LEAKAGE CURRENT
TYPICAL MAX. OPERATING FREQUENCY
16
TA = 0˚C
TA = 25˚C
12
50
TA = 85˚C
40
10
ACIL (nA)
Freq (MHz)
VCC = 6V, TA = 25˚C
60
14
8
6
30
20
10
4
0
2
-10
0
2
3
4
5
0
6
0.5
1
1.5
2
2.5
VCC = 5V
4.5
5
5.5
6
12
10
8
6
4
8
TA = 85˚C
6
5
4
3
2
0
2
7
TA = 70˚C
7
1
1
6.5
TA = 25˚C
TA = 45˚C
9
Offset Voltage (mV)
Offset Voltage (mV)
14
TA = 45˚C
TA = 70˚C
TA = 80˚C
2
3
4
Common Mode Voltage (V)
70
4
VCC = 2.7V
10
TA = 25˚C
16
0
0
3.5
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
18
3
VIN (V)
VCC (V)
AT90S8515
5
0
0.5
1
1.5
2
Common Mode Voltage (V)
2.5
AT90S8515
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 2.7V
VCC = 5V
120
30
TA = 25˚C
100
TA = 25˚C
25
TA = 85˚C
TA = 85˚C
20
IOP (uA)
IOP (uA)
80
60
15
40
10
20
5
0
0
1
2
3
4
0
5
0
0.5
1
1.5
VIN (V)
VCC = 2.7V
VCC = 5V
6
TA = 25˚C
18
TA = 25˚C
TA = 85˚C
5
16
TA = 85˚C
14
4
IOH (mA)
IOH (mA)
2.5
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
20
2
VIN (V)
12
10
8
3
2
6
1
4
2
0
0
0
1
2
3
4
0
0.5
1
5
1.5
2
2.5
VOH (V)
VOH (V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
VCC = 5V
25
70
TA = 25˚C
TA = 25˚C
60
TA = 85˚C
20
TA = 85˚C
IOL (mA)
IOL (mA)
50
40
30
15
10
20
5
10
0
0
0.5
1
1.5
2
0
2.5
0
VOL (V)
0.5
1
1.5
2
VOL (V)
I/O PIN INPUT THRESHOLD vs. VCC
I/O PIN INPUT HYSTERESIS vs. VCC
2.5
0.18
Input Hysteresis (V)
Threshold Voltage (V)
0.16
2
1.5
1
0.14
0.12
0.1
0.08
0.06
0.04
0.5
0.02
0
2.7V
0
4.0V
2.7V
5.0V
4.0V
5.0V
VCC
VCC
Note:
Charts show typical values.
71
AT90S8515 Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
…
$00 ($20)
SREG
SPH
SPL
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
Reserved
TCCR0
TCNT0
Reserved
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
Reserved
Reserved
ICR1H
ICR1L
Reserved
Reserved
WDTCR
Reserved
Reserved
EEARL
EEDR
EECR
PORTA
DDRA
PINA
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
USR
UCR
UBRR
ACSR
Reserved
Reserved
I
SP15
SP7
T
SP14
SP6
H
SP13
SP5
S
SP12
SP4
V
SP11
SP3
N
SP10
SP2
Z
SP9
SP1
C
SP8
SP0
18
19
19
INT1
INTF1
TOIE1
TOV1
INT0
INTF0
OCIE1A
OCF1A
-
-
-
-
-
-
OCIE1B
OCF1B
-
TICIE1
ICF1
-
TOIE0
TOV0
-
24
24
24
25
SRE
SRW
SE
SM
ISC11
ISC10
ISC01
ISC00
26
-
-
-
CS02
CS01
CS00
29
30
CTC1
CS12
PWM11
CS11
PWM10
CS10
32
33
34
34
35
35
35
35
72
Timer/Counter0 (8 Bit)
COM1A1
COM1A0
COM1B1
COM1B0
ICNC1
ICES1
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
-
-
-
EEPROM Address Register Low Byte
EEPROM Data Register
PORTA7
PORTA6
PORTA5
DDA7
DDA6
DDA5
PINA7
PINA6
PINA5
PORTB7
PORTB6
PORTB5
DDB7
DDB6
DDB5
PINB7
PINB6
PINB5
PORTC7
PORTC6
PORTC5
DDC7
DDC6
DDC5
PINC7
PINC6
PINC5
PORTD7
PORTD6
PORTD5
DDD7
DDD6
DDD5
PIND7
PIND6
PIND5
SPI Data Register
SPIF
WCOL
SPIE
SPE
DORD
UART I/O Data Register
RXC
TXC
UDRE
RXCIE
TXCIE
UDRIE
UART Baud Rate Register
ACD
ACO
AT90S8515
36
36
WDTOE
WDE
WDP2
WDP1
WDP0
38
-
-
-
-
EEAR8
PORTA4
DDA4
PINA4
PORTB4
DDB4
PINB4
PORTC4
DDC4
PINC4
PORTD4
DDD4
PIND4
PORTA3
DDA3
PINA3
PORTB3
DDB3
PINB3
PORTC3
DDC3
PINC3
PORTD3
DDD3
PIND3
EEMWE
PORTA2
DDA2
PINA2
PORTB2
DDB2
PINB2
PORTC2
DDC2
PINC2
PORTD2
DDD2
PIND2
EEWE
PORTA1
DDA1
PINA1
PORTB1
DDB1
PINB1
PORTC1
DDC1
PINC1
PORTD1
DDD1
PIND1
EERE
PORTA0
DDA0
PINA0
PORTB0
DDB0
PINB0
PORTC0
DDC0
PINC0
PORTD0
DDD0
PIND0
MSTR
CPOL
CPHA
SPR1
SPR0
FE
RXEN
OR
TXEN
CHR9
RXB8
TXB8
ACI
ACIE
ACIC
ACIS1
ACIS0
39
39
39
40
54
54
54
56
56
56
61
61
61
63
63
63
45
44
44
48
48
49
51
52
AT90S8515
AT90S8515 Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
Operation
Flags
#Clocks
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
2
3
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
73
AT90S8515 Instruction Set Summary
Mnemonics
Operands
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
LDI
Rd, K
LD
Rd, X
LD
Rd, X+
LD
Rd, - X
LD
Rd, Y
LD
Rd, Y+
LD
Rd, - Y
LDD
Rd,Y+q
LD
Rd, Z
LD
Rd, Z+
LD
Rd, -Z
LDD
Rd, Z+q
LDS
Rd, k
ST
X, Rr
ST
X+, Rr
ST
- X, Rr
ST
Y, Rr
ST
Y+, Rr
ST
- Y, Rr
STD
Y+q,Rr
ST
Z, Rr
ST
Z+, Rr
ST
-Z, Rr
STD
Z+q,Rr
STS
k, Rr
LPM
IN
Rd, P
OUT
P, Rr
PUSH
Rr
POP
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
CBI
P,b
LSL
Rd
LSR
Rd
ROL
Rd
ROR
Rd
ASR
Rd
SWAP
Rd
BSET
s
BCLR
s
BST
Rr, b
BLD
Rd, b
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
74
Description
Operation
Flags
#Clocks
Move Between Registers
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
In Port
Out Port
Push Register on Stack
Pop Register from Stack
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watchdog Reset
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V←1
V←0
T←1
T←0
H←1
H←0
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
AT90S8515
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
AT90S8515
Ordering Information
Speed (MHz)
Power Supply
Ordering Code*
Package
4
2.7 - 6.0V
AT90S8515-4AC
AT90S8515-4JC
AT90S8515-4PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT90S8515-4AI
AT90S8515-4JI
AT90S8515-4PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
AT90S8515-8AC
AT90S8515-8JC
AT90S8515-8PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT90S8515-8AI
AT90S8515-8JI
AT90S8515-8PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
8
4.0 - 6.0V
Operation Range
Package Type
44A
44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
44J
44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6
40-Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)
75
Packaging Information
44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
Dimensions in Millimeters and (Inches)*
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
*Controlling dimension: millimeters
40P6, 40-Lead, 0.600" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
76
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
AT90S8515