ATMEL ATF1504AS

Features
• High-density, High-performance, Electrically-erasable Complex Programmable
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Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3V or 5.0V I/O Pins
Security Fuse Feature
Highperformance
Complex
Programmable
Logic Device
ATF1504AS
ATF1504ASL
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent – Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
VCC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0950N–PLD–07/02
1
44-lead PLCC
Top View
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
GCLK2/OE2/I
I/GCLR
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
I/O
VCCIO
1/O
I/O
I/O
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O/PD1
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O/PD2
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
GND
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
7
8
9
10
11
12
13
14
15
16
17
84-lead PLCC
Top View
I/O
I/O
I/O
GND
I/O
I/O
VCCINT
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
VCCIO
I/O
I/O
68-lead PLCC
Top View
I/O
VCCIO
I/O/TD1
I/O
I/O
I/O
GND
I/O/PD1
I/O
I/O/TMS
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
6
5
4
3
2
1
44
43
42
41
40
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
18
19
20
21
22
23
24
25
26
27
28
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
44-lead TQFP
Top View
2
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
100-lead TQFP
Top View
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
NC
NC
I/O
100-lead PQFP
Top View
NC
NC
VCCIO
I/O/TDI
NC
I/O
NC
I/O
I/O
I/O
GND
I/O/PD1
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
NC
I/O
NC
I/O
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
GND
I/O/TDO
NC
I/O
NC
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
NC
I/O
NC
I/O
VCCIO
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
I/O
I/O
GND
I/O/TDO
NC
I/O
NC
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
NC
I/O
NC
I/O
VCCIO
NC
NC
GND
NC
NC
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O/PD2
GND
I/O
I/O
I/O
I/O
I/O
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O/PD2
GND
I/O
I/O
I/O
I/O
I/O
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
I/O
I/O
VCCIO
I/O/TDI
NC
I/O
NC
I/O
I/O
I/O
GND
I/O/PD1
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
NC
I/O
NC
I/O
GND
NC
NC
3
0950N–PLD–07/02
Description
The ATF1504AS is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices
increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1504AS has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504AS allows fast, efficient generation of complex logic functions. The ATF1504AS contains four such logic chains, each capable of creating sum
term logic with a fan-in of up to 40 product terms.
The ATF1504AS macrocell, shown in Figure 1, is flexible enough to support highly-complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
4
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Block Diagram
I/O (MC64)/GCLK3
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature
is accessible regardless of the state of the security fuse.
The ATF1504AS device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG’s
Boundary-scan Description Language (BSDL). ISP allows the device to be programmed
without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
5
0950N–PLD–07/02
Product Terms and Select
Mux
Each ATF1504AS macrocell has five product terms. Each product term receives as its
possible inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1504AS’s logic structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with a little small additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
Flip-flop
The ATF1504AS’s flip-flop has very flexible data and control functions. The data input
can come from either the XOR gate, from a separate product term or directly from the
I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented
by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be
configured as a flow-through latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
The clock itself can be either one of the Global CLK Signals (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (product term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.
Output Select and Enable
The ATF1504AS macrocell output can be selected as registered or combinatorial. The
buried feedback signal can be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output enable signals. Any buffer can
be permanently enabled for simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configuration all the macrocell
resources are still available, including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be selected as either of the two dedicated OE input pins as an I/O pin configured as an input, or as an individual product
term.
Global Bus/Switch Matrix
6
The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 64 macrocells. The switch matrix in each logic block receives as its possible
inputs all signals from the global bus. Under software control, up to 40 of these signals
can be selected as inputs to the logic block.
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The sixteen foldback terms in each region allow generation
of high fan-in sum terms (up to sixteen product terms) with a nominal additional delay.
Figure 1. ATF1504AS Macrocell
7
0950N–PLD–07/02
Programmable Pinkeeper Option for
Inputs and I/Os
The ATF1504AS offers the option of programming all input and I/O pins so that pinkeeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Input Diagram
Speed/Power
Management
The ATF1504AS has several built-in speed and power management features. The
ATF1504AS contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
I/O Diagram
To further reduce power, each ATF1504AS macrocell has a Reduced Power bit feature.
This feature allows individual macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1504AS also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power-down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
8
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the
AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
The ATF1504AS macrocell also has an option whereby the power can be reduced on a
per macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned-down, thereby reducing the overall power consumption
of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1504AS designs are supported by several industry-standard third-party tools. Automated fitters allow logic synthesis using a variety of high level description languages
and formats.
Power-up Reset
The ATF1504AS is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the
system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3. The clock must remain stable during TD.
The ATF1504AS has two options for the hysteresis about the reset level, VRST, Small
and Large. During the fitting process users may configure the device with the Power-up
Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large
option by including the flag “-power_reset” on the command line after “filename.POF”.
To allow the registers to be properly reinitialized with the Large hysteresis option
selected, the following condition is added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on
again.
When the Large hysteresis option is active, ICC is reduced by several hundred microamps as well.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1504AS fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
9
0950N–PLD–07/02
Programming
ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG
protocol. This capability eliminates package handling normally required for programming
and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1504AS via
the PC. ISP is performed by using either a download cable or a comparable board tester
or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel provided software utilities.
ATF1504AS devices can also be programmed using standard third-party programmers.
With third-party programmer, the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1504AS has a special feature that locks the device and prevents the inputs and
I/O from driving if the programming process is interrupted for any reason. The inputs
and I/O default to high-Z state during such a condition. In addition the pin-keeper option
preserves the former state during device programming, if this circuit were previously
programmed on the device. This prevents disturbing the operation of other circuits in the
system while the ATF1504AS is being programmed via ISP.
All ATF1504AS devices are initially shipped in the erased state thereby making them
ready to use for ISP.
Note:
10
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0°C - 70°C
-40°C - 85°C
VCCINT or VCCIO (5V) Power Supply
5V ± 5%
5V ± 10%
3.0V - 3.6V
3.0V - 3.6V
VCCIO (3.3V) Power Supply
DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
VIN = V CC
IIH
Input or I/O High
Leakage Current
IOZ
Tri-state Output
Off-state Current
Min
VO = VCC or GND
Std Mode
ICC1
Power Supply Current,
Standby
VCC = Max
VIN = 0, VCC
“L” Mode
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode
ICC3(2)
Current in Reduced-power
Mode
VCC = Max
VIN = 0, VCC
Std Power
VCCIO
Supply Voltage
5.0V Device Output
VCCIO
Supply Voltage
3.3V Device Output
VIL
VIH
Notes:
Max
Units
-2
-10
µA
2
10
-40
40
µA
Com.
105
mA
Ind.
130
mA
Com.
10
µA
Ind.
10
µA
1
10
Com
85
Ind
105
mA
ma
Com.
4.75
Ind.
4.5
5.5
V
3.0
3.6
V
Input Low Voltage
-0.3
0.8
V
Input High Voltage
2.0
VCCIO + 0.3
V
5.25
V
0.45
V
Output Low Voltage (TTL)
VIN = V IH or VIL
VCCIO = MIN, IOL = 12 mA
Com.
Output Low Voltage (CMOS)
VIN = V IH or VIL
VCC = MIN, IOL = 0.1 mA
Com.
.2
V
Ind.
.2
V
Output High Voltage (TTL)
VIN = V IH or VIL
VCCIO = MIN, IOH = -4.0 mA
VOL
VOH
Typ
Ind.
2.4
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. When macrocell reduced-power feature is enabled.
Pin Capacitance
Typ
Max
Units
Conditions
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
11
0950N–PLD–07/02
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
1.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
AC Characteristics
-7
Max
Min
-15
-20
Max
Min
Max
7.5
10
3
15
7
9
3
12
Parameter
tPD1
Input or Feedback to
Non-registered Output
tPD2
I/O Input or Feedback to
Non-registered Feedback
tSU
Global Clock Setup Time
6
7
11
16
20
ns
tH
Global Clock Hold Time
0
0
0
0
0
ns
tFSU
Global Clock Setup Time of
Fast Input
3
3
3
3
5
ns
tFH
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
2
ns
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
3
4
5
6
7
ns
tCL
Global Clock Low Time
3
4
5
6
7
ns
tASU
Array Clock Setup Time
3
3
4
4
5
ns
tAH
Array Clock Hold Time
2
3
4
5
6
ns
tACOP
Array Clock Output Delay
tACH
Array Clock High Time
3
4
6
8
10
ns
tACL
Array Clock Low Time
3
4
6
8
10
ns
tCNT
Minimum Clock Global Period
fCNT
Maximum Internal Global
Clock Frequency
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array
Clock Frequency
4.5
5
7.5
125
100
10
100
Max
Units
20
25
ns
16
25
ns
13
25
17
66
13
76.9
Min
20
13
76.9
Max
10
15
10
8
125
8
10
8
Min
-25
Symbol
12
Min
-10
22
50
17
66
ns
ns
MHz
22
50
ns
ns
MHz
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
AC Characteristics (Continued)
-7
Max
Max
Max
Maximum Clock Frequency
tIN
Input Pad and Buffer Delay
0.5
0.5
2
2
2
ns
tIO
I/O Input Pad and Buffer Delay
0.5
0.5
2
2
2
ns
tFIN
Fast Input Delay
1
1
2
2
2
ns
tSEXP
Foldback Term Delay
4
5
8
10
12
ns
tPEXP
Cascade Logic Delay
0.8
0.8
1
1
1.2
ns
tLAD
Logic Array Delay
3
5
6
7
8
ns
tLAC
Logic Control Delay
3
5
6
7
8
ns
tIOE
Internal Output Enable Delay
2
2
3
3
4
ns
tOD1
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 5V; CL = 35 pF)
2
1.5
4
5
6
ns
tOD2
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
2.5
2.0
5
6
7
ns
tOD3
Output Buffer and Pad Delay
(Slow slew rate = ON;
VCCIO = 5V or 3.3V; CL = 35 pF)
5
5.5
8
10
10
ns
100
Min
-25
fMAX
125
Min
-20
Parameter
166.7
Min
-15
Symbol
Note:
Min
-10
Max
83.3
Min
Max
60
Units
MHz
See ordering information for valid part numbers.
Timing Model
13
0950N–PLD–07/02
AC Characteristics (Continued)
-7
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
4.0
5.0
7
tZX2
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
4.5
5.5
tZX3
Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; CL = 35 pF)
9
tXZ
Output Buffer Disable Delay
(C L = 5 pF)
4
tSU
Register Setup Time
3
3
4
5
6
ns
tH
Register Hold Time
2
3
4
5
6
ns
tFSU
Register Setup Time of Fast Input
3
3
2
2
3
ns
tFH
Register Hold Time of Fast Input
0.5
0.5
2
2
2.5
ns
tRD
Register Delay
1
2
1
2
2
ns
tCOMB
Combinatorial Delay
1
2
1
2
2
ns
tIC
Array Clock Delay
3
5
6
7
8
ns
tEN
Register Enable Time
3
5
6
7
8
ns
tGLOB
Global Control Delay
1
1
1
1
1
ns
tPRE
Register Preset Time
2
3
4
5
6
ns
tCLR
Register Clear Time
2
3
4
5
6
ns
tUIM
Switch Matrix Delay
1
1
2
2
2
ns
10
11
13
14
15
ns
Notes:
Max
Min
Max
Min
-25
tZX1
Reduced-power Adder
Min
-20
Parameter
(2)
Max
-15
Symbol
tRPA
Min
-10
Max
Min
Max
Units
9
10
ns
7
9
10
ns
9
10
11
12
ns
5
6
7
8
ns
1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.
Input Test Waveforms and Measurement Levels
tR, tF = 1.5 ns typical
14
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Output AC Test Loads
Note:
*Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
Power-down Mode
The ATF1504AS includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched internally and held. Therefore, all registered and
combinatorial output data remain valid. Any outputs that were in a high-Z state at the
onset will remain at high-Z. During power-down, all input signals except the power-down
pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float
to indeterminate levels, further reducing system power. The power-down mode feature
is enabled in the logic design file or as a fitted or translated s/w option. Designs using
the power-down pin may not use the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
Power Down AC Characteristics(1)(2)
-7
Symbol
Parameter
tIVDH
Valid I, I/O before PD High
tGVDH
Valid OE
(2)
Min
-10
Max
Min
-15
Max
Min
-20
Max
Min
-25
Max
Min
Max
Units
7
10
15
20
25
ns
before PD High
7
10
15
20
25
ns
(2)
7
10
15
20
25
ns
tCVDH
Valid Clock
tDHIX
I, I/O Don’t Care after PD High
12
15
25
30
35
ns
tDHGX
OE (2) Don’t Care after PD High
12
15
25
30
35
ns
12
15
25
30
35
ns
(2)
before PD High
tDHCX
Clock
tDLIV
PD Low to Valid I, I/O
1
1
1
1
1
µs
tDLGV
PD Low to Valid OE (Pin or Term)
1
1
1
1
1
µs
tDLCV
PD Low to Valid Clock (Pin or Term)
1
1
1
1
1
µs
tDLOV
PD Low to Valid Output
1
1
1
1
1
µs
Notes:
Don’t Care after PD High
1. For slow slew outputs, add tSSO.
2. Pin or product term.
3. Includes tRPA due to reduced power bit enabled.
15
0950N–PLD–07/02
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1504AS. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to
support boundary scan testing. The ATF1504AS does not currently include a Test Reset
(TRST) input pin because the TAP controller is automatically reset at power-up. The five
JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE
and HIGHZ. The ATF1504AS’s ISP can be fully described using JTAG’s BSDL as
described in IEEE Standard 1149.1b. This allows ATF1504AS programming to be
described and implemented using any one of the third-party development tools supporting this standard.
The ATF1504AS has the option of using four JTAG-standard I/O pins for boundary-scan
testing (BST) and in-system programming (ISP) purposes. The ATF1504AS is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol
established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the
ISP interface for in-system programming. The JTAG feature is a programmable option.
If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O
pins.
JTAG Boundary-scan
Cell (BSC) Testing
The ATF1504AS contains up to 68 I/O pins and four input pins, depending on the device
type and package type selected. Each input pin and I/O pin has its own boundary-scan
cell (BSC) in order to support boundary-scan testing as described in detail by IEEE
Standard 1149.1. A typical BSC consists of three capture registers or scan registers and
up to two update registers. There are two types of BSCs, one for input or I/O pin, and
one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the
output is directed to the TDO pin. Capture registers are used to capture active device
data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note:
16
The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option.
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
BSC Configuration for Macrocell
Pin BSC
TDO
0
1
Pin
DQ
Capture
DR
Clock
TDI
Shift
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Shift
Clock
Macrocell BSC
17
0950N–PLD–07/02
PCI Compliance
The ATF1504AS also supports the growing need in the industry to support the new
Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and
specifications. The PCI interface calls for high current drivers, which are much larger
than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support
the high current load required by the PCI interface. The ATF1504AS allows this without
contributing to system noise while delivering low output-to-output skew. Having a programmable high drive option is also possible without increasing output delay or pin
capacitance. The PCI electrical characteristics appear on the next page.
PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode
Pull Up
VCC
Voltage
Test Point
2.4
DC
drive point
1.4
AC drive
point
-44 Current (mA) -178
-2
PCI Voltage-to-current Curves for +5V Signaling in Pull-down Mode
Pull Down
VCC
Voltage
AC drive
point
2.2
DC
drive point
0.55
Test Point
3,6
18
95 Current (mA) 380
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
PCI DC Characteristics
Symbol
Parameter
VCC
Conditions
Min
Max
Units
Supply Voltage
4.75
5.25
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.5
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
µA
IIL
Input Low Leakage Current
VIN = 0.5V
-70
µA
VOH
Output High Voltage
IOUT = -2 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
CIN
2.4
V
0.55
V
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
12
pF
CIDSEL
IDSEL Pin Capacitance
8
pF
LPIN
Pin Inductance
20
nH
Note:
Leakage current is with pin-keeper off.
PCI AC Characteristics
Symbol
Parameter
IOH(AC)
Switching
Current High
(Test High)
Conditions
Min
0 < VOUT ≤ 1.4
-44
mA
-44+(VOUT - 1.4)/0.024
mA
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
VOUT = 3.1V
VOUT > 2.2V
IOL(AC)
Switching
Current Low
(Test Point)
2.2 > VOUT > 0
Max
Units
Equation A
mA
-142
µA
95
mA
VOUT/0.023
mA
0.1 > VOUT > 0
VOUT = 0.71
Equation B
mA
206
mA
ICL
Low Clamp Current
-5 < VIN ≤ -1
SLEWR
Output Rise Slew Rate
0.4V to 2.4V load
0.5
3
V/ns
SLEWF
Output Fall Slew Rate
2.4V to 0.4V load
0.5
3
V/ns
Notes:
-25+(V IN + 1)/0.015
mA
1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT ) for 0V < VOUT < 0.71V.
19
0950N–PLD–07/02
ATF1504AS Dedicated Pinouts
44-lead
TQFP
44-lead
J-lead
68-lead
J-lead
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
INPUT/OE2/GCLK2
40
2
2
2
92
90
INPUT/GCLR
39
1
1
1
91
89
INPUT/OE1
38
44
68
84
90
88
INPUT/GCLK1
37
43
67
83
89
87
I/O /GCLK3
35
41
65
81
87
85
I/O/PD (1,2)
5, 19
11, 25
17, 37
20, 46
14, 44
12, 42
I/O/TDI (JTAG)
1
7
12
14
6
4
I/O/TMS (JTAG)
7
13
19
23
17
15
I/O/TCK (JTAG)
26
32
50
62
64
62
I/O/TDO (JTAG)
32
38
57
71
75
73
GND
4, 16, 24, 36
10, 22, 30, 42
6, 16, 26, 34,
38, 48, 58, 66
7, 19, 32, 42,
47, 59, 72, 82
13, 28, 40, 45,
61, 76, 88, 97
11, 26, 38, 43,
59, 74, 86, 95
VCCINT
9, 17, 29, 41
3, 15, 23, 35
3, 35
3, 43
41, 93
39, 91
VCCIO
–
–
11, 21, 31, 43,
53, 63
13, 26, 38, 53,
66, 78
5, 20, 36, 53,
68, 84
3, 18, 34, 51,
66, 82
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
Dedicated Pin
N/C
–
–
–
–
1, 2, 7, 9,
24, 26, 29, 30,
51, 52, 55, 57,
72, 74, 79, 80
# of Signal Pins
36
36
52
68
68
68
# User I/O Pins
32
32
48
64
64
64
OE (1, 2)
Global OE Pins
GCLR
Global Clear Pin
GCLK (1, 2, 3)
Global Clock Pins
PD (1, 2)
Power down pins
TDI, TMS, TCK, TDO
JTAG pins used for boundary-scan testing or in-system programming
GND
Ground Pins
VCCINT
VCC pins for the device (+5V - Internal)
VCCIO
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
20
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
ATF1504AS I/O Pinouts
44-
44-
68-
84-
100-
100-
44-
44-
68-
84-
100-
100-
lead
lead
lead
lead
lead
lead
lead
lead
lead
lead
lead
lead
MC
PLC
PLCC
TQFP
PLCC
PLCC
PQFP
TQFP
MC
PLC
PLCC
TQFP
PLCC
PLCC
PQFP
TQFP
1
A
12
6
18
22
16
14
33
C
24
18
36
44
42
40
2
A
–
–
–
21
15
13
34
C
–
–
–
45
43
41
3
A/
PD1
11
5
17
20
14
12
35
C/
PD2
25
19
37
46
44
42
4
A
9
3
15
18
12
10
36
C
26
20
39
48
46
44
5
A
8
2
14
17
11
9
37
C
27
21
40
49
47
45
6
A
–
–
13
16
10
8
38
C
–
–
41
50
48
46
7
A
–
–
–
15
8
6
39
C
–
–
–
51
49
47
8/
TDI
A
7
1
12
14
6
4
40
C
28
22
42
52
50
48
9
A
–
–
10
12
4
100
41
C
29
23
44
54
54
52
10
A
–
–
–
11
3
99
42
C
–
–
–
55
56
54
11
A
6
44
9
10
100
98
43
C
–
–
45
56
58
56
12
A
–
–
8
9
99
97
44
C
–
–
46
57
59
57
13
A
–
–
7
8
98
96
45
C
–
–
47
58
60
58
14
A
5
43
5
6
96
94
46
C
31
25
49
60
62
60
15
A
–
–
–
5
95
93
47
C
–
–
–
61
63
61
16
A
4
42
4
4
94
92
48/
TCK
C
32
26
50
62
64
62
17
B
21
15
33
41
39
37
49
D
33
27
51
63
65
63
18
B
–
–
–
40
38
36
50
D
–
–
–
64
66
64
19
B
20
14
32
39
37
35
51
D
34
28
52
65
67
65
20
B
19
13
30
37
35
33
52
D
36
30
54
67
69
67
21
B
18
12
29
36
34
32
53
D
37
31
55
68
70
68
22
B
–
–
28
35
33
31
54
D
–
–
56
69
71
69
23
B
–
–
–
34
32
30
55
D
–
–
–
70
73
71
D
38
32
57
71
75
73
D
39
33
59
73
77
75
24
B
17
11
27
33
31
29
56/
TDO
25
B
16
10
25
31
27
25
57
26
B
–
–
–
30
25
23
58
D
–
–
–
74
78
76
27
B
–
–
24
29
23
21
59
D
–
–
60
75
81
79
28
B
–
–
23
28
22
20
60
D
–
–
61
76
82
80
29
B
–
–
22
27
21
19
61
D
–
–
62
77
83
81
30
B
14
8
20
25
19
17
62
D
40
34
64
79
85
83
31
B
–
–
–
24
18
16
63
D
–
–
–
80
86
84
32/
TMS
B
13
7
19
23
17
15
64
D/
GCLK3
41
35
65
81
87
85
21
0950N–PLD–07/02
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(T A = 25°C, F = 0)
125
1100
100
1000
ICC (µA)
ICC (mA)
STANDARD
75
50
800
REDUCED POWER MODE
25
STANDARD POWER
900
REDUCED POWER MODE
700
0
4.50
4.75
5.00
5.25
4.50
5.50
4.75
5.00
5.25
5.50
V CC (V)
V CC (V)
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
LOW POWER (TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW-POWER ("L") VERSION
(TA = 25°C, F = 0)
125.0
30
ICC (mA)
100.0
ICC (µA)
20
STANDARD POWER
75.0
50.0
REDUCED POWER MODE
10
25.0
0.0
0
0.00
4.50
4.75
5.00
5.25
5.00
10.00
5.50
15.00
20.00
25.00
FREQUENCY (MHz)
V CC (V)
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE
(VCC = 5V, TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
0.0
-10.0
200.0
-20.0
-30.0
IOH (mA)
150.0
ICC (mA)
STANDARD POWER
100.0
-40.0
-50.0
-60.0
-70.0
REDUCED POWER MODE
-80.0
50.0
-90.0
0.0
0.00
-100.0
20.00
40.00
60.00
80.00
0.00
100.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
OUTPUT VOLTAGE (V)
FREQUENCY (MHz)
INPUT CLAMP CURRENT VS. INPUT VOLTAGE
(V CC = 5V, T A = 25°C)
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE
(VOH = 2.4V, T A = 25°C)
0
0.0
-10
INPUT CURRENT (mA)
-10.0
IOH (mA)
-20.0
-30.0
-20
-30
-40
-40.0
-50
-50.0
-60
-1.00
-60.0
4.50
4.75
5.00
5.25
5.50
-0.80
-0.60
-0.40
-0.20
0.00
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
22
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE
(VOL = 0.5V, TA = 25°C)
NORMALIZED TPD
VS. TEMPERATURE (VCC = 5.0V)
43
1.2
42
41
NORMALIZED TPD
IOL (mA)
40
39
38
37
36
35
1.1
1.0
0.9
34
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
NORMALIZED TPD
VS. SUPPLY VOLTAGE (TA = 25°C)
NORMALIZED TCO
VS. SUPPLY VOLTAGE (TA = 25°C)
1.10
1.2
1.00
NORMALIZED TPD
NORMALIZED TPD
1.20
0.90
0.80
4.5
4.8
5.0
5.3
5.5
1.1
1.0
0.9
SUPPLY VOLTAGE (V)
0.8
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V, TA = 25°C)
40
NORMALIZED TSU
VS. SUPPLY VOLTAGE (TA = 25°C)
20
1.2
10
0
1.1
-10
-20
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
NORMALIZED TSU
INPUT CURRENT ( µ A)
30
1.0
0.9
INPUT VOLTAGE (V)
0.8
4.5
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE
(VCC = 5V, TA = 25°C)
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
140.0
120.0
IOL (mA)
100.0
80.0
60.0
40.0
20.0
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
OUTPUT VOLTAGE (V)
23
0950N–PLD–07/02
NORMALIZED TCO
VS.TEMPERATURE (V CC = 5.0V)
NORMALIZED TCO
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
NORMALIZED TSU
VS. TEMPERATURE (VCC = 5.0V)
NORMALIZED TSU
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
24
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
ATF1504AS Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
7.5
4.5
166.7
10
5
125
10
5
15
15
Ordering Code
Package
ATF1504AS-7
ATF1504AS-7
ATF1504AS-7
ATF1504AS-7
ATF1504AS-7
ATF1504AS-7
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
ATF1504AS-10 AC44
ATF1504AS-10 JC44
ATF1504AS-10 JC68
ATF1504AS-10 JC84
ATF1504AS-10 QC100
ATF1504AS-10 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
125
ATF1504AS-10 AI44
ATF1504AS-10 JI44
ATF1504AS-10 JI68
ATF1504AS-10 JI84
ATF1504AS-10 QI100
ATF1504AS-10 AI100
44A
44J
68J
84J
100Q1
100A
Industrial
(-40°C to +85°C)
8
100
ATF1504AS-15 AC44
ATF1504AS-15 JC44
ATF1504AS-15 JC68
ATF1504AS-15 JC84
ATF1504AS-15 QC100
ATF1500AS-15 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
8
100
ATF1504AS-15 AI44
ATF1504AS-15 JI44
ATF1504AS-15 JI68
ATF1504AS-15 JI84
ATF1504AS-15 QI100
ATF1504AS-15 AI100
44A
44J
68J
84J
100Q1
100A
Industrial
(-40°C to +85°C)
AC44
JC44
JC68
JC84
QC100
AC100
Operation Range
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
25
0950N–PLD–07/02
ATF1504ASL Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
20
12
25
15
Ordering Code
Package
Operation Range
83.3
ATF1504ASL-20 AC44
ATF1504ASL-20 JC44
ATF1504ASL-20 JC68
ATF1504ASL-20 JC84
ATF1504ASL-20 QC100
ATF1504ASL-20 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
70
ATF1504ASL-25 AI44
ATF1504ASL-25 JI84
ATF1504ASL-25 JI68
ATF1504ASL-25 JI84
ATF1504ASL-25 QI100
ATF1504ASL-25 AI100
44A
44J
68J
84J
100Q1
100A
Industrial
(-40°C to +85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
26
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Packaging Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
27
0950N–PLD–07/02
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
28
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
68J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
25.019
–
25.273
D1
24.130
–
24.333
E
25.019
–
25.273
E1
24.130
–
24.333
D2/E2
22.606
–
23.622
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
68J, 68-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
68J
B
29
0950N–PLD–07/02
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
30.099
–
30.353
D1
29.210
–
29.413
E
30.099
–
30.353
E1
29.210
–
29.413
D2/E2
27.686
–
28.702
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
30
2325 Orchard Parkway
San Jose, CA 95131
TITLE
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
84J
B
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
100Q1 – PQFP
Dimensions in Millimeters and (Inches)*
*Controlling dimensions: millimeters
JEDEC STANDARD MS-022, GC-1
17.45 (0.687)
16.95 (0.667)
PIN 1 ID
PIN 1
20.10 (0.791)
19.90 (0.783)
0.65 (0.0256) BSC
0.40 (0.016)
23.45 (0.923)
0.22 (0.009)
22.95 (0.904)
14.12 (0.556)
13.90 (0.547)
0.23 (0.009)
0.11 (0.004)
3.40 (0.134) MAX
0º~7º
1.03 (0.041)
0.73 (0.029)
0.50 (0.020)
0.25 (0.010)
04/11/2001
R
DRAWING NO.
TITLE
2325 Orchard Parkway
100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch,
100Q1
San Jose, CA 95131
Plastic Quad Flat Package (PQFP)
REV.
A
31
0950N–PLD–07/02
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.17
–
0.27
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.50 TYP
10/5/2001
R
32
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
100A
REV.
C
ATF1504AS(L)
0950N–PLD–07/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
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FAX (852) 2722-1369
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Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
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TEL 1(408) 441-0311
FAX 1(408) 436-4314
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TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
[email protected]
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL ® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0950N–PLD–07/02
xM