CL3256A Link Processed Logic Device Family Key Features u Patented High Fidelity Conversion Technology u Link Processed Logic Device (LPLD®) technology offers the ultimate combination of performance, flexibility, and low cost u Functionally, architecturally, and electrically compatible with industry-standard Altera® MAX® 3000 u High Density - 5,000 Usable gates - 256 Macrocells - 158 Maximum user I/O pins u Metal link technology provides very fast, dense interconnect routing u Low current consumption u Supports 3.3 volt operation u Alpha particle immune CL3000 Product Family Overview Feature CL3128A CL3256A 2,500 5,000 128 256 Logic array Blocks 8 16 Max user I/O pins 96 158 -4, -5, -7, -10 -5, -6, -7, -10 100-Pin TQFP 144-Pin TQFP 144-Pin TQFP 208-Pin PQFP Useable Gates Macrocells Speed Grades Packages 3KA tbl 01A December 2000 Page 121 CL3256A Laser Processed Logic Devices Description The Clear Logic CL3000 Laser Processed Logic Device (LPLD®) family offers the ultimate combination of performance, flexibility, and cost. This family is a system level second source to Altera MAX® 3000A products. For designs not requiring insystem reprogrammability, design verification can be performed using the programmable Altera devices, and Clear Logic LPLDs can be used for low cost, high volume production. Clear Logic’s innovative laser-based technology eliminates NRE costs, test vector development, ordering minimums and long lead times. No re-simulation or re-layout is required, as the device uses a cell-based, PLD-like architecture. Clear Logic’s NoFault® technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. The Clear Logic CL3000 Laser Processed Logic Device family is based upon a large array of macrocells. Each macrocell contains a logic array with five product terms, a product-term select matrix, and a configurable register. A group of sixteen macrocells forms a block. Laser-configured metal fuses implement logical functions and control signal routing. Laser configuration provides reduced cost and enhanced performance. These inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Additional Information For further information on designing with the CL3000 LPLD family (See CL7000), please consult the following documents: u AN-01: Requesting a First Article. This document provides instructions on how to submit a bitstream file for generation of first articles. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL7000 family. u AN-09: CL7000 Technology White Paper. This document outlines the technologies employed by the CL7000 LPLD family. u AN-10: Calculating CL7000 Power Consumption. This document provides guidelines for calculating power consumption based on design characteristics. u AN-11: CL7000 Test Methodology. This document describes how Clear Logic provides 100% stuck-at fault coverage. Page 122 CL3256A Laser Processed Logic Devices u AN-12: CL7000 LPLD Timing and Function Compatibility. This document shows how a seamless conversion from CPLD to ASIC can be achieve with no additional engineering with Clear Logic. Page 123 CL3256A Laser Processed Logic Devices Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables 6 Output Enables Block A 4 to 16 I/O Pins I/O Control Block 4 to 16 Block B 36 36 Macrocells 1 - 16 Macrocells 17 - 32 4 to 16 6 to 16 6 to 16 6 6 Block C I/O Control Block 4 to 16 Block D 36 36 Macrocells 33 - 48 Macrocells 49 - 64 4 to 16 6 Block E 4 to 16 Block F 36 36 Macrocells 65 - 80 Block G I/O Control Block 4 to 16 36 Macrocells 97 - 112 16 6 to 16 6 Block I 4 to 16 I/O Pins I/O Control Block 4 to 16 Macrocells 129 - 144 36 16 6 to 16 Laser-Configured Interconnect Array (LIA) 6 to 16 6 Macrocells 81 - 96 4 to 16 6 Block H 36 Macrocells 113 - 128 4 to 16 6 to 16 6 Block J 36 Macrocells 145 - 160 4 to 16 4 to 16 I/O 6 to 16 4 to 16 Macrocells 161 - 176 36 36 Macrocells 177 - 192 4 to 16 I/O Control Block 4 to 16 I/O Pins 16 6 to 16 6 Block M 4 to 16 Macrocells 193 - 208 Block N 36 16 6 to 16 36 Macrocells 209 - 224 4 to 16 4 to 16 I/O Pins 6 to 16 6 Block P Block O I/O 4 to 16 Control Block I/O Control Block 16 6 Macrocells 225 - 240 36 16 6 to 16 36 Macrocells 241 - 256 4 to 16 I/O Control Block 4 to 16 I/O PIns 16 6 to 16 3256A drw 01 Page 124 Pins 6 6 to 16 4 to 16 I/O Pins I/O Control Block 16 6 I/O Control Block 4 to 16 I/O Pins Block L 16 4 to 16 I/O Pins I/O Control Block 16 Block K I/O Control Block 4 to 16 I/O Pins 6 to 16 6 4 to 16 I/O Pins I/O Control Block 16 16 4 to 16 I/O Pins 4 to 16 I/O Pins 6 to 16 6 to 16 6 I/O Control Block I/O Control Block 16 16 4 to 16 I/O Pins 4 to 16 I/O Pins 16 16 4 to 16 I/O Pins I/O Control Block CL3256A Laser Processed Logic Devices Macrocell Diagram Global Global Clear Clocks Local Array Fast Input Select 2 Configurable Register Parallel Logic Expanders Register Bypass D Clock/ Enable Select Product Term Select Matrix Clear Select Shared Logic Expanders 36 Signals from LIA from I/O pin PRN to I/O Control Block Q ENA CLRN VCC to LIA 3K drw 01 16 Expander Product Terms Page 125 CL3256A Laser Processed Logic Devices Pin Configuration Pin Name 144 pin TQFP 208 pin PQFP INPUT/GCLK1 125 184 INPUT/GCLRn 127 182 INPUT/OE1 126 183 INPUT/OE2/GCLK2 128 181 TDI 4 176 TMS 20 127 TCK 89 30 TDO 104 189 52, 57, 124, 129 75, 82, 180, 185 3, 13, 17, 26, 33, 59, 64, 77, 85, 94, 105, 114, 135 6, 14, 32, 40, 50, 72, 84, 94, 108, 116, 134, 142, 152, 174, 190, 200 VCCINT 51, 58, 123, 130 74, 83, 179, 186 VCCIO 24, 50, 73, 76, 95, 115, 144 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 - 1, 2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 116 158 GNDINT GND NC (No Connect) Total user I/O pins 3256A tbl 01 Page 126 CL3256A Laser Processed Logic Devices DC Electrical Specifications Recommended Operating Conditions Symbol Parameter VCCINT VCCIO VI VO TA TJ tR tF Conditions Min Max Unit Supply voltage, internal logic and input buffers 3.0 3.6 V Supply voltage for output drivers 3.3 volt operation 2.5 volt operation Input voltage 3.0 2.3 -0.5 3.6 2.7 5.75 V V V 0 VCCIO V 0 -40 70 85 °C °C 0 -40 90 105 40 40 °C °C ns ns Output voltage Ambient Operating temperature Commercial temperature range Industrial temperature range Ambient Operating temperature Commercial temperature range Industrial temperature range Input signal rise time Input signal fall time 3KA tbl 02 Absolute Maximum Ratings Symbol VCC VI Parameter Supply voltage DC input voltage [1] Conditions Min Max Unit With respect to ground -0.5 4.6 V With respect to ground -2.0 5.75 V -25 25 mA IOUT DC output current, per pin TSTG Storage temperature No bias -65 150 °C TA Ambient temperature Under bias -65 135 °C TJ Junction temperature PQFP, and TPFP packages, Under bias 135 °C 3KA tbl 03 Page 127 CL3256A Laser Processed Logic Devices DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter VIH High-level input Voltage VIL Input LOW Voltage Conditions [1] 3.3-V high-level TTL output Voltage IOH = -8 mA DC, VCCIO = 3.00 V 2.5-V high-level output Voltage 3.3-V high-level TTL output Voltage Max Unit 1.7 5.75 V -0.5 0.8 V 2.4 V VCCIO-0.2 V IOH = -100 µA DC, VCCIO = 2.30 V 2.1 V IOH = -1 mA DC, VCCIO = 2.30 V 2.0 IOH = -2 mA DC, VCCIO = 2.30 V 1.7 3.3-V high-level CMOS output Voltage IOH = -0.1 mA DC, VCCIO = 3.00 V VOH Min 0.45 V 3.3-V high-level CMOS output Voltage IOH = 0.1 mA DC, VCCIO = 3.00 V 0.2 V IOH = 100 µA DC, VCCIO = 2.30 V 0.2 V IOH = 1 mA DC, VCCIO = 2.30 V 0.4 V IOH = 2 mA DC, VCCIO = 2.30 V 0.7 V VOL 2.5-V high-level output Voltage IOH = 8 mA DC, VCCIO = 3.00 V IIN Input Leakage Current VI = VCC or GND -10 10 µA IOZ Output Leakage Current VO = VCC or GND -10 10 µA 3KA tbl 04 Capacitance Symbol Parameter Conditions CIN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 8 pF VOUT = 0 V, f = 1.0 MHz 8 pF 3KA tbl 05 Page 128 CL3256A Laser Processed Logic Devices AC Electrical Specifications I/O Element Timing Parameters Symbol Parameter Conditions Speed: -4 Min Max Speed: -5 Min Max Speed: -6 Min Max Unit tPD1 Input to non-registered output CL = 35 pF 4.5 5.0 6.0 ns tPD2 I/O input to non-registered output CL = 35 pF 4.5 5.0 6.0 ns tSU Global clock setup time 3.0 3.2 3.7 ns tH Global clock hold time 0.0 0.0 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 2.0 2.0 3.0 ns tCL Global clock low time 2.0 2.0 3.0 ns tASU Array clock setup time 1.4 1.0 0.8 ns tAH Array clock hold time 0.8 0.8 1.9 ns tACO1 Array clock to output delay tACH Array clock high time 2.0 2.0 3.0 ns tACL Array clock low time 2.0 2.0 3.0 ns tCNT Minimum global clock period fCNT Max. internal global clock frequency tACNT Minimum array clock period fACNT Max. internal array clock frequency CL = 35 pF 1.0 CL = 35 pF 2.8 1.0 4.4 5.2 5.2 192.3 1.0 1.0 5.5 181.8 5.2 192.3 3.0 6.2 6.4 156.3 5.5 181.8 3.3 ns ns MHz 6.4 156.3 ns ns MHz 3KA tbl 06A1 Page 129 CL3256A Laser Processed Logic Devices AC Electrical Specifications cont. External Timing Parameters Symbol Parameter Speed: -7 Conditions Min Max Speed: -10 Min Max Unit tPD1 Input to non-registered output CL = 35 pF 7.5 10.0 ns tPD2 I/O input to non-registered output CL = 35 pF 7.5 10.0 ns tSU Global clock setup time 4.9 6.6 ns tH Global clock hold time 0.0 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 3.0 4.0 ns tCL Global clock low time 3.0 4.0 ns tASU Array clock setup time 1.6 2.1 ns tAH Array clock hold time 2.1 3.4 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 4.0 ns tACL Array clock low time 3.0 4.0 ns tCNT Minimum global clock period fCNT Max. internal global clock frequency tACNT Minimum array clock period fACNT Max. internal array clock frequency CL = 35 pF 1.0 CL = 35 pF 4.5 1.0 7.8 10.4 8.4 119.0 11.2 89.3 8.4 119.0 5.9 ns ns MHz 11.2 89.3 ns ns MHz 3KA tbl 06A2 Page 130 CL3256A Laser Processed Logic Devices AC Electrical Specifications cont. Internal Timing Parameters[4] Symbol Parameter Conditions Speed: -4 Min Max Speed: -5 Min Max Speed: -6 Min Max Unit tiN Input pad and buffer delay 0.3 0.3 0.3 ns tIO I/O input pad and buffer delay 0.3 0.3 0.3 ns tSEXP Shared expander delay 1.9 2.4 2.8 ns tPEXP Parallel expander delay 0.5 0.6 0.5 ns tLAD Logic array delay 1.9 2.5 2.5 ns tLAC Logic control array delay 1.8 2.3 2.5 ns tIOE Internal output enable delay 0.0 0.0 0.2 ns CL = 35 pF 0.3 0.4 0.3 ns CL = 35 pF 0.8 0.9 0.8 ns CL = 35 pF 5.3 5.4 5.3 ns CL = 35 pF 4.0 4.0 4.0 ns CL = 35 pF 4.5 4.5 4.5 ns CL = 35 pF 9.0 9.0 9.0 ns CL = 5 pF[3] 4.0 4.0 4.0 ns tOD1 tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tXZ Output buffer disable delay tSU Register setup time 1.4 0.8 1.0 ns tH Register hold time 0.8 1.0 1.7 ns tRD Register delay 1.2 1.4 1.6 ns tCOMB Combinatorial delay 1.3 1.0 1.6 ns tIC Array clock delay 1.9 2.3 2.7 ns tEN Register enable time 1.8 2.3 2.5 ns tGLOB Global control delay 1.0 0.9 1.1 ns tPRE Register preset time 2.3 2.6 2.3 ns tCLR Register clear time 2.3 2.6 2.3 ns tLIA LIA delay 0.7 0.8 1.3 ns 3KA tbl 07A1 Page 131 CL3256A Laser Processed Logic Devices AC Electrical Specifications cont. Speed: -7 Symbol Max Unit tiN Input pad and buffer delay 0.4 0.6 ns tIO I/O input pad and buffer delay 0.4 0.6 ns tSEXP Shared expander delay 3.6 4.9 ns tPEXP Parallel expander delay 0.8 1.1 ns tLAD Logic array delay 3.7 5.0 ns tLAC Logic control array delay 3.4 4.6 ns tIOE Internal output enable delay 0.0 0.0 ns CL = 35 pF 0.6 0.7 ns CL = 35 pF 1.1 1.2 ns CL = 35 pF 5.6 5.7 ns CL = 35 pF 4.0 5.0 ns CL = 35 pF 4.5 5.5 ns CL = 35 pF 9.0 10.0 ns CL = 5 pF[3] 4.0 5.0 ns tOD1 tOD2 Parameter Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Conditions Min Max Speed: -10 Min Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tXZ Output buffer disable delay tSU Register setup time 1.3 1.7 ns tH Register hold time 2.4 3.8 ns tRD Register delay 2.1 2.8 ns tCOMB Combinatorial delay 1.5 2.0 ns tIC Array clock delay 3.4 4.6 ns tEN Register enable time 3.4 4.6 ns tGLOB Global control delay 1.4 1.8 ns tPRE Register preset time 3.9 5.2 ns tCLR Register clear time 3.9 5.2 ns tLIA LIA delay 1.3 1.7 ns 3KA tbl 07A2 Page 132 CL3256A Laser Processed Logic Devices AC Test Conditions (A) (B) 464 Ω VCCIO VCCIO OUTPUT Includes jig capacitance All Input Pulses 464 Ω 3.0V 90% 90% OUTPUT 35 pF 250 Ω Includes jig capacitance 5 pF 250 Ω GND 10% 10% ≤ 3ns ≤ 3ns 3K drw 02 Notes to Tables 1. During transitions, inputs may undershoot to -2.0V for periods shorter than 20ns. Otherwise, minimum DC input voltage is 0.3V. 2. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC. 3. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 4. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. Revision History 20 Oct. 2000: Created preliminary document. 1 Dec. 2000: Updated application note reference. Page 133 CL3256A Laser Processed Logic Devices Ordering Information Part Number CL3256ATC144-10 Temperature Range Altera Equivalent EPM3256ATC144-10 CL3256ATC144-7 -7 EPM3256ATC144-7 CL3256ATC144-6 -6 EPM3256ATC144-6 CL3256ATC144-5 -5 Commercial 144-pin Thin QFP Speed -10 CL3256AQC208-10 Commercial Package Type 208-pin Plastic QFP N/A -10 EPM3256AQC208-10 CL3256AQC208-7 -7 EPM3256AQC208-7 CL3256AQC208-6 -6 EPM3256AQC208-6 CL3256AQC208-5 -5 N/A 3256A tbl 02 Page 134