CY7C372i UltraLogic™ 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks The CY7C372i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C372i is designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • 32 I/O pins • Five dedicated inputs including two clock pins • In-System Reprogrammable (ISR™) Flash technology — JTAG interface • Bus Hold capabilities on all I/Os and dedicated inputs Like all of the UltraLogic™ FLASH370i devices, the CY7C372i is electrically erasable and ISR, which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. • No hidden delays • High speed — fMAX = 125 MHz — tPD = 10 ns — tS = 5.5 ns — tCO = 6.5 ns • Fully PCI compliant The 64 macrocells in the CY7C372i are divided between four logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. • 3.3V or 5.0V I/O operation • Available in 44-pin PLCC, TQFP, and CLCC packages • Pin-compatible with the CY7C371i The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Logic Block Diagram INPUTS 3 INPUT MACROCELLS CLOCK INPUTS 2 INPUT/CLOCK MACROCELLS 2 2 8 I/Os I/O0-I/O7 8 I/Os I/O8-I/O15 LOGIC BLOCK A 36 16 16 LOGIC BLOCK B 36 36 16 16 PIM 36 • 8 I/Os LOGIC BLOCK C 8 I/Os I/O24-I/O31 I/O16-I/O23 16 16 Cypress Semiconductor Corporation Document #: 38-03033 Rev. *A LOGIC BLOCK D 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 16, 2004 CY7C372i Selection Guide 7C372i-125 Maximum Propagation Delay[1] , tPD (ns) 7C372i-100 7C372i-83 7C372iL-83 7C372i-66 7C372iL-66 10 12 15 15 20 20 Minimum Set-up, tS (ns) 5.5 6.0 8 8 10 10 Maximum Clock to Output[1], tCO (ns) 6.5 6.5 8 8 10 10 Typical Supply Current, ICC (mA) 75 75 75 45 75 45 Pin Configurations 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O27/SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21 I/O20 7 8 9 10 11 12 13 14 15 16 17 I/O18 I/O19 /SDO CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21 I/O5/SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 I/O12 I/O 13 /SMODE I/O14 I/O15 V CC GND I/O16 I/O17 I/O27/SDI I/O26 I/O25 I/O24 I/O19 /SDO I/O20 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 /SMODE I/O14 I/O15 V CCINT GND I/O16 I/O17 I/O18 7 8 9 10 11 12 13 14 15 16 17 I/O29 I/O28 6 5 4 3 2 1 44 43 42 41 40 6 5 4 3 2 1 44 43 42 41 40 I/O5/SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 I/O31 I/O30 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 GND VCC I/O28 I/O29 CLCC TopView I/O31 I/O30 I/O 1 I/O 0 GND VCCIO I/O 2 I/O 4 I/O 3 PLCC TopView Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V. Document #: 38-03033 Rev. *A Page 2 of 13 CY7C372i Functional Description Like all members of the FLASH370i family, the CY7C372i is rich in I/O resources. Every two macrocells in the device feature an associated I/O pin, resulting in 32 I/O pins on the CY7C372i. In addition, there are three dedicated inputs and two input/clock pins. Finally, the CY7C372i features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used. or the type of application, the timing parameters on the CY7C372i remain the same. Logic Block The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C372i includes four logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in a single pass through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370 PLDs. Note that product term allocation is handled by software and is invisible to the user. I/O Macrocell Half of the macrocells on the CY7C372i have separate I/O pins associated with them. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The I/O macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Buried Macrocell The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, as a D flip-flop, a T flip-flop, or a latch. The clock for this register has the same options as described for the I/O macrocell. One difference on the buried macrocell is the addition of input register capability. The user can program the buried macrocell to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neigh- Document #: 38-03033 Rev. *A boring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C372i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, “An Introduction to In System Reprogramming with FLASH370i.” PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one set, VCCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When VCCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Design Tools Development software for the CY7C372i is available from Cypress’s Warp™, Warp Professional™, and Warp Enterprise™ software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools. Please refer to third-party tool support for further information. Page 3 of 13 CY7C372i Maximum Ratings Output Current into Outputs ........................................ 16 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage........................................... > 2001V (per MIL–STD–883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range Ambient Temperature DC Voltage Applied to Outputs in High-Z State ............................................... –0.5V to +7.0V Commercial 0°C to +70°C DC Input Voltage............................................ –0.5V to +7.0V Industrial −40°C to +85°C 5V ± 0.5V Military[2] –55°C to +125°C 5V ± 0.5V Test Conditions Min. DC Program Voltage .....................................................12.5V VCC VCCINT VCCIO 5V ± 0.25V 5V ± 0.25V or 3.3V ± 0.3V 5V ± 0.5V 3.3V ± 0.3V Electrical Characteristics Over the Operating Range[3, 4] Parameter Description Typ. Max. Unit VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)[5] VOHZ Output HIGH Voltage with Output Disabled[8] VCC = Max. IOH = 0 µA (Com’l/Ind)[5, 6] 4.0 V IOH = –50 µA 3.6 V VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[5] 0.5 V 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[7] 2.0 7.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs[7] –0.5 0.8 V IIX Input Load Current VI = Internal GND, VI = VCC –10 +10 µA IOZ Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled –50 +50 µA IOH = –2.0 mA (Mil) 2.4 V 2.4 V (Com’l/Ind)[5, 6] IOL = 12 mA (Mil) VCC = Max., VO = 3.3V, Output Disabled[6] IOS Output Short Circuit Current[8, 9] VCC = Max., VOUT = 0.5V ICC Power Supply Current [10] VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, VCC 0 –70 –30 Com’l/Ind. 75 –125 µA –160 mA 125 mA Com’l “L” –66 45 75 mA Military 75 200 mA IBHL Input Bus Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 µA IBHH Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V –75 µA IBHLO Input Bus Hold LOW Overdrive Current VCC = Max. +500 µA IBHHO Input Bus Hold HIGH Overdrive Current VCC = Max. −500 µA Notes: 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC = VCCINT. 5. For SDO: IOH =–2 mA, IOL = 2 mA. 6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 9. Tested initially and after any design or process changes that may affect these parameters. 10. Measured with 16-bit counter programmed into each logic block. Document #: 38-03033 Rev. *A Page 4 of 13 CY7C372i Capacitance[9] Parameter CI/O Description [11, 12] CCLK Test Conditions Input Capacitance VIN = 5.0V at f = 1 MHz Clock Signal Capacitance VIN = 5.0V at f = 1 MHz Min. Max. Unit 8 pF 5 12 pF Inductance[9] Parameter Description L Maximum Pin Inductance Test Conditions 44-Lead CLCC 44-Lead PLCC Unit 2 5 nH VIN = 5.0V at f = 1 MHz Endurance Characteristics[9] Parameter N Description Maximum Reprogramming Cycles Test Conditions Max. Unit Normal Programming Conditions 100 Cycles AC Test Loads and Waveforms 238Ω (com'l) 319Ω (mil) 238Ω (com'l) 319Ω (mil) 5V 5V OUTPUT OUTPUT 170Ω (com'l) 236Ω (mil) 35 pF INCLUDING JIG AND SCOPE 170Ω (com'l) 236Ω (mil) 5 pF INCLUDING JIG AND SCOPE (a) (b) ALL INPUT PULSES THÉVENIN EQUIVALENT 99Ω (com'l) 136Ω (mil) 2.08V(com'l) OUTPUT 2.13V(mil) 3.0V Equivalent to: Parameter[13] Vx tER(–) 1.5V 90% 10% GND < 2 ns (c) 2.6V 0.5V V X 1.5V 0.5V V X tEA(–) < 2 ns V X 0.5V V OL tEA(+) 10% Output Waveform Measurement Level V OH tER(+) 90% V OH Vthe V X 0.5V V OL (d) Test Waveforms Note: 11. CI/O for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max. 12. CI/O for CLCC package is 15 pF Max. 13. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load. Document #: 38-03033 Rev. *A Page 5 of 13 CY7C372i Switching Characteristics Over the Operating Range [14] Parameter Description 7C372i-125 7C372i-100 7C372i-83 7C372iL-83 7C372i-66 7C372iL-66 Min. Min. Min. Min. Max. Max. Max. Max. Unit Combinatorial Mode Parameters tPD Input to Combinatorial Output[1] 10 12 15 20 ns tPDL Input to Output Through Transparent Input or Output Latch[1] 13 15 18 22 ns tPDLL Input to Output Through Transparent Input and Output Latches[1] 15 16 19 24 ns tEA Input to Output Enable[1] 14 16 19 24 ns tER Input to Output Disable 14 16 19 24 ns Input Registered/Latched Mode Parameters tWL Clock or Latch Enable Input LOW Time[9] tWH Clock or Latch Enable Input HIGH Time[9] 3 3 4 5 ns tIS Input Register or Latch Set-Up Time 2 2 3 4 ns tIH Input Register or Latch Hold Time 2 tICO Input Register Clock or Latch Enable to Combinatorial Output[1] 14 16 19 24 ns tICOL Input Register Clock or Latch Enable to Output Through Transparent Output Latch[1] 16 18 21 26 ns 3 3 4 2 5 3 ns 4 ns Output Registered/Latched Mode Parameters tCO Clock or Latch Enable to Output[1] tS Set-Up Time from Input to Clock or Latch Enable tH Register or Latch Data Hold Time tCO2 Output Clock or Latch Enable to Output Delay (Through Memory Array)[1] tSCS Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) 8 10 12 15 ns tSL Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable 10 12 15 20 ns tHL Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable 0 0 0 0 ns fMAX1 Maximum Frequency with Internal Feedback in Output Registered Mode (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] 125 100 83 66 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[9] 153.8 153.8 125 100 MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[9] 83.3 80 62.5 50 MHz tOH-tIH 37x Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[9, 15] 0 0 0 0 ns 6.5 5.5 6.5 6 0 0 14 8 8 0 16 10 10 0 19 ns ns ns 24 ns Pipelined Mode Parameters tICS Input Register Clock to Output Register Clock 8 10 12 15 ns fMAX4 Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)[9] 125 100 83.3 66.6 MHz Notes: 14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. Document #: 38-03033 Rev. *A Page 6 of 13 CY7C372i Switching Characteristics Over the Operating Range (continued)[14] Parameter Description 7C372i-125 7C372i-100 7C372i-83 7C372iL-83 7C372i-66 7C372iL-66 Min. Min. Min. Min. Max. Max. Max. Max. Unit Reset/Preset Parameters tRW Asynchronous Reset Width[9] 10 12 15 20 ns tRR Asynchronous Reset Recovery Time[9] 12 14 17 22 ns [1] tRO Asynchronous Reset to Output tPW Asynchronous Preset Width[9] 10 16 tPR Asynchronous Preset Recovery Time[9] 12 tPO Asynchronous Preset to Output[1] 18 12 14 16 21 15 17 18 26 20 22 21 ns ns ns 26 ns Tap Controller Parameter fTAP Tap Controller Frequency 500 500 500 500 kHz 3.3V I/O Mode Parameters t3.3IO 3.3V I/O Mode Timing Adder 1 1 1 1 ns Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT Registered Output INPUT tS tH CLOCK tCO REGISTERED OUTPUT tWH tWL CLOCK Document #: 38-03033 Rev. *A Page 7 of 13 CY7C372i Switching Waveforms (continued) Latched Output INPUT tH tS LATCH ENABLE tPDL tCO LATCHED OUTPUT Registered Input REGISTERED INPUT tIH tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWH tWL CLOCK Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK tICS tSCS OUTPUT REGISTER CLOCK Document #: 38-03033 Rev. *A Page 8 of 13 CY7C372i Switching Waveforms (continued) Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL tHL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tWH tWL LATCH ENABLE Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK Document #: 38-03033 Rev. *A Page 9 of 13 CY7C372i Switching Waveforms (continued) Output Enable/Disable INPUT tEA tER OUTPUTS Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 125 CY7C372i-125JC J67 44-Lead Plastic Leaded Chip Carrier Commercial 100 CY7C372i-100JC J67 44-Lead Plastic Leaded Chip Carrier Commercial CY7C372i-100JI J67 44-Lead Plastic Leaded Chip Carrier Industrial 83 83 66 66 CY7C372i-83JC J67 44-Lead Plastic Leaded Chip Carrier Commercial CY7C372i-83JI J67 44-Lead Plastic Leaded Chip Carrier Industrial CY7C372i-83YMB Y67 44-Lead Ceramic Leaded Chip Carrier Military CY7C372iL-83JC J67 44-Lead Plastic Leaded Chip Carrier Commercial CY7C372i-66JC J67 44-Lead Plastic Leaded Chip Carrier Commercial CY7C372i-66JI J67 44-Lead Plastic Leaded Chip Carrier Industrial CY7C372i-66YMB Y67 44-Lead Ceramic Leaded Chip Carrier Military CY7C372iL-66JC J67 44-Lead Plastic Leaded Chip Carrier Commercial Document #: 38-03033 Rev. *A Page 10 of 13 CY7C372i MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Switching Characteristics Parameter Subgroups tPD 9, 10, 11 tCO 9, 10, 11 tICO 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11 tIS 9, 10, 11 tIH 9, 10, 11 tICS 9, 10, 11 Package Diagrams 44-Lead Plastic Leaded Chip Carrier J67 51-85003-*A Document #: 38-03033 Rev. *A Page 11 of 13 CY7C372i Package Diagrams (continued) 44-Pin Ceramic Leaded Chip Carrier Y67 51-80014-** ISR, UltraLogic, FLASH370, FLASH370i, Warp, Warp Professional, and Warp Enterprise, are trademarks of Cypress Semiconductor Corporation. Document #: 38-03033 Rev. *A Page 12 of 13 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C372i Document History Page Document Title: CY7C372i UltraLogic™ 64-Macrocell Flash CPLD Document Number: 38-03033 REV. ECN NO. Issue Date Orig. of Change Decsription of Change ** 106378 06/18/01 SZV Change from Spec# 38-00498 to 38-03033 *A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs” Document #: 38-03033 Rev. *A Page 13 of 13