LX1801 Datasheet

LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
KEY FEATURES
DESCRIPTION
ƒ Fully Compliant to Standard
SMBus Specifications
ƒ I2C Bus Compatible
ƒ 8 bit Resolution
ƒ ±10 LSB Accuracy
ƒ One 8 bit ADC
ƒ Three 8 bit DAC’s
ƒ SMBus Address Strap for 2
Selectable Addresses
ƒ External Reference Inputs Set
Analog Brightness Voltage
Lower Limit and Range
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In addition to its SMBus interface,
the LX1801 contains an eight bit ADC,
seven 8 bit registers, three 8 bit DAC’s,
a multiplier, and other special circuits
that process its analog voltage output.
The LX1801 controls inverter on/off
and monitors and reports lamp status
and inverter faults in real time.
The LX1801 is available in the 16
lead 3 x 3mm MLPQ package.
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The LX1801 is a SMBus controlled
dimming interface for CCFL inverters.
It complies with the Dell Inc. M07
specification for Notebook backlight
inverters.
The LX1801 processes 3 brightness
control inputs, one each from the
SMBus, an ambient light sensor, and a
separate system side PWM signal and
generates an analog output signal that
drives the dimming circuitry of a
CCFL inverter controller.
Five
different brightness control modes are
supported which include Intel DPST
display power saving technology.
APPLICATIONS
ƒ Processor and Ambient Light
Senor (ALS) Controlled LCD
Panel Dimming with Intel DPST
ƒ General Purpose SMBus I/O
Control Applications
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PRODUCT HIGHLIGHT
5V
LX1972
Part
ALS
LX1801
ADR0
ALS_IN
I/O
CONN
SMB_DAT
SMB_CLK
INV_PWM
SDA
V_BOT
SCL
VREF_IN
PWM_IN
O
VSS
VDD
Part
VSS
OVR_CUR
FLT_DLY
LMP_ON
EN_OUT
LMP_C
LX169x Based
CCFL Inverter
BRITE_OUT
LX1801
Notebook LCD inverter with 5 SMBus dimming modes including bus driven, ambient light sensor driven, PWM driven, and either SMBus or ALS
with Intel® DPST enhancement.
PACKAGE ORDER INFO
TJ (°C)
LQ
Plastic 3x3 mm MLPQ 16 pin
RoHS Compliant / Pb-free
-40 to 85
LX1801ILQ
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1801ILQ-TR)
Copyright © 2005
Rev. 1.1, 7/7/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
VREF_IN
VDD
14
13
12
VSS
SDA
2
11
FLT_DLY
SCL
3
10
EN_OUT
PWM_IN
4
9
BRITE_OUT
Plastic 3x3 mm MLPQ 16-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
7
8
LMP_ON
LMP_C
VSS
6
OVR_CUR
5
THERMAL DATA
LQ
15
1
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Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
16
ALS_IN
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Supply Input Voltage ........................................................................-0.3V to 7.0V
Input and Output Pins .......................................................................-0.3V to 7.0V
Operating Temperature Range. ……………………………………...-40 to 85°C
Maximum Operating Junction Temperature ................................................ 150°C
Storage Temperature Range...........................................................-65°C to 150°C
Peak Package Solder Reflow Temp (40 seconds max. exposure)..... 260°C(+0,-5)
ADR0
PACKAGE PIN OUT
V_BOT
ABSOLUTE MAXIMUM RATINGS
LQ PACKAGE
(Top View)
33.3°C/W
RoHS / Pb-free 100% Matte Tin Lead Finish
Copyright © 2005
Rev. 1.1, 7/7/2006
PACKAGE DATA
O
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the
above assume no ambient airflow.
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
FUNCTIONAL PIN DESCRIPTION
Description
VDD
Power Supply Input: 4.5V to 5.5V
VSS
Ground (2 Pins)
SCL
Digital Input. SMBus Clock – 10 to 100 KHz capable
SDA
Digital I/O. SMBus Data – SMBus Data line
ADR0
SMBus Address strap input – The address for the LX1801 is determined by the state of this pin (see table 1).
Analog input. Ambient light sensor input. Zero to VREF_IN range.
PWM_IN
A digital input from the system controller whose duty cycle determines lamp brightness when in PWM mode,
and multiplies lamp brightness by a fractional value equal to its duty cycle when in DPST mode.
VREF_IN
V_BOT
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ALS_IN
BRITE_OUT
LMP_C
OVR_CUR
LMP_ON
Analog Input reference voltage for ADC and DAC. Operating range is 1.5 to 3 Vdc. Nominal input is 2.040V.
Input impedance is greater than 10MΩ.
An analog voltage input whose value determines the minimum output voltage of BRITE_OUT after the effect
of the PWM input when in DPST mode and at all times in other modes.
Analog output voltage that is equal to desired BRITE_OUT voltage after modulation by the PWM input and
offset by the voltage at the V_BOT input. An R/C filter at this pin to low pass filters the signal and determines
response time when in PWM and DPST modes. In PWM and DPST modes, the output voltage is modulated
on and off at the duty cycle and frequency of PWM_IN. The R/C filter is comprised of an internal 100K
resistor and an external capacitor to ground.
Lamp Capacitor. A capacitor, typically 10nF and a resistor, typically 1MΩ, are connected in parallel from
this pin to ground. They filter a peak voltage detector with the LMP_ON input.
Analog / Digital input to comparator and latch. Used for over current status input in M07 application. 1.2V
threshold. If OVR_CUR > 1.2VDC, a “1” is latched and written to bit 0 (FAULT) and bit 2(OV_CURR) of the
fault status register (Register 0x02). The latched bits can only be cleared by a write byte command to
register 0x01 to make the LAMP_CTL bit true. If bit 0 or bit 2 of register 0x02 is set, this will reset the
LAMP_CTL bit in register 0x01, causing the enable output to the CCFL controller (EN_OUT) to go low and
turn off the inverter. Zero to VDD input voltage range.
Digital input. Approximately 1V threshold. When LMP_ON is “1” it charges the capacitor at pin LMP_C to
VDD, indicating the lamp is turned on. This pin is normally connected to the A_OUT pin of the LX1692 / 93
controller, and will cause internal circuitry to report the lamp is on if there are pulses on A_OUT. If these
pulses stop long enough for the voltage at LMP_C to decrease below 1.2 V, the lamp is reported off at bit
03 of the FLT/STAT register (0x02). . If LAMP_CTL transitions to high, requesting the inverter to turn on, and
LMP_C does not go above 1.2V before the FLT_DLY pin reaches 2.5V, an open lamp error signal is
produced and is stored, along with other error conditions, to bit zero of the FLT STATUS register 0x02. An
Open lamp fault will cause EN_OUT to go low. See FLT_DLY description. Zero to VDD input voltage range
Digital Output. Enable output to CCFL controller. TTL voltage and current levels. EN_OUT is made high or
low by a write byte command to register 0x01. It is also reset by bit zero of register 0x02 going high.
O
EN_OUT
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
PACKAGE DATA
FLT_DLY
Analog / Digital input to the open lamp comparator and latch. This input provides for a time out before
LMP_ON is sensed for an open lamp fault. The comparator has a 2.5V threshold. The comparator output is
latched when 2.5V is exceeded. The latch is reset at power on and when EN_OUT transitions to high. This
pin is normally connected to the C_TO pin of the LX1692 or 1693 CCFL controller.
Copyright © 2005
Rev. 1.1, 7/7/2006
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Name
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
ELECTRICAL CHARACTERISTICS
Parameter
`
POWER SUPPLY
Operating Supply Voltage
VDD
Average Supply Current
IDD
DAC = FFH; idle ADC
BRIGHTNESS CONTROL DAC DC PERFORMANCE
Resolution
Integral Nonlinearity
INL
CODE = 0 to 255, -10nA < IOUT < 10nA
Differential Nonlinearity
DNL
CODE = 0 to 255, -10nA < IOUT < 10nA
Full Scale Output Voltage
`
`
`
`
FSV
CODE = 255, -10nA < IOUT < 10nA
Offset Error
CODE = 0, -10nA < IOUT < 10nA
Gain Error
-10nA < IOUT < 10nA
LOW LIMIT CLAMP DAC DC PERFORMANCE
Resolution
Low Limit DAC CODE = 15 to 205, High Limit DAC
Relative Accuracy (Note 1)
CODE > 50 LSB above Low Limit DAC CODE
Low Limit DAC CODE = 0, High Limit DAC CODE >
Offset Error
50 LSB above Low Limit DAC CODE
HIGH LIMIT CLAMP DAC DC PERFORMANCE
Resolution
High Limit DAC CODE = 50 to 232, Low Limit DAC
Relative Accuracy (Note 2)
CODE = 50 LSB below High Limit DAC CODE
ALS MODE ACCURACY
Low Limit DAC CODE = 15 to 205, High Limit DAC
Output Error at BRITE_OUT
Code > 50 LSB above Low Limit DAC CODE,
ALS_IN = 20% * VREF to 80% * VREF. VBOT = 0V
ADC
Resolution
Resolvable Input Range
Full Scale Output Voltage
Input Leakage Current (ALS_IN)
Integral Nonlinearity
Differential Nonlinearity
Offset Error
FSV
I_leak
INL
DNL
Gain Error
Min
LX1801
Typ
Max
4.5
1.0
2.5
5.5
4.0
Units
V
mA
8
-9
-2
97% *
VREF
-3
9
5
103% *
VREF
4
ALS_IN = 0V to VDD
Only Major Carry Codes Tested
Only Major Carry Codes Tested
ALS_IN = 0V
ALS_IN = VREF; Read Register. 4
-4
VREF
2
3
8
Bits
LSB
LSB
V
LSB
% of
Ideal
Bits
-10
7
LSB
-1
12
LSB
7
LSB
8
-7
% of
ALS_IN
3
8
0
97% *
VREF
-1
VREF
Bits
VREF
103% *
VREF
+1
-2
±3
±1.5
0
2
-3
2
3
Bits
V
V
µA
LSB
LSB
LSB
% of
FSR
`
`
`
Copyright © 2005
Rev. 1.1, 7/7/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
ELECTRICALS
REF_IN
Reference Voltage
VREF
1.80
2.040
3.00
V
Input Leakage Current
IREF
-50
0
50
nA
ADR
High Level Input Voltage
VAHL
80
%VDD
Low Level Input Voltage
VALL
20
%VDD
Input Leakage Current
IADR
-50
0
50
nA
SCL, SDA, PWM
High Level Input Voltage
VSHL
2.1
V
Low Level Input Voltage
VSLL
0.8
V
Input Leakage Current
ISMB
-5
0
1
µA
SDA Low Level Output Voltage
VOL
IOUT = 3mA
0.4
V
SMBUS
SMB clock frequency
FCLK
10
100
KHz
Note 1: The Relative Accuracy of the Low Limit DAC is specified to be the deviation from the ideal programmed value: Ideal = VREF * (CODE/255).
The Relative Accuracy is specified for the range CODE = 15 to 205
Note 2: The Relative Accuracy of the High Limit DAC is specified to be the deviation from the ideal programmed value: Ideal = VREF * (CODE/255).
The Relative Accuracy is specified for the range CODE = 50 to 232
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`
Test Conditions
85°C except where
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`
Symbol
≤
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Unless otherwise specified, the following specifications apply over the operating ambient temperature -40°C ≤ TA
otherwise noted and the following test conditions: VDD = 5V + 10 / -5%.
LX1801
SMBus to Analog & Digital System Interface
®
TM
P RODUCTION D ATA S HEET
The LX1801 is a seven register device that uses SMBus
commands to communicate with the host system. All registers are
defined as full byte wide with reserved (undefined) bits containing a
default value of “0”. Four of the seven registers are read / write, and
three are read only with respect to the SMBus.
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SMB PROTOCOL
Only standard SMBus protocol, version 2.0 or higher, may be
used for this device. The only required commands are the SMBus
Read Byte and the SMBus Write Byte protocols. There are to be no
non standard protocols implemented. Further, register contents shall
not be altered by invalid commands.
Writes to registers can be performed by either the SMBus Write
Byte protocol and / or by internal IC logic, depending on the register
type (see table 1).
Reads can be performed on all seven registers by issuing the
Read_Byte protocol.
Read Only registers can be written only by internal logic. Their
contents can not be affected by SMBus write commands.
Specific Requirements for SMBus Protocols:
• The IC shall implement the SMBus Read Byte protocol.
• The IC shall implement the SMBus Write Byte protocol.
• The IC shall not require the use of any other SMBus protocol to
meet the requirements contained in the Dell M07 specification.
• The IC shall operate correctly when the SMBus master clock
operates at a frequency of 55KHz and over the complete
frequency range of 10KHz to 100KHz.
• The IC shall not employ clock stretching.
• The IC shall not include SMBus pull up resistors. These are
provided by the host system.
General Rules for Writing and Reading LX1801 Registers with
the SMBus.
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APPLICATION NOTE
Read Byte Protocol:
S
1
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte
Ā
P
7
1
1
8
1
1
7
1
1
8
1
1
Write Byte Protocol:
S
Slave Address
Wr
A
Command Code
A
Data Byte
Ā
P
1
7
1
1
8
1
8
1
1
Grey shading represents cycles during which the LX1801 “owns” or “drives” the Data line. All other cycles are driven by the host.
Definitions
Start condition
Write
Read
Acknowledge
Stop Condition
O
S:
Wr:
Rd:
A:
P:
Protocol must be per standard SMB specification version 2.0 or higher.
APPLICATIONS
Copyright © 2005
Rev. 1.1, 7/7/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
SMBus De-featuring
Packet Error Correction (PEC) and the Alarm function are not supported.
DEVICE ADDRESS:
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In this document the device address is always expressed as a full 8 bit address. The high nibble of the address is always 5H. In the low nibble
bit 0 is always the R/W bit, and bits 3-1 are A2, A1, and A0. This device implements one address strap at A0. When this strap is grounded
the resulting device address is 58(H); when pulled to 5V, the resulting device address is 5A(H). The state of the A0 strap is sensed at Power
on reset. The pin will not change state when the system is in operation.
REGISTER DEFINITIONS:
DESCRIPTION
ADDR
TYPE
0x00
6
R/W
BRT7
BRT6
BRT5
BRT4
0x01
R/W
RESRV
D
RESRVD
ALS DLY1
(OPTION)
ALS DLY0
(OPTION)
FAULT / STATUS
0x02
R/O
RESRVD
RESRVD
RESRVD
RESRVD
IDENTIFICATION
ALS STATUS
ALS LOW LIMIT
ALS HIGH LIMIT
0x03
0x04
0x05
0x06
R/O
R/O
R/W
R/W
MFG4
ALS7
ALSLL7
ALSHL7
MFG3
ALS6
ALSLL6
ALSHL6
MFG2
ALS5
ALSLL5
ALSHL5
MFG1
ALS4
ALSLL4
ALSHL4
BRIGHTNESS
CONTROL
DEVICE
CONTROL
5
BIT DEFINITIONS
4
3
7
2
1
0
BRT3
BRT2
BRT1
BRT0
ALS_CTL
PWM_MD
PWM_SEL
LMP_CTL
LMP_ST
1= LAMP
IS ON
MFG0
ALS3
ALSLL3
ALSHL3
OV_CUR
1= OVER
CURENT
REV2
ALS2
ALSLL2
ALSHL2
THR_SD
1= OVER
TEMP
REV1
ALS1
ALSLL1
ALSHL1
FAULT
1= ANY
FAULT
REV0
ALS0
ALSLL0
ALSHL0
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APPLICATION NOTE
Specific requirements for Register 4:
1. Register 0x04 reads always produce the digitized raw ALS_IN voltage, independent of what mode has been set. This data will not
include the effect of DPST if DPST is active, or the effect of the high and low limit registers.
Copyright © 2005
Rev. 1.1, 7/7/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
APPLICATIONS
O
Specific requirements for Register 0:
1. A Write Byte cycle shall set the brightness level if the IC is in SMBus mode as selected by bits 3-1 of the Device control register.
2. A Write Byte cycle shall have no effect on the BRITE_OUT pin when the IC is not in the SMBus mode.
3. A Read Byte cycle shall return the current brightness level regardless of the value of PWM_SEL.
4. When in SMBus or SMBus + DPST mode, register 0x00 must reflect exactly the last value written to it via the SMBus, not a
digitized version of the analog brightness control output voltage. If DPST is active a read to register 0x00 shall not include its
affect.
5. When the PWM or ALS or ALS+DPST mode is set, register 0x00 reads will return the digitized DC brightness control voltage
exclusive of any offset produced from the V_BOT input. Range of the read voltage is from zero to VREF_IN.
6. A value of 0xFF shall set the BRITE_OUT level to maximum brightness.
7. A value of 0x00 shall set the BRITE_OUT level to minimum brightness.
8. The default value shall be 0xFF.
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
LX1801 COMMANDS
W
0x01
R
0x01
W
0x02
R
W
R
W
R
W
R
W
0x02
0x03
0x03
0x04
0x04
0x05
0x05
0x06
0x06
Copyright © 2005
Rev. 1.1, 7/7/2006
APPLICATIONS
O
R
Description
Write an 8 bit data byte to the Brightness Control register.
Read the 8 bit data byte stored in the Brightness Control register.
Write an 8 bit control byte to the Device Control Register.
See the M07 specification for command details.
Read the 8 bit control byte from the Device Control Register.
See the M07 specification for command details.
Write the 8 bit Fault / Status Register.
This register shall ignore write operations. It is read only.
Read the 8 bit Fault / Status Register.
See the M07 specification for command details.
Write the 8 bit Identification Register.
This register shall ignore write operations. It is read only.
Read the 8 bit Identification Register.
See the M07 specification for command details.
Write the 8 bit ALS Status Register.
This register shall ignore write operations. It is read only.
Read the 8 bit ALS Status Register.
See the M07 specification for command details.
Write the 8 bit ALS Low Limit Register.
See the M07 specification for command details.
Read the 8 bit ALS Low Limit Register.
See the M07 specification for command details.
Write the 8 bit ALS High Limit Register.
See the M07 specification for command details.
Read the 8 bit ALS High Limit Register.
See the M07 specification for command details.
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Register
0x00
0x00
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W/R
W
R
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Integrated Products Division
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Page 7
LX1801
SMBus to Analog & Digital System Interface
®
TM
P RODUCTION D ATA S HEET
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
REVISION X2 k
3 November 05 Microsemi Integrated Products
PWM_IN
PWM_MD
PWM_SEL
ALS_CTL
V_REF
ALS_CTL
100K
BRITE_OUT
PWM_SEL
VSS1
SMBus
DAC
0
0
-
A
MUX
+
1
A
MUX
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5VDC
BRITE
0X00
1
V_REF
VSS2
5VDC
5VDC
V_REF
ALS
LOW
0X05
C2
100nF
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LX1801
DAC
1P2V
V_REF
2P5V
5V
5VDC
+
V_REF
VDD
V_BOT
+
-
ALS
HIGH
0X06
LX1972
ALS
BRITE_OUT
-
DAC
0
A
MUX
ADC
ALS 0X04
SMDATA
100K
1
100K
ALS-IN
RD_ALS
+
R1
20.0K
C1
100K
SCL
-
SDA
ID/
REV
0X03
OVR_CUR
+
ADR0
-
FLT-DLY
C3
10 nF
LMP_C
R2
40K
OPN LMP
-
S
+
LMP_ON
VDD_A
SMBus CONTROL
Q
R
5V
-
FAULT
0
FLT/
1 STAT
LATCH
2 0x02
3 RST
THRM_SHDN
OV_CURR
LAMP_STAT
RST_
LAMP_
CTL
DVC
CTL
0X01
ALS DLY (N/U)
ALS DLY (N/U)
ALS_CTL
PWM_MD
PWM_SEL
LAMP_CTL
VREF_IN
V_REF
-
200MV
+
LAMP_CTRLPOSEDGE
R4
10K
EN_OUT
POR
R5
1M
R3
30K
+
O/S
Copyright © 2005
Rev. 1.1, 7/7/2006
APPLICATIONS
O
Figure 1 – Block Diagram
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 8
LX1801
SMBus to Analog & Digital System Interface
®
TM
P RODUCTION D ATA S HEET
APPLICATION CIRCUITS
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LX1692 WIDE INPUT VOLTAGE RANGE NOTEBOOK INVERTER
with ALS & INTEL DPST FOR DELL M07 Inverters
LX1801 Application Schematic With LX1962 REV 4NOV05.VSD
40 COMPONENTS
INV_SRC
10uF
GND
LX1801
5VALW
2
3
SMB_DAT
4
5
INV_PWM
ADR0
VDD
16
5VALW
15
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SMB_CLK
1
6
7
8
SCL
BRITE_OUT
SCD
VSS2
PWM_IN
EN_OUT
VREF_IN
FLT_DLY
V_BOT
LMP_ON
ALS_IN
VSS1
LMP_C
OVR_CUR
FDC6333C
14
1
13
2
12
3
11
5VALW
LX1692
10
9
1
2
INV_SRC
3
4
5
6
VDDA
7
8
9
5VALW
ALS
10
VDDA
VDDP
C_R
AOUT
C_BST
BOUT
C_TO
GND
I_R
COUT
ENABLE
DOUT
BRITE_A
I_SNS
VIN_SNS
OV_SNS
BRITE_D
ICOMP
VCOMP
OC_SNS
G2P
D2P
S2P
S1N
G1N
D1N
6
5
4
FDC6333C
20
1
19
2
18
3
G2P
D2P
S2P
S1N
G1N
D1N
JST
SMO2
6
5
4
17
16
15
14
13
12
11
LX1972
Copyright © 2005
Rev. 1.1, 7/7/2006
APPLICATIONS
O
Figure 2 – Typical Application
Microsemi
Integrated Products Division
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Page 9
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
THEORY OF OPERATION
The LX1801 contains three 8 bit DAC’s, an 8 bit ADC and a
SMBus interface with 7 addressable registers to control 5 dimming
modes for a notebook backlight inverter. The ADC contains a track
and hold input that stores the analog voltage level while the
conversion is being processed. Several special circuits are also
present in the LX1801. Analog comparators and a 2 bit R/S register
detect and latch inverter fault conditions. Another analog comparator
monitors real time on / off status of the CCFL lamp and writes it,
along with inverter fault status to a host readable register.
The LX1801 communicates over the SMBus in the slow speed
Low Power Level and operates in a “slave” mode receiving
commands and sending and receiving data from the host or bus
“master”. The LX1801 can be configured for one of two addresses
by connecting the ADR0 input to 5V or ground. Addresses 0x58
and 0x5A can be selected with the strapping code below:
bs
ol
et
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SMBUS INTERFACE
An analog multiplier provides the ability for implementing IntelTM
DPST (Display Power Savings Technology), and voltage limiting
clamps on the ALS input provide SMBus programmable range
limiting of the ambient light sensor output signal.
Table 1. Address strapping codes
Option #
ADR 0
Hex Address
0V
:058
1
5V
:05A
2
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BASIC FUNCTIONALITY
APPLICATION NOTE
LAYOUT GUIDELINES
Copyright © 2005
Rev. 1.1, 7/7/2006
APPLICATIONS
O
The LX1801 is sensitive to noise at the analog input pins so these
nodes should be a low impedance path to ground for high frequency
noise. As a precaution, the BRITE_OUT and ALS _IN pins should
be routed away from digital switching traces and have ceramic
capacitors located close to the package pins. The VDD Pin should be
decoupled to ground with a 0.1uF ceramic capacitor located as close
as possible to the IC.
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
LX1801
SMBus to Analog & Digital System Interface
®
TM
P RODUCTION D ATA S HEET
PACKAGE DIMENSIONS
D
b
E2
E
D2
e
A1
MILLIMETERS
MIN
MAX
0.80
1.00
0
0.05
0.20 REF
0.18
0.30
3.00 BSC
3.00 BSC
0.50 BSC
1.30
1.55
1.30
1.55
0.2
0.35
0.50
0.15
INCHES
MIN
MAX
0.031
0.039
0
0.002
0.008 REF
0.007
0.012
0.118 BSC
0.118 BSC
0.020 BSC
0.051
0.061
0.051
0.061
0.008
0.012
0.020
0.006
bs
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e
L
Dim
A
A1
A3
b
D
E
e
D2
E2
K
L
L1
A
K
or
Pin 1 Indicator
A3
Note:
1.
Dimensions do not include mold flash or
protrusions; these shall not exceed 0.155mm(.006”)
on any side. Lead dimension shall not include
solder coverage.
Due to multiple qualified assembly sub-contractors
either package (with different pin one indicators)
may be shipped. Package type will be consistent
within the smallest individual container.
MECHANICALS
O
2.
Copyright © 2005
Rev. 1.1, 7/7/2006
WWW . Microsemi .C OM
16-Pin MLPQ 3x3
LQ
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 11
LX1801
®
TM
SMBus to Analog & Digital System Interface
P RODUCTION D ATA S HEET
NOTES
O
bs
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NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright © 2005
Rev. 1.1, 7/7/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 12