INTEGRATED CIRCUITS CBTV4010 10-bit DDR SDRAM mux/bus switch Product data File under Integrated Circuits — ICL03 2002 Feb 19 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 FEATURES DESCRIPTION • Enable signal is SSTL_2 compatible • Optimized for use in Double Data Rate (DDR) SDRAM applications This 10-bit bus switch is designed for 2.3 V to 2.7 V VCC operation and SSTL_2 select input levels. Each Host port pin is multiplexed to one of four DIMM port pins. When the S pin is low the corresponding 10-bit bus switch is turned on. The on-state connects the Host port to the DIMM port through a 20 Ω nominal series resistance. When the S pin is high the switch is open and a high-impedance state exists between the two ports. The DIMM port is terminated with a 100 Ω resistor to ground when the S pin is high. The design is intended to have only one DIMM port active at any time. • Designed to be used with 400 Mbps/200 MHz DDR data bus • Switch on resistance is designed to eliminate the need for series resistor to DDR SDRAM • 20 Ω on resistance • Internal 100 Ω pull-down resistors • Low differential skew • Matched rise/fall slew rate The part incorporates a very low cross-talk design. It has a very low skew between outputs (< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optional performance in DDR data bus applications. • Low cross-talk data-data/data-DQM • Independent DIMM control lines • Latch-up protection exceeds 500 mA per JESD78 • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Each switch has been optimized for connection to 1 or 2-bank DIMMs. The low internal RC time constant of the switch (20 Ω × 7 pF) allows data transfer to be made with minimal propagation delay. The CBTV4010 is characterized for operation from 0 to +85 °C. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25 °C; GND = 0 V PARAMETER TYPICAL UNIT tPLH tPHL Propagation delay An to Yn CL = 7 pF; VCC = 2.5 V 140 ps CIN Input capacitance – control pins VI = 0 V or VCC 1.8 pF CON Channel on capacitance Vin = 1.5 V 7 pF ICCZ Total supply current VCC = 2.5 V 500 µA ORDERING INFORMATION PACKAGES TFBGA64 (Thin Fine Pitch BGA) 2002 Feb 19 TEMPERATURE RANGE ORDER CODE DWG NUMBER 0 to +85 °C CBTV4010EE SOT746-1 2 853-2315 27756 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 64-BALL BGA CONFIGURATION 1 2 3 A VDD S1 NC B S2 VDD S0 C NC S3 GND 3DP2 E 2DP9 3DP9 0DP3 1DP3 F 1DP9 HP9 HP3 2DP3 0DP9 3DP8 GND 3DP3 2DP8 0DP4 D G H 4 GND J 1DP8 HP8 K 0DP8 GND HP7 L 3DP7 2DP7 1DP7 0DP7 5 6 7 1DP0 2DP0 3DP0 0DP0 HP0 0DP1 3DP6 HP6 GND 2DP6 1DP6 0DP6 PIN DESCRIPTION PIN NUMBER SYMBOL HP0–HP9 NAME AND FUNCTION Host ports A2, B1, B3, C2 S0–S3 A5, A6, A7, A9, A10, A11, B5, B7, B8, B11, C11, D10, E1, E2, E10, E11, F1, F11, G1, G2, G11, H2, H10, J1, J11, K1, K4, K5, K8, K10, K11, L1, L2, L3, L5, L6, L7, L9, L10, L11 0DP0–3DP3 0DP1–3DP1 0DP2–3DP2 0DP3–3DP3 0DP4–3DP4 0DP5–3DP5 0DP6–3DP6 0DP7–3DP7 0DP8–3DP8 0DP9–3DP9 B10, D2, G10, K2, K7, GND Ground A1, B2 VDD Positive supply voltage Select DIMM ports FUNCTION TABLE INPUT S FUNCTION L Host port = DIMM port H Host port = Disconnect DIMM port = 100 Ω to GND H = High voltage level L = Low voltage level 2002 Feb 19 1DP1 3DP5 9 10 11 2DP1 3DP1 0DP2 HP1 GND 1DP2 HP2 2DP2 HP4 1DP4 HP5 3DP4 2DP4 2DP5 1DP5 0DP5 SA00589 NOTE: BLANK SPACE INDICATES NO BALL B6, B9, C10, F2, F10, J2, J10, K3, K6, K9 8 3 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 SIMPLIFIED SCHEMATIC, EACH FET SWITCH HPx A LOGIC DIAGRAM (POSITIVE LOGIC) nDPx Sw B HP0 0DP0 Sw 1DP0 Sw 100 Ω 2DP0 Sw Sn Sw HP9 3DP0 0DP9 Sw SW00889 1DP9 Sw 2DP9 Sw Sw 3DP9 S0 S1 S2 S3 SW00901 ABSOLUTE MAXIMUM RATINGS1, 3 SYMBOL VCC PARAMETER CONDITIONS RATING DC supply voltage –0.5 to +3.3 V –50 mA IIK DC input clamp current VI DC input voltage range (S pin only)2 VCC + 0.3 V Storage temperature range –65 to 150 °C DC input voltage range (except S pin)2 –0.5 to 3.3 V Tstg VI VI/O < 0 UNIT NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER Min Typ Max UNIT VCC DC supply voltage 2.3 2.5 2.7 V VIH High-level input voltage DIMM port and Host 1.6 — — V VIL Low-level Input voltage DIMM port and Host — — 0.9 V Operating free-air temperature range 0 — +85 °C Tamb NOTE: 1. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. 2002 Feb 19 4 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL VIK II PARAMETER Tamb = 0 to +85 °C TEST CONDITIONS Input clamp voltage VCC = 2.3 V; II = –18 mA Input leakage current VCC = 2.5 V; VI = VCC or GND; S = VCC S = GND for IIL (test) UNIT Min Typ1 Max — — –1.2 S — — ±100 Host port — — ±100 DIMM port — — ±100 V µA ICC Quiescent supply current VCC = 2.5 V; IO = 0, VI = VCC or GND — 0.7 1.5 mA Cin Control pin capacitance VI= 2.5 V or 0 — 1.8 3 pF Con Switch on capacitance Vin= 1.5 V — — 10 pF ron2 On-resistance VCC = 2.5 V; VA = 0.8 V; VB = 1.0 V 16 20 30 VCC = 2.5 V; VA = 1.7 V; VB = 1.5 V 16 20 30 Ω NOTES: 1. All typical values are at VCC = 2.5 V, Tamb = 25 °C 2. Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side of the switch. 3. Capacitance values are measured at a of 10 MHz and a bias voltage 3 V. Capacitance is not production tested. AC CHARACTERISTICS SYMBOL PARAMETER tpd Propagation delay1 FROM (INPUT) TO (OUTPUT) HPx or xDPx VCC = +2.5 V ±0.2 V UNIT Min Typ Max xDPx or HPx — — 140 ps ten enable Sn HPx or nDPx 1 — 2 ns tdis disable Sn HPx or nDPx 1 — 3 ns tosk Output skew Any output to any output, Waveform 4 (see note 2) — 25 50 ps tesk Edge skew Difference of rising edge propagation delay to falling edge propagation delay, Waveform 5 (see note 2) — 25 50 ps NOTES: 1. The propagation delay is based on the RC time constant of the typical on–state resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance); 20 Ω × 7 pF. This parameter is not production tested. 2. Skew is not production tested. 2002 Feb 19 5 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 HPx to nDPx AC WAVEFORMS AND TEST CIRCUIT AC WAVEFORMS TEST CIRCUIT HPx to xDPx 2.5 V 1.25 V 1.25 V tPLH tPHL From Output Under Test D or H 0V CL = 30 pF VOH 1.25 V Load Circuit 1.25 V DEFINITIONS Load capacitance includes jig and probe capacitance CL = H or D VOL SA00622 SA00620 Waveform 1. Input (D or H) to Output (H or D) Propagation Delays Sn (Low-level enabling NOTES: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. The outputs are measured one at a time with one transition per measurement. 2.5 V 1.25 V 1.25 V 0V Output nDPx (see Note) VOL tPHZ tPZH VOH VOH – 0.15 V 1.25 V VOL Note: The output is high except when disabled by the Sn control. SA00621 Waveform 2. 3-State Output Enable and Disable Times 2002 Feb 19 500 Ω 6 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 nDPx to HPx AC WAVEFORMS AND TEST CIRCUIT AC WAVEFORM TEST CIRCUIT nDPx to HPx 2.5 V Sn (Low-level enabling 1.25 V 1.25 V 2 × VCC 500 Ω From Output Under Test SW Open GND 0V 500 Ω CL = 30 pF tPLZ tPZL 2.5V Output HPx SW at 4.3 V (see Note 1) Load Circuit 1.25 V VOL + 0.3V VOL tPHZ tPZH VOH Output HPx SW at Open (see Note 2) VOH – 0.3V 1.25 V VOL TEST SW tpd open tPLZ/tPZL 2 × VCC tPHZ/tPZH GND DEFINITIONS Load capacitance includes jig and probe capacitance CL = Note: 1. The output is low except when disabled by the Sn control. 2. The output is high except when disabled by the Sn control. SA00624 SA00623 NOTES: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. The outputs are measured one at a time with one transition per measurement. Waveform 3. 3-State Output Enable and Disable Times skew ANY TWO OUTPUTS SW00396 Waveform 4. Skew Between Any Two Outputs 2.5 V 1.25 V 1.25 V INPUT 0V FALLING EDGE SKEW VOH RISING EDGE SKEW 1.25 V 1.25 V OUTPUT VOL SA00568 Waveform 5. Rising and Falling Edge Skew 2002 Feb 19 7 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 7 x 7 x 0.7 mm 2002 Feb 19 8 SOT746-1 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 NOTES 2002 Feb 19 9 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 02-02 For sales offices addresses send e-mail to: [email protected]. Document order number: 2002 Feb 19 10 9397 750 09463