D2 PA K PSMN5R0-80BS N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK Rev. 1 — 20 March 2012 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in SOT404 package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for standard level gate drive sources 1.3 Applications DC-to-DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 100 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 270 W Tj junction temperature -55 - 175 °C - 7.19 8.5 mΩ - 4.36 5.1 mΩ [1] Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 13; see Figure 12 VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12 Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge VGS = 10 V; ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 21 - nC - 101 - nC - - 396 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain[1] Simplified outline Graphic symbol mb 3 S source mb D mounting base; connected to drain D G mbb076 S 2 1 3 SOT404 (D2PAK) [1] It is not possible to make connection to pin 2 3. Ordering information Table 3. Ordering information Type number PSMN5R0-80BS Package Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) 4. Marking Table 4. Marking codes Type number Marking code PSMN5R0-80BS PSMN5R0-80BS PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 2 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 80 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 [1] - 100 A VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] - 100 A - 598 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 270 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 100 A Source-drain diode [1] IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 598 A VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped - 396 mJ Avalanche ruggedness non-repetitive drain-source avalanche energy EDS(AL)S [1] Continuous current is limited by package 003aad078 150 ID (A) 03aa16 120 Pder (%) 80 100 (1) 50 40 0 0 0 Fig 1. 50 100 150 Tmb (°C) 200 Product data sheet 50 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature PSMN5R0-80BS 0 Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 3 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 003aad299 103 Limit RDSon = VDS / ID ID (A) tp = 10 μs 102 100 μs (1) 10 DC 1 10-1 10-1 Fig 3. 1 10 1 ms 10 ms 100 ms 102 VDS (V) 103 Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 4 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.3 0.56 K/W Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 50 - K/W 003aad080 1 Zth(j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 0.05 10-2 0.02 δ= P tp T 10-3 single shot t tp T 10-4 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration; typical values PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 5 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 7. Characteristics Table 7. Characteristics Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit 73 - - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C VGS(th) gate-source threshold voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 1 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 4.6 V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11; see Figure 10 2 3 4 V IDSS drain leakage current VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.02 8 µA VDS = 80 V; VGS = 0 V; Tj = 125 °C - - 150 µA IGSS gate leakage current VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 12; see Figure 13 - 10.46 12.3 Ω VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 13; see Figure 12 - 7.19 8.5 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12 - 4.36 5.1 mΩ f = 1 MHz - 0.95 - Ω 87 - nC RDSon RG internal gate resistance (AC) Dynamic characteristics QG(tot) total gate charge ID = 0 A; VDS = 0 V; VGS = 10 V - 101 - nC gate-source charge ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - QGS - 26 - nC QGS(th) pre-threshold gate-source charge - 18 - nC QGS(th-pl) post-threshold gate-source charge - 8 - nC QGD gate-drain charge - 21 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 4.2 - V Ciss input capacitance - 6793 - pF Coss output capacitance VDS = 40 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 913 - pF Crss reverse transfer capacitance - 350 - pF td(on) turn-on delay time tr rise time td(off) tf VDS = 40 V; RL = 0.5 Ω; VGS = 10 V; RG(ext) = 4.7 Ω - 33 - ns - 21 - ns turn-off delay time - 73 - ns fall time - 14 - ns PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 6 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK Table 7. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit - 0.8 1.2 V Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 trr reverse recovery time Qr recovered charge IS = 25 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 40 V 003aad081 250 ID (A) 20 10 6 5.5 - 56 - ns - 116 - nC 003aad083 100 ID (A) 80 200 5 150 60 100 40 4.5 50 Tj = 175 °C 20 25 °C VGS (V) = 4 0 0 0 Fig 5. 1 2 3 V (V) 4 DS Output characteristics: drain current as a function of drain-source voltage; typical values 003aad087 10000 C (pF) 9000 Ciss 0 Fig 6. 3 4 VGS (V) 5 003aad088 140 gfs (S) 120 100 7000 80 60 Crss 5000 40 4000 20 0 3000 2 Fig 7. 2 Transfer characteristics: drain current as a function of gate-source voltage; typical values 8000 6000 1 4 6 8 VGS (V) Input and reverse transfer capacitances as a function of gate-source voltage; typical values PSMN5R0-80BS Product data sheet 0 10 Fig 8. 20 40 60 80 100 120 ID (A) Forward transconductance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 7 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 003aad089 40 003aad280 5 VGS(th) (V) RDSon (mΩ) 4 max 30 3 typ 20 2 min 10 1 0 0 Fig 9. 5 10 15 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values 03aa35 10−1 ID (A) min 10−2 typ 0 −60 0 120 180 Tj (°C) Fig 10. Gate-source threshold voltage as a function of junction temperature 003aad082 10 RDSon (mΩ) max 60 VGS (V) = 5 8 5.5 10−3 6 6 10−4 10 4 10−5 20 10−6 2 0 2 4 6 0 50 VGS (V) Fig 11. Sub-threshold drain current as a function of gate-source voltage PSMN5R0-80BS Product data sheet 100 150 200 ID (A) 250 Fig 12. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 8 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 003aad045 2.5 VDS a ID 2.0 VGS(pl) 1.5 VGS(th) VGS 1.0 QGS1 QGS2 QGS 0.5 QGD QG(tot) 003aaa508 0.0 -60 -30 0 30 60 90 120 150 180 Tj (°C) Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature 003aad085 10 VGS (V) Fig 14. Gate charge waveform definitions 003aad086 104 Ciss 8 C (pF) 6 VDS = 40 V 103 Coss 4 Crss 2 0 0 20 40 60 80 100 120 QG (nC) Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN5R0-80BS Product data sheet 102 10-1 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 9 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 003aad084 100 IS (A) 80 60 40 175 °C 20 Tj = 25 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 VSD (V) Fig 17. Source current as a function of source-drain voltage; typical values PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 10 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 8. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 11 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 9. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN5R0-80BS v.1 20120320 Product data sheet - - PSMN5R0-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2012 © NXP B.V. 2012. All rights reserved. 12 of 15 PSMN5R0-80BS NXP Semiconductors N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK 10. 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Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 10.1 10.2 10.3 10.4 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contact information. . . . . . . . . . . . . . . . . . . . . .14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 20 March 2012 Document identifier: PSMN5R0-80BS