Features • Low-power Operation Including Special STOP Mode • Frequency: 16.78 MHz at 5V ± 10% Supply and 20.97 MHz at 5V ± 5%, Software Programmable • Technology: 1µ High-density Complementary Metal-Oxide Semiconductor (HCMOS), Static Design • Package: 132-pin Ceramic Leaded Chip Carrier (CERQUAD) and 132-pin Ceramic Pin • • • • • • • • • Grid Array (PGA) Modular Architecture in a Single Chip CPU: 32-bit 6800 Family (Upward Object-code Compatible with The 68010) New Instructions For Controller Applications Intelligent 16-bit Timer – 16 Independent, Programmable Channels – Any Channel Can Perform Any Time Function (For Example Input Capture, Output Compare, Pulse Width Modulation, etc.) – Two timer Count Registers with 2-bit Programmable Prescalers – Selectable Channel Priority Levels – Reduced CPU Intervention – RISC like CPU within the TPU Two Serial I/O Subsystems – Enhanced 68HC11-type Serial Communications Interface (SCI) Universal Asynchronous Receiver Transmitter (UART) with Parity – Enhanced 68HC11-type Serial Peripheral Interface with I/O RAM Queue (QSPI) On-chip Memory: 2-Kbytes Standby RAM On-chip, Programmable, Chip-select Logic – Up to 12 Signals for Memory and Peripheral Interface with I/O Select System Failure Protection – 68HC11-type Computer Operating Properly (COP) Watchdog Timer – 68HC11-type Periodic Interrupt Timer – 68000 Family Spurious Interrupt, Halt, and Bus Time-out Monitors Up to 48 Discrete I/O Pins Highperformance 32-bit Integrated Microcontroller TS68332 1. Description The TS68332 is a 32-bit microcontroller, combining high-performance data manipulation capabilities with powerful peripheral subsystems. The TS68332 is the first member of the 68300 family of modular embedded controllers featuring fully static, high-speed complementary metal-oxide semiconductor technology. Based on the powerful TS68020, the CPU32 instruction processing module provides enhanced system performance and utilizes the extensive software base of the 68000 family. 2118A–HIREL–11/05 Screening/Quality This product is manufactured in full compliance with: • MIL-STD-883 (class B) • DSCC 5962-91501 • Or according to Atmel-Grenoble standard R suffix PGA 132 Ceramic Pin Grid Array A suffix CERQUAD 132 Ceramic Leaded Chip Carrier 2. Introduction Figure 2-1 on page 3 is a block diagram of the TS68332 showing the major components. The pin descriptions are provided in Table 2-1 on page 6. The TS68332 contains intelligent peripheral modules such as the Time Processor Unit (TPU), which provides 16 microcoded channels for performing time-related activities from simple input capture or output compare to complicated motor control or pulse width modulation. High-speed serial communications are provided by the Queued Serial Module (QSM) with synchronous and asynchronous protocols available. 2Kbytes of fully static standby RAM allow fast two-cycle access for system and data stacks and variable storage with provision for battery back-up. There is a System Integration Module (SIM) which includes twelve chip selects to enhance system integration for fast external memory or peripheral access. The powerful 32-bit CPU (CPU 32) is based on the industry-standard TS68020. These modules are connected on chip via the Intermodule Bus (IMB) and provide reduced system part count, size, cost of implementation and increased reliability. 2 TS68332 2118A–HIREL–11/05 TS68332 Figure 2-1. Block Diagram of TS68332 VSTBY CHIP SELECTS TPUCH[15:0] TPUCH[15:0] T2CLK 2 KBYTES RAM TPU FC2 FC1 FC0 ADDR[23:19] T2CLK CONTROL PORT C BR BG BGACK CS[10:0] RXD PQS7/TXD PQS6/PCS3 QS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO PORT QS CONTROL TXD PCS3 PCS2 PCS1 PCS0/SS SCK MOSI MISO ADDR[23:0] ADDR[18:0] SIZ1 SIZ0 EBI DS AS RMC AVEC DSACK1 DSACK0 PE7/SIZ1 PE6/SIZ0 PE5/DS PE4/AS PE3/RMC PE2/AVEC PE1/DSACK1 PE0/DSACK0 CONTROL PORT E IMB DATA[15:0] DATA[15:0] IRQ[7:1] CPU 32 CONTROL PORT F QSM MODCLK TSC TEST QUOT R/W RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK CLKOUT XTAL EXTAL XFC VDDSYN TSC CONTROL CONTROL BKPT IFETCH IPIPE DSI DSO DSCLK FREEZE CLOCK BKPT/DSCLK IFETCH/DSI IPIPE/DSO CSBOOT ADDR23/CS10 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 BGACK/CS2 BG/CS1 BR/CS0 FREEZE/QUOT 3 2118A–HIREL–11/05 Figure 2-2. 4 PGA Terminal Designation TS68332 2118A–HIREL–11/05 TS68332 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 ADDR23/CS10 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 VSS CERQUAD Terminal Designation VSS TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7 VSS VDD TPUCH8 TPUCH9 TPUCH10 TPUCH11 VSS VDD TPUCH12 TPUCH13 TPUCH14 TPUCH15 T2CLK VSS VDD Figure 2-3. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TOP VIEW 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 VDD BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 DATA3 VDD VSS DATA4 DATA5 DATA6 DATA7 VSS DATA8 DATA9 DATA10 DATA11 VDD VSS DATA12 DATA13 DATA14 DATA15 ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE5/DS VDD VSS PQS7/TXD RXD IPIPE/DSO IFETCH/DSI BKPT/DSCLK TSC FREEZE/QUOT VSS XTAL VDDSYN EXTAL VDD XFC VDD CLKOUT VSS RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK R/W PE7/SIZ1 PE6/SIZ0 AS VSS 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 VDD VSTBY ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VDD VSS ADDR9 ADDR10 ADDR11 ADDR12 VSS ADDR13 ADDR14 ADDR15 ADDR16 VDD VSS ADDR17 ADDR18 PQS0/MISO PQS1/MOSI PQS2/SCK PQS3/PCS0/SS PQS4/PCS1 PQS5/PCS2 PQS6/PCS3 VDD 5 2118A–HIREL–11/05 2.1 Signal Description Figure 2-1 on page 3 illustrates the functional signal groups and Table 2-1 lists the signals and their function. Table 2-1. Signal Index Signal Name Mnemonic Function Address Bus A23 - A0 24-bit address bus Data Bus D15 - D0 16-bit data bus used to transfer byte or word data per bus cycle Data Bus Function Codes FC2 - FC0 Identify the processor state and the address space of the current bus cycle Boot Chip Select CSBOOT Chip-select boot stat up ROM containing user’s reset vector and initialization program Chip Selects CS10 - CSO Enables peripherals at programmed addresses Bus Request BR Indicates that an external device requires bus mastership Bus Grant BG Indicates that current bus cycle is complete and the TS68332 has relinquished the bus Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership Data and Size Acknowledgement DSACK1, DSACK0 Provides asynchronous data transfers and dynamic bus sizing Autovector AVEC Requests an automatic vector during an interrupt acknowledge cycle Read-Modify-Write Cycle RMC Identifies the bus cycle as part of an indivisible read-modify-write cycle Address Strobe AS Indicates that a valid address is on the address bus Data Strobe DS During a read cycle, DS indicates that an external device should place valid data on the data bus. During a write cycle, DS indicates that valid data is on the data bus. Size SIZ1 - SIZ0 Indicates the number of bytes remaining to be transferred for this cycle Read/Write R/W Indicates the direction of data transfer on the bus Interrupt Request Level IRQ7 - IRQ0 Provides an interrupt priority level to the CPU Reset RESET System reset Halt HALT Suspend external bus activity Bus Error BERR Indicates that an erroneous bus operation is being attempted System Clockout CLKOUT Internal system clock Crystal Oscillator EXTAL, XTAL Connection for an external crystal to the internal oscillator circuit External Filter Capacitor XFC Connection pin for an external capacitor to filter the circuit of the phase-locked loop Clock Mode Select MODCK Selects the source of the internal system clock Instruction Fetch IFETCH Indicates when the CPU is performing an instruction word pre-fetch and when the instruction pipeline has been flushed Instruction Pipe IPIPE Used to track movement of words through the instruction pipeline Breakpoint BKPT Signals a hardware breakpoint to the CPU Freeze FREEZE Indicates that the CPU has acknowledged a breakpoint Quotient Out QUOT Serial I/O and clock for background debug mode Test Mode Enable TSTME Hardware enable for test mode Three-State Control TSC Places all output drivers in a high-impedance state 6 TS68332 2118A–HIREL–11/05 TS68332 Table 2-1. Signal Index (Continued) Signal Name Mnemonic Function Development Serial In, Out, Clock DSI, DSO, DSCLK Serial I/O and clock for background debug mode TPU Channels TP15 - TP0 TPU channel input/output Serial I/O and clock for background debug mode TPU Clock In T2CLK External clock source to the TPU SCI Receive Data RXD Serial input to the SCI SCI Transmit Data TXD Serial output from the SCI Peripheral Chip Select PCS3 - PCS0 QSPI peripheral chip selects Slave Select SS Places the QSPI in slave mode QSPI Serial Clock SCK Furnishes the clock from the QSPI in master mode or to the QSPI in slave mode Master-in Slave-out MISO Furnishes serial input to the QSPI in master mode, and serial output from the QSPI in slave mode Master-out Slave-in MOSI Furnishes serial output from the QSPI in master mode, and serial input to the QSPI in slave mode Standby RAM VSTBY Power supply for RAM Synchronizer Power VDDSYN Power supply to VCO System Power Supply and Return VDD, VSS Power supply and return to the MCU 7 2118A–HIREL–11/05 3. Scope This drawing describes the specific requirements for the microcontroller 68332 at 16.78 MHz and 20.97 MHz, in compliance either with MIL-STD-883 class B or Atmel-Grenoble standard. 4. Applicable Documents 4.1 MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics. 2. MIL-I-38535: general specifications for microcircuits. 3. DSCC Drawing: 5962-91501. 5. Requirements 5.1 General The microcircuits are in accordance with the applicable document and as specified herein. 5.2 Design And Construction 5.2.1 Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2-2 on page 4 and Figure 2-3 on page 5. 5.2.2 Lead Material and Finish Lead material and finish shall be any option of MIL-STD-853. 5.2.3 Package The macrocircuits are packaged in hermetically sealed ceramic packages which conform to case outlines of MIL-M-38510 appendix C (when defined): • 132-PIN SQ.PGA UP PAE outline • 132-PIN Ceramic CERQUAD 5.3 Electrical Characteristics The following ratings define the conditions under which the device operates without damage. Sections of the device may not operate normally while being exposed to the electrical extremes and contains circuitry to protect against damage from high static voltages or electrical fields. It is advised, however, that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage (i.e., either VSS or VDD). 8 TS68332 2118A–HIREL–11/05 TS68332 Table 5-1. Absolute Maximum Ratings Symbol Parameter VDD VI Min Max Unit Supply Voltage -0.3 +7.0 V Input Voltage -0.3 +7.0 V Low Power Operation 600 mW Stand By Mode 500 mW PDMAX Max Power Dissipation Tcase Operating Temperature Tstg Storage Temperature Tleads Lead Temperature Table 5-2. M Suffix -55 +125 °C V Suffix -40 +85 °C -55 +150 °C +270 °C Max 5 Sec. Soldering Thermal Characteristics (at 25°C) Package PGA 132 CERQUAD 132 5.3.1 Test Conditions Symbol Parameter θJ-A Thermal Resistance Ceramic Junction-to-ambient θJ-C Thermal Resistance Ceramic Junction-to-case θJ-A Thermal Resistance Ceramic Junction-to-ambient θJ-C Thermal Resistance Ceramic Junction-to-case Value Unit TBD °C/W 10 °C/W TBD °C/W 10 °C/W Power Considerations The average chip-junction temperature, TJ, in °C can be obtained from: TJ = TA + (PD ⋅ θJA) (1) TA = Ambient Temperature, °C θ JA = Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT + PI/O PINT = ICC ⋅ VCC, Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output Pins - User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273) (2) Solving equations (1) and (2) for K gives: K = PD ⋅ (TA + 273) + θ JA ⋅ PD2 (3) where K is a constant pertaining to the particular part K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (θ JA) can be separated into two components, θ JC and θ CA, representing the barrier to heat flow from the semiconductor junction to the package (case), surface (θ JC) and from the case to the outside ambient (θCA). 9 2118A–HIREL–11/05 These terms are related by the equation: θ JA = θ JC + θ CA (4) θ JC is device related and cannot be influenced by the user. However, θ CA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce θ CA so that θ JA approximately equals θ JC. Substitution of θJC for θ JA in equation (1) will result in a lower semiconductor junction temperature. 5.4 Mechanical and Environment The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or screened according to Atmel-Grenoble standards devices. 5.5 Marking The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and permanently marked with the following information as minimum: • Atmel logo • Manufacturer’s part number • Class B identification • Date-code of inspection lot • ESD identifier if available • Country of manufacturing 6. Quality Conformance Inspection 6.1 DESC/MIL-STD-883 Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot. Group C and D inspection are performed on a periodical basis. 7. Electrical Characteristics 7.1 General Requirements All static and dynamic electrical characteristics specified and the relevant measurement conditions are given below. For inspection purpose, refer to relevant specification: • DSCC (last issue on request to our marketing services) Table 7-1 on page 11 Static electrical characteristics for all electrical variants. Table 7-3 on page 14 Dynamic electrical characteristics for 6832-16 (16.78 MHz). For static characteristics, test methods refer to IEC 748-2 method number, where existing. For dynamic characteristics, test methods refer to clause 5.4 hereafter of this specification. 10 TS68332 2118A–HIREL–11/05 TS68332 7.2 Static Characteristics Table 7-1. DC Characteristics. VDD and VDDSYN = 5.0VDC ± 10% for 16.78 MHz and 5.0VDC ± 5% for 20.97 MHz; VSS = 0VDC; TC = -55°C to +125°C or -40°C to +85°C 16.78 MHz Number Symbol 1 VIH 2 3 4 5 6 7 8 9 Min Max Min Max Unit Input High Voltage 0.7 (VDD) VDD+0.3 0.7(VDD) VDD+0.3 V VIL Input Low Voltage VSS - 0.3 0.2(VDD) VSS - 0.3 0.2(VDD) V VHYS Input Hysteresis(1) 0.5 - 0.5 - V Input-only pins - 2.5 2.5 - 2.5 2.5 µA All input/output and output pins - 2.5 2.5 - 2.5 2.5 µA Group 1, 2, 4 input/output and all output pins and all output pins VDD - 0.2 - VDD - 0.2 - V Group 1, 2, 4 input/output and all output pins - 0.2 - 0.2 V Group 1, 2, 4 input/output and all output pins VDD - 0.8 - VDD - 0.8 - V Group 1 I/O pins CLKOUT, FREEZE/QUOT, IPIPE Group 2, 4 I/O pins, CSBOOT, BG/CS Group 3 - 0.4 - 0.4 V - 0.4 - 0.4 V - 0.4 - 0.4 V 1.6(VDD) 9.1 1.6(VDD) 9.1 V -15 -120 - - 15 -120 - µA µA - 124 134 350 5 - 140 150 350 5 mA mA µA mA IIN IOZ VOH VOL VOH VOL Parameter 20.97 MHz (2) Input Leakage Current VIN = VDD or VSS High Impedance (off-state) Leakage Current (2) VIN = VDD or VSS L CMOS Output High Voltage(2)(3) IOH = -10.0 µA CMOS Output High Voltage(2) IOH = -10.0 µA Output High Voltage(2)(3) IOH = -0.8 mA Output Low Voltage(2) IOL = 1.6 mA IOL = 5.3 mA IOL = 12 mA 10 VIHTSC 11 IMSP 12 IDD IDD SIDD SIDD Three State Control Input High Voltage Data Bus Mode Select Pullup Current(5) VIN = VIL VIN = VIH DATA [15:0] DATA [15:0] VDD supply current(5) RUN(6) RUN, TPU emulation mode LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0) LPSTOP (external clock input frequency = maximum fsys) 11 2118A–HIREL–11/05 Table 7-1. DC Characteristics. VDD and VDDSYN = 5.0VDC ± 10% for 16.78 MHz and 5.0VDC ± 5% for 20.97 MHz; VSS = 0VDC; TC = -55°C to +125°C or -40°C to +85°C (Continued) 16.78 MHz Number Symbol Parameter 13 VDDSYN Clock synthesizer operating voltage IDDSYN IDDSYN SIDDSYN IDDSYN 16 Min Max Min Max Unit 4.5 5.5 4.75 5.25 V - 1 5 150 100 - 2 6 150 100 mA mA µA µA 0.0 3.0 5.5 5.5 0.0 3.0 5.25 5.25 V V - 10 3 - 10 3 µA mA - 60 - 50 µA - 690 - 766 mW All input-only pins All input/output pins - 10 20 - 10 20 pF pF Load capacitance(2) Group 1 I/O pins CLKOUT, FREEZE/QUOT, IPIPE Group 2 I/O pins and CSBOOT, BG/CS Group 3 I/O pins Group 4 I/O pins - 90 100 130 200 - 90 100 130 200 pF pF pF pF (5) 14 15 VSB ISB VDDSYN supply current 32.768 kHz crystal, VCO on, maximum fsys External clock, maximum fsys LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0) 32.768 kHz crystal, VDD powered down RAM standby voltage(7) Specified VDD applied VDD = VSS RAM standby current (5)(7)(8) Normal RAM operation Transient condition Standby operation 17 18 19 Notes: 20.97 MHz PD Cin CL VDD > VSB - 0.5V VSB - 0.5 ≥ VDD ≥ VSS + 0.5V VDD < VSS + 0.5V (9) Power dissipation (2)(10) Input capacitance 1. Applies to: Port E [7:4] - SIZ [1:0],AS, DS. Port F [7:0] -IRQ [7:1], MODCLK. Port QS [7:0] - TXD, PCS [3:1], PCS0/SS, SCK, MOSI, MISO. TRUCH [15:0], T2CLK. BKPT/DSCLK, IFETCH, RESET, RXD, TSSTME/TSC. EXTAL (when PLL enabled). 2. Input- only pins: EXTAL, TSTME/TSC, BKPT T2CLK, RXD. Output-only pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, I PIPE. Input/output pins: Group 1: DATA [15:0], IFETCH, TPUCH [15:01]. Group 2: Port C [6:0] - ADDR [22:19]/CS [9:6], FC[2:0]/CS [5:3]. Port E: [7:0] - SIZ [1:0], AS, DS, AVEC, RMC, DSACK [1:0] Port F [&:0] - IRQ [7:1], MODCLK. Port QS [7:3] - TXD, PCS [3:1], PCS0/SS. ADDR23/CS10/ECLK, ADDR [18:0], R/W, BERR, BR/CSO, BGACK/CS2. Group 3: HALT, RESET. Group 4: MISO, MOSI, SCK. 3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS [7:0], (TXD, PCS [3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 4. Use of an active pull-down device is recommended. 12 TS68332 2118A–HIREL–11/05 TS68332 5. Total operating current is the sum of the appropriate IDD, IDDSYN, and ISB values. IDD values. IDD values include supply currents for device modules powered by VDDE and VDDI pins 6. Current measured with system clock frequency of 16.78 MHz, all modules active. 7. The RAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5-volt. The RAM array cannot be accessed while the module is in standby mode. 8. When VDD is transitioning during power-up or power-down sequence, and VSB is applied, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum transient condition specification. System noise on the VDD and VSTBY pins can contribute to this condition. 9. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can be calculated using the expression: PD = Maximum VDD (IDD + IDDSYN + ISB) IDD includes supply currents for all device modules powered by VDDE and VDDI pins. 10. This parameter is periodically sampled rather than 100% tested. 7.3 Dynamic (Switching) Characteristics The INTERVAL numbers refer to the timing diagram. Table 7-2. Clock Control Timing. VDD and VDDSYN = 5.0 VDC ± 10% for 16.78 MHz and 5.0 VDC ± 5% for 20.97 MHz; VSS = 0 VDC; TC = -55°C to +125°C or -40°C to +85°C 16.78 Number Symbol 1 fref 2 Min Max Min Max Unit PLL reference frequency range 25 50 25 50 kHz fsys System frequency(1) On-chip PLL system frequency External clock operation dc 0.131 dc 16.78 16.78 16.78 dc 0.131 dc 20.97 20.97 20.97 MHz MHz MHz 3 flpll PLL lock time(2)(3)(4)(5) - 20 - 20 ms 4 fvco VCO frequency(6) - 2 (fsys max) - 2 (fsys max) MHz 5 fLIMP Limp mode clock frequency SYNCR X bit = 0 SYNCR X bit = 1 - fsys max/2 fsys max - fsys max/2 fsys max MHz MHz CLKOUT stability(2)(3)(4)(7) Short term (5 µs interval) Long term (500 µs interval) -05 -0.05 05 0.05 -05 -0.05 05 0.05 % % 6 Notes: Cstab Parameter 20.97 1. All internal registers retain data at 0 Hz. 2. This parameter is periodically sampled rather than 100% tested. 3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total external resistance from XFC pin due to external leakage must be greater than 15 MΩ to guarantee this specification. Filter network geometry can vary depending upon operating environment. 4. Proper layout procedures must be followed to achieve specifications. 5. Assumes that stable VDDSYN is applied, and that the crystal oscillator is stable. Lock time is measured from the time VDD and VDDSYN are valid until RESET is released. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP. 6. Internal VCO frequency (fVCO) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and fsys = fVCO: 4. When X = 1, the divider is disabled, and fsys = fVCO: 2. X must equal one when operating at maximum specified fsys. 13 2118A–HIREL–11/05 7. Stability is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator frequency increase the Cstab percentage for a given interval. When clock stability is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system. . Table 7-3. AC Timing. VDD and VDDSYN = 5.0 VDC ± 10% for 16.78 MHz and 5.0 VDC ± 5% for 20.97 MHz; VSS = 0 VDC; TC = -55°C to +125°C or -40°C to +85°C (1) 16.78 MHz Number Symbol Parameter 20.97 MHz Min Max Min Max Unit Frequency of operation (32.768 kHz crystal) 0.13 16.78 0.13 20.97 MHz 59.6 - 47.7 - ns 476 - 381 - ns 59.6 - 47.7 - ns (2) F1 f 1 tCYC Clock period 1A tEcyc ECLK period (3) 1B tXcyc External clock input period 2, 3 tCW Clock pulse width 24 - 18.8 - ns 2A, 3A tECW ECLK pulse width 236 - 183 - ns 2B, 3B tXCHL External clock input high/low time(3) 29.8 - 23.8 - ns 4, 5 tCrf Clock rise and fall time - 5 - 5 ns 4A, 5A trt Rise and fall time - All outputs except CLKOUT - 8 - 8 ns - 5 - 5 ns (4) 4B, 5B TXCrf External clock rise and fall time 6 tCHAV Clock high to address, FC, SIZE, RMC valid 0 29 0 23 ns 7 tCHAZx Clock high to address, Data, FC, SIZE, RMC high impedance 0 59 0 47 ns 8 tCHAZn Clock high to address, FC, SIZE, RMC invalid 0 - 0 - ns 9 tCLSA Clock low to AS, DS, CS, asserted 2 25 0 23 ns -15 15 -10 10 ns 14 (5) 9A tSTSA AS to DS or CS, asserted (read) 9C tCLIA Clock low to IFETCH, IPIPE asserted 2 22 2 22 ns 11 tAVSA Address, FC, SIZE, RMC valid to AS, CS (and DS read) asserted 15 - 10 - ns 12 tCLSN Clock low to AS, DS, CS negated 2 29 2 23 ns 12A tCLIN Clock low to IFETCH, IPIPE negated 2 22 2 22 ns 13 tSNAI AS, DS, CS negated to address, FC, SIZE invalid (address hold) 15 - 10 - ns 14 tSWA AS, CS (and DS read) width asserted 100 - 80 - ns 14A tSWAW DS, CS, width asserted (write) 45 - 36 - ns 14B tSWDW AS, CS (and DS read) width asserted (fast write cycle) 40 - 32 - ns 15 tSN AS, DS, CS width negated(6) 40 - 32 - ns 16 tCHSZ Clock high to AS, DS, R/W high impedance - 59 - 47 ns 17 tSNRN AS, DS, CS negated to R/W negated 15 - 10 - ns 18 tCHRH Clock high to R/W high 0 29 0 23 ns TS68332 2118A–HIREL–11/05 TS68332 Table 7-3. AC Timing. VDD and VDDSYN = 5.0 VDC ± 10% for 16.78 MHz and 5.0 VDC ± 5% for 20.97 MHz; VSS = 0 VDC; TC = -55°C to +125°C or -40°C to +85°C (Continued)(1) 16.78 MHz Number Symbol 20 tCHRL 21 Min Max Min Max Unit Clock high to R/W low 0 29 0 23 ns tRAAA R/W asserted to AS, CS asserted 15 - 10 - ns 22 tRASA R/W low to DS, CS asserted (write) 70 - 54 - ns 23 tCHDO Clock high to data out valid - 29 - 23 ns 24 tDVASN Data out valid to negating edge of AS, CS (fast write cycle) 15 - 10 - ns 25 tSNDOI DS, CS negated to data out invalid (data out hold) 15 - 10 - ns 26 tDVSA Data out valid to DS, CS asserted (write) 15 - 10 - ns 27 tDICL Data in valid to clock low (data setup) 5 - 5 - ns 27A tBELCL Late BERR, HALT asserted to clock low (setup time) 20 - 15 - ns 28 tSNDN AS, DS negated to DSACK [1:0], BERR, HALT, AVEC negated 0 80 0 60 ns 29 tSNDI DS, CS negated to data in invalid (data in hold)(7) 0 - 0 29A tSHDI DS, CS negated to date in high impedance(7)(8) - 55 - 48 ns 30 tCLDI CLKOUT low to data in invalid (fast cycle hold)(7) 15 - 10 - ns - 90 - 72 ns - 50 - 46 ns - 29 - 23 ns 30A Parameter 20.97 MHz tCLDH CLKOUT low to data in high impedance 31 tDADI (9) 33 tCLBAN DSACK [1:0] asserted to data in valid (7) Clock low to BG asserted/negated (10) ns 35 tBRAGA BR asserted to BG asserted (RMC not asserted) 1 - 1 - tCYC 37 tGAGN BGACK asserted to BG negated 1 2 1 2 tCYC 39 tGH BG width negated 2 - 2 - tCYC 39A tGA BG width asserted 1 - 1 - tCYC 46 tRWA R/W width asserted (write or read) 150 - 115 - ns 46A tRWAS R/W width asserted (fast write or read cycle) 90 - 70 - ns 47A tAIST Asynchronous input setup time BR, BGACK, DSACK [1:0], BERR, AVEC, HALT 5 - 5 - ns 47B tAIHT Asynchronous input hold time 15 - 12 - ns 48 tDABA DSACK [1:0], asserted to BERR, HALT asserted(11) - 30 - 30 ns 53 tDOCH Data out hold from clock high 0 - 0 - ns 54 tCHDH Clock high to data out high impedance - 28 - 23 ns 55 tRADC R/W asserted to data bus impedance change 40 - 32 - ns 56 tHRPW RESET pulse width (reset instruction) 512 - 512 - tCYC 57 tBNHN BERR negated to HALT negated (rerun) 0 - 0 - ns 70 tSCLDD Clock low to data bus driven (show) 0 29 0 23 ns 71 tSCLDS Data setup time to clock low (show) 15 - 10 - ns 15 2118A–HIREL–11/05 Table 7-3. AC Timing. VDD and VDDSYN = 5.0 VDC ± 10% for 16.78 MHz and 5.0 VDC ± 5% for 20.97 MHz; VSS = 0 VDC; TC = -55°C to +125°C or -40°C to +85°C (Continued)(1) 16.78 MHz Number Symbol 72 tSCLDH 73 Parameter 20.97 MHz Min Max Min Max Unit Data hold from clock low (show) 10 - 10 - ns tBKST BKPT input setup time 15 - 10 - ns 74 tBKHT BKPT input hold time 10 - 10 - ns 75 tMSS Mode select setup time 20 - 20 - tCYC 76 tMSH Mode select hold time 0 - 0 - ns (12) 77 tRSTA RESET assertion time 4 - 4 - tCYC 78 tRSTR RESET rise time(13)(14) - 10 - 10 tCYC Notes: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. Minimum system clock frequency is four times the crystal frequency, subject to specified limits. 3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock signal varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL/(50% - external input duty cycle tolerance) 4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are at critical. 5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. 6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles. 7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time. 8. Maximum value is equal to (tcyc/2) + 25 ns. 9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK [1:0] low to data setup time (specification 31) and DSACK [1:0] low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle. 10. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated. 11. In the absence of DSACK [1:0], BERR is an asynchronous input using the asynchronous setup time (specification 47A). 12. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the SIM drives RESET low for 512 tcyc. 13. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles. 14. External logic must pull RESET high during this period in order for normal MCU operation to begin. 15. Address access time = (2.5 + WS) tcyc - tCHAV - tDICL. Chip select access time = (2 + WS) tcyc - tCLSA - tDICL. Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = - 1. 16 TS68332 2118A–HIREL–11/05 TS68332 7.4 7.4.1 Test Conditions Specific to the Device Time Definitions The times specified in Table 7-3 on page 14 as dynamic characteristics are defined in Figure 71 to Figure 7-12 on page 24 below, by a reference number given the column “NUM” of the tables together with the relevant figure number. Figure 7-1. Note: Timing shown with respect to 20% and 70% VDD. Figure 7-2. Note: External Input Timing Diagram Timing shown with respect to 20% and 70% VDD. Pulse width shown with respect to 50% VDD. Figure 7-3. Note: Clkout Output Timing Diagram ECLK Output Timing Diagram Timing Shown With Respect To 20% and 7% VDD. 17 2118A–HIREL–11/05 Figure 7-4. 18 Read Cycle Timing Diagram TS68332 2118A–HIREL–11/05 TS68332 Figure 7-5. Write Cycle Timing Diagram 19 2118A–HIREL–11/05 Figure 7-6. 20 Fast Termination Read Cycle Timing Diagram TS68332 2118A–HIREL–11/05 TS68332 Figure 7-7. Fast Termination Write Cycle Timing Diagram 21 2118A–HIREL–11/05 Figure 7-8. 22 Bus Arbitration Timing Diagram – Active Bus Case TS68332 2118A–HIREL–11/05 TS68332 Figure 7-9. Bus Arbitration Timing Diagram – Idle Bus Case Figure 7-10. Show Cycle Timing Diagram Note: Show cycles can stretch during S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion. 23 2118A–HIREL–11/05 Figure 7-11. Chip Select Timing Diagram Note: AS and DS timing shown for reference only. Figure 7-12. Reset and Mode Select Timing Diagram 24 TS68332 2118A–HIREL–11/05 TS68332 8. Functional Description 8.1 Module Memory Map The RAM array is positioned by the base address register in the RAM CTRL block. Reset forces the RAM array to be disabled. Unimplemented blocks are mapped externally. Figure 8-1. Note: 8.2 Module Memory Map Y - M111, where M is the modmap signal state on the IMB which reflects the state of the modmap bit in the module configuration register of the system integration module (Y = $7 or $F). CPU32 Overview The CPU32, the instruction processing module of the 68300 family, is based on the industrystandard TS68000 core processor with many features of the 68010 and TS68020 as well as unique features suited for high-performance controller applications. The CPU32 is designed to provide a significant increase in performance over existing microcontroller CPUs to meet the demand for higher performance requirements for the 1990s, while maintaining source code and binary code compatibility with the 68000 family. Ease of programming is an important consideration in using a microcontroller. An instruction format implementing a register-memory interaction philosophy predominates in the design, and all data resources are available to all operations requiring those resources. All capabilities and functions of this module are detailed fully in the CPU32 reference manual. 25 2118A–HIREL–11/05 8.2.1 Block Diagram The major clocks depicted operate in a highly independent fashion that maximizes concurrency of operation while managing the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and control unit provide overall chip control, managing the internal buses, registers, and functions of the execution unit. 8.2.2 Architecture Summary The CPU32 architecture includes several important features that provide both power and versatility to the user. The CPU32 is source and object code compatible with the TS68000 and 68010. All user-state programs can be executed unchanged. The major CPU32 features are as follows: • 32-bit internal data path and arithmetic hardware • 32-bit internal address bus, 24-bit external address bus • eight 32-bit general-purpose data registers • seven 32-bit general-purpose address registers • separate user and supervisor stack pointers and address spaces • separate program and data address spaces • full interrupt processing • fully upward object code compatible with 68000 family • virtual memory implementation, loop mode of instruction execution • fast multiply, divide, and shift instructions • fast bus interface with dynamic bus port sizing • improved execution handling for controller applications • enhanced addressing modes: – scaled index – address register indirect with base displacement and index – expanded PC relative modes 32-bit branch displacements breakpoint instruction. • instruction set enhancements: – high precision multiply and divide – trap on condition codes – upper and lower bounds checking – enhanced breakpoint instruction • trace on change of flow • table lookup and interpolate instruction • low power stop instruction • hardware breakpoint signal, background mode • 16.78 MHz and 20.97 MHz operating frequency at -55°C to +125°C • fully static implementation 26 TS68332 2118A–HIREL–11/05 TS68332 Figure 8-2. 8.2.3 CPU32 Block Diagram Programmer’s Model The programming model of the CPU32 consists of two groups of registers: user model and supervisor model, which correspond to the user and supervisor privilege levels. Executing at the user privilege level, user programs can only use the registers of the user model. Executing at the supervisor level, system software uses the control registers of the supervisor level to perform supervisor functions. The supervisor level has higher privileges than the user level. Not all instructions are permitted to execute in the lower privileged user level, but all instructions are available at the supervisor level. This scheme allows a separation of supervisor and user levels, and so the supervisor can protect system resources from uncontrolled access. The processor uses the privilege level indicated by the S bit in the status register to select either the user or supervisor privilege level and either the USP or SSP for stack operations. The user programming model remains unchanged from previous 68000 family microprocessors. The supervisor programming model, which supplements the user programming model is used exclusively by the CPU32 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions. The supervisor programming model contains all the controls to access and enable the special features of the CPU32. All application software, written to run at the non privileged user level, migrates to the CPU32 from any 68000 platform without modification. The programming models are shown in Figure 8-3 on page 28 and Figure 8-4 on page 29. 27 2118A–HIREL–11/05 8.2.4 Registers Registers D7-D0 are used as data registers and readily support 8-bit (byte), 16-bit (word) and 32-bit (long word) operand lengths for all operations. Registers A6-A0 and the user and supervisor stack pointers are address registers that may be used as software stack pointers of base address registers. Register A7 is a register that applies to the user stack pointer in the user privilege level and to the supervisor stack pointer in the user privilege level. In addition, the address registers may be used for word and long-word operations. All of the 16 general-purpose registers (D7-D0, A7-A0) may be used as index registers. The PC contains the address of the next instruction to be executed by the CPU32. The status register (SR) stores the processor status. It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The vector base register (VBR) contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. Alternate function code registers (SFC and DFC) contain 3-bit function codes. Function codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces. These address spaces are designated as either user or supervisor space and as either program or data space. There is a CPU space to allow the CPU to acquire specific control information not usually associated with read or write bus cycles. The function code signals FC2-FC0 select the appropriate address space. Figure 8-3. 28 User Programming Model TS68332 2118A–HIREL–11/05 TS68332 Figure 8-4. 8.2.5 Supervisor Programming Model Supplement Data Types Six basic data types are supported: • bits • packaged binary-coded decimal digits • byte integers (8 bits) • word integers (16 bits) • long-word integers (32 bits) • quad-word integers (64 bits) 8.2.5.1 8.2.6 Organization In Registers The eight data registers can store data operands of 1, 8, 16, 32 and 64 bits and addresses of 16 or 32 bits. The seven address registers and the two stack pointers are used for address operands of 16 or 32 bits. The PC is 32 bits wide. System Features The CPU32 includes a number of features to aid system implementation. These include a privilege mechanism, separation of address spaces, multilevel priority interrupts, trap instructions, and a trace facility. The privilege mechanism provides user and supervisor privilege states, privileged instructions, and external distinction of user and supervisor state references. The processor separates references between program and data space. This permits sharing of code segments that access separate data segments. The CPU32 supports seven priority levels for 199 memory vectored interrupts. For each interrupt, the vector location can be provided externally or generated internally. The seventh level provides a non-maskable interrupt capability. To simplify system development, instructions are provided to check internal processor conditions and allow software traps. The trace facility allows instruction-by-instruction tracing of program execution without alteration of the program or special hardware. 8.2.7 Virtual Memory The full addressing range of the CPU32 on the TS68332 is 16-Mbyte in each of eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16-Mbyte of memory available to each user program by using virtual memory techniques. 29 2118A–HIREL–11/05 8.2.8 Loop Mode Instruction Execution The CPU32 has several features that provide efficient execution of program loops. One of these features is the DBcc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by a single word instruction that does not change program flow. Loop mode is implemented in conjunction with the DBcc instruction. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. 8.2.9 Vector Base Register The VBR contains the base address of the 1024-byte exception vector table, consisting of 256 exception vectors. Exception vectors contain memory addresses of routines that begin execution at the completion of exception processing, i.e. an interrupt routine. 8.2.10 Processing States The processor is always in one of four processing states: normal, exception, halted or background. The normal processing state is that associated with instruction execution; the bus is used to fetch instructions and operands and to store results. The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, a bus error, or a reset. The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. The background processing state is initiated by breakpoints, execution of special instructions, or a double bus fault. Background processing allows interactive debugging of the system via a simple serial interface. 8.2.11 Addressing Modes Addressing in the CPU32 is register-oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory. The seven basic addressing modes are as follows: • register direct • register indirect • register indirect with index • program counter indirect with displacement • program counter indirect with index • absolute • immediate Included in the register indirect addressing modes are the capabilities to post-increment, predecrement, and offset. The program counter relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the status register, stack pointer, and/or program counter. 30 TS68332 2118A–HIREL–11/05 TS68332 8.2.12 8.2.12.1 Instructions 68000 Family Compatibility It is the philosophy of the 68000 family that all user-code programs can execute unchanged on a more advanced processor, and supervisor-mode programs and exception handlers should require only minimal alteration. The CPU32 can be thought of as an intermediate member of the 68000 family. Object code from an TS68000 or 68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the TS68020 are also supported. Refer to the CPU32 reference manual for a detailed comparison of the CPU32 and TS68020 instruction set (see also Table 81 on page 32). 8.2.12.2 New Instructions Two new instructions have been added to the TS68000 instruction set for use in controller applications. They are low power stop (LPSTOP) and table lookup and interpolate (TBL). Low Power Stop (LPSTOP): In applications where power consumption is a consideration, the CPU32 forces the device into a low-power standby mode when immediate processing is not required. The low-power stop mode is entered by executing the LPSTOP instruction. The processor will remain in this mode until a user-specification (or higher) interrupt level or reset occurs. Table Lookup and Interpolate (TBL): To maximize throughput for real-time applications, reference data is often “pre-calculated” and stored in memory for quick access. The storage of each data point would require an inordinate amount of memory. The table instruction requires only a sample of data points stored in the array, reducing memory requirements. This single instruction allows intermediate values to be recovered by linear interpolation, thus significantly increasing CPU throughput compared with earlier interpolation methods which used several instructions. The results are optionally rounded with the round-to-nearest algorithm. 8.2.13 Development Support The following features have been implemented on the CPU32 to enhance the instrumentation and development environment: • 68000 family development support • background debug mode • deterministic opcode tracking • hardware breakpoints 8.2.13.1 68000 Family Development Support All 68000 family members include features to facilitate applications development. These features include the following: Trace On Instruction: 68000 family processors include an instruction-by-instruction tracing facility as an aid to program development. The CPU32 also allows the user to trace only those instructions causing a change in program flow. Breakpoint Instruction: An emulator may insert software breakpoints into the target code to indicate when a breakpoint has occurred. On the CPU32, this function is provided via illegal instructions, $4848-$484F, to serve as breakpoint instructions. 31 2118A–HIREL–11/05 Unimplemented Instruction Emulation: During instruction execution, when an attempt is made to execute an illegal instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, A-line,...) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software. 8.2.13.2 Background Debug Mode Microcomputer systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The background debug mode in the CPU32 is unique in that the debugger has been implemented in CPU microcode. Registers can be viewed and/or altered, memory can be read or written to, and test features can be invoked. Incorporating these capabilities on-chip simplifies the environment in which the in-circuit emulator operates. 8.2.13.3 Deterministic Opcode Tracking CPU 32 function code outputs are augmented by two supplementary signals to monitor the instruction pipeline. The instruction pipe (PIPE) output indicates the start of each new instruction and each mid-instruction pipeline advance. The instruction fetch (FETCH) output identifies the bus cycles in which the operand is loaded into the instruction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these two signals allows a bus analyzer to synchronize itself to the instruction stream and monitor its activity. 8.2.13.4 On-chip Breakpoint Hardware An external breakpoint trap on any memory access. . Table 8-1. 32 Instruction Set Summary Mnemonic Description ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Add Decimal with Extend Add Add Address Add Immediate Add Quick Add with Extend Logical AND Logical AND Immediate Arithmetic Shift Left and Right Bcc BCHG BCLR BGND BKPT BRA BSET BSR BTST Branch Conditionally Test Bit and Change Test Bit and Clear Background Breakpoint Branch Test Bit and Set Branch to Subroutine Test Bit TS68332 2118A–HIREL–11/05 TS68332 Table 8-1. Instruction Set Summary (Continued) Mnemonic Description CHK, CHK2 CLR CMP CMPA CMPI CMPM CMP2 Check Register Against Upper and Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory to Memory Compare Register Against Upper and Lower Bounds DBcc DIVS, DIVSL DIVU, DIVUL Test Condition, Decrement and Branch Signed Divide Unsigned Divide EOR EORI EXG EXT, EXTB Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend ILLEGAL Take Illegal Instruction Trap JMP JSR Jump Jump to Subroutine LEA LINK LPSTOP LSL, LSR Load Effective Address Link and Allocate Low Power Stop Logical Shift Left and Right MOVE MOVE CCR MOVE SR MOVE USP MOVEA MOVEC MOVEM MOVEP MOVEQ MOVES MULS, MULS.L MULU, MULU.L Move Move Condition Code Register Move Status Register Move User Stack Pointer Move Address Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply NBCD NEG NEGX NOP Negate Decimal with Extend Negate Negate with Extend No Operation OR ORI Logical Inclusive OR Logical Inclusive OR Immediate PEA Push Effective Address 33 2118A–HIREL–11/05 Table 8-1. 8.3 Instruction Set Summary (Continued) Mnemonic Description RESET ROL, ROR ROXL, ROXR RTD RTE RTR RTS Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and De-allocate Return from Exception Return and Restore Codes Return from Subroutine SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words TBLS, TBLSN TBLU, TBLUN TAS TRAP TRAPcc TRAPV TST Signed/Unsigned Table Lookup and Interpolate Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand UNLK Unlink Bus Operation This section provides a functional description of the bus and the signals that control it. Operation of the bus is the same whether the MCU or an external device is the bus master; the names and description of bus cycles are from the point of view of the bus master. The MCU architecture supports byte, word, and long-word operands, allowing access to 8-bit and 16-bit data ports through use of asynchronous cycles controlled by the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). 8.3.1 Function Codes The function code signals (FC2 - FC0) select one of eight 16-Mbyte address space to which the address applies. 8.3.2 Address Bus The address bus signals (A23 - A0) define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The address is valid while AS asserted. 8.3.3 34 Address Strobe The Address Strobe (AS) is a timing signal that indicates the validity of an address on the address bus and of many control signals. TS68332 2118A–HIREL–11/05 TS68332 8.3.4 Data Bus The data signals (D15 - D0) comprise a bi-directional, non-multiplexed parallel bus that contains the data being transferred to or from the MCU. A read or write operation may transfer 8 or 16 bits of data (1 or 2 bytes) in one bus cycle. 8.3.5 Data Strobe The Data Strobe (DS) is a timing signal that applies to the data bus. For a read cycle, the MCU asserts DS to signal the external device to place data on the bus. For a write cycle, DS signals to the external devices that the data to be written is valid on the bus. 8.3.6 Bus Control Signals The MCU initiates a bus cycle by driving the address, size, function, code, and read/write outputs. At the beginning of a bus cycle, the size signals (SIZ1, SIZ0) are driven along with the function code signals. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). Table 8-2 shows the encoding of SIZ1 and SIZ0. The read/write (R/W) signal determines the direction of the transfer during a bus cycle. The read-modify-write cycle signal (RMC) is asserted at the beginning of the first bus cycle of a read-modify-write operation, and remains asserted until completion of the final bus cycle of the operation. Table 8-2. 8.3.7 Size Signal Encoding SIZ1 SIZ2 Transfer Size 0 1 Byte 1 0 Word 1 1 3 Byte 0 0 Long Word Bus Cycle Termination Signals During bus cycles, external devices assert the data transfer and size acknowledge signals DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MCU to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the MCU the size of the port for the bus cycle just completed. The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence of DSACKx to indicate a bus error condition. It can also be asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the appropriate timing. Additionally, the BERR and HALT signals can be asserted simultaneously, in lieu of, or in conjunction with, the DSACKx signals. The internal bus monitor can be used to generate the BERR signal for internal and internal-toexternal transfers. An external bus master must provide its own BERR generation and drive the BERR pin, since the internal BERR monitor has no information about transfers initiated by an external bus master. Finally, the autovector (AVEC) signal can be used to terminate interrupt acknowledge cycles, indicating that the MCU should internally generate a vector number to locate an interrupt handler routine. AVEC is ignored during all other bus cycles. 35 2118A–HIREL–11/05 8.3.8 Dynamic Bus Sizing The MCU dynamically interrupts the port size of the addressed device during each bus signal, allowing operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MCU through the use of the DSACKx encodings and assertion results. Refer to Table 8-3 for DSACKx encodings and assertion results. For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. Dynamic bus sizing requires that the portion of the data bus for a transfer to or from a particular port size be fixed. For example an 8-bit port must reside on data bus bits 15 - 8. The SIZx signals also form part of the bus sizing protocol. These outputs indicate the remaining number or bytes to be transferred during the current bus cycle. Table 8-3. 8.3.9 DSACK Codes and Results DSACK1 DSACK0 Result 1 (Negated) 1 (Negated) Insert wait states in current bus cycle 1 (Negated) 0 (Asserted) Complete cycle – Data bus port size is 8-bit 0 (Asserted) 1 (Negated) Complete cycle – Data bus port size is 16-bit 0 (Asserted) 0 (Asserted) Reserved Bus Operation The MCU bus is used in an asynchronous manner. The external devices connected to the bus can operate at clock frequencies different from the clock for the MCU. Bus operation uses the handshake lines (AS, DS, DSACK1, DSACK0, BERR and HALT) to control data transfers. Decoding the size outputs and lower address line A0 provides strobes that select the active portion of the data bus. The slave device (memory or peripheral) then responds by placing the requested data on the correct portion of the data bus for a read cycle or latching the data on a write cycle, and asserting the DSACK1/DSACK0 combination that corresponds to the port size to end the cycle. If no slave responds or the access is invalid, external control logic asserts the BERR, or BERR and HALT) signal(s) to abort or retry the bus cycle, respectively. 8.3.10 Fast Termination Cycles With an external device that has a fast access time, the chip-select circuit fast-termination option can provide a two-cycle external bus transfer. Since the chip select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. 8.3.11 Bus Exception Control Cycles The bus architecture requires assertion of DSACKx from an external device to signal that a bus cycle is complete. DSACKx or AVEC is not asserted in these cases: • The external device does not respond • No interrupt vector is provided • Various other application-dependent errors occur 36 TS68332 2118A–HIREL–11/05 TS68332 This MCU has a bus error input (BERR) when no device responds by asserting DSACKx or within an appropriate period of time after the MCU asserts the AVEC. This allows the cycle to terminate and the MCU to enter exception processing for the error condition. Another signal that is used for bus exception control is the halt signal (HALT).This signal can be asserted by an external device for debugging purposes to cause single bus operation or (in combination with BERR) a retry of a bus cycle in error. 8.3.12 Bus Arbitration The bus design of the MCU provides for a single bus master at any one time: either the MCU or an external device. One or more of the external devices on the bus can have the capability of becoming bus master. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the MCU manages the bus arbitration signals so that the MCU has the lowest priority. External devices that need to obtain the bus must assert the bus arbitration signals in a certain sequence. Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes the bus master first. The protocol is explained fully in the SIM manual, however here is the basic sequence of events: • An external device asserts the bus request signal (BR). • The MCU asserts the bus grant signal to indicate that the bus is available (BG). • The external device asserts the bus grant acknowledge signal (BGACK) to indicate that it has assumed bus mastership. Bus arbitration requests are recognized during normal processing, HALT assertion, when the CPU has halted due to a double bus fault. 8.3.13 Reset Operation The MCU has reset control logic to determine the cause of reset and synchronize it if necessary. If an external device drives the RESET pin low, the reset control logic holds RESET asserted internally until the external RESET is released. When the reset control logic detects that the external RESET is no longer being driven, it drives RESET low for an additional 512 cycles to guarantee this length of reset to the entire system. If RESET is asserted from any other source, the reset control logic asserts RESET for a minimum of 512 cycles and until the source of reset is negated. Figure 8-5 on page 38 is a timing diagram of the power-up reset operation, showing the relationship between RESET, VDD, and bus signals. During the reset period, the entire bus (except for non-tri-statable signals, which are driven to their inactive state three-states. Once RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for RESET exception processing begins. RESET should be asserted for at least 590 clock periods to ensure that the MCU resets. Resetting the MCU causes any bus cycle in progress to terminate as if DSACKx or BERR has been asserted. In addition, the MCU initializes registers appropriately for a reset exception. For further information refer to the System Integration Module Manual. 37 2118A–HIREL–11/05 Figure 8-5. Notes: Initial Reset Operation Timing 1. Internal startup time 2. SSP read here 3. PC read here 4. First instruction fetched here 8.4 System Integration Module The TS68332 system integration module (SIM) consists of five sudmodules that control the microcontroller unit (MCU) system start-up, initialization, configuration, and external bus with a minimum of external devices. The fives submodules that make up the SIM, shown in Figure 8-6 on page 39, are as follows: • System configuration and protection • Clock synthesizer • Chip selects • External bus interface • System test 8.4.1 System Configuration and Protection Submodule The SIM module allows the user to control some features of system configuration by writing bits in the Module Configuration Register. This register also contains read-only status bits that show the state of some of the SIM features. This MCU is designed with the concept of providing maximum system safe-guards. Many of the functions that normally must be provided in external circuits are incorporated in this MCU. The features provided in the system configuration and protection submodule are as follows: 38 TS68332 2118A–HIREL–11/05 TS68332 8.4.1.1 System Configuration The module configuration register allows the user to configure the system according to the particular system requirements. 8.4.1.2 Internal Bus Monitor The MCU provides an internal bus monitor to monitor the DSACKx response time for all internal bus accesses. An option allows the monitoring of internal to external bus accesses. There are four selectable response times that allow for the response speed of peripherals used in the system. A bus error (BERR) signal is asserted internally if the DSACKx response time is exceeded. When operating as a bus master, the BERR signal is not asserted externally. Figure 8-6. 8.4.1.3 System Integration Module Block Diagram Halt Monitor A halt monitor causes a reset to occur if the internal halt (HALT) is asserted by the CPU. 8.4.1.4 Spurious Interrupt Monitor If no interrupt arbitration occurs during an interrupt acknowledge (IACK) cycle, the BERR signal is asserted internally. 8.4.1.5 Software Watchdog The watchdog asserts RESET if the software fails to service the software watchdog for a designated period of time (presumably because it is trapped in a loop or lost). There are four selectable time-out periods, and a prescaler may be used for long time-out periods. 8.4.1.6 Periodic Interrupt Timer The MCU provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 µs - 15.94 µs (with a 32.768 kHz crystal used to generate the system clock). 39 2118A–HIREL–11/05 Figure 8-7. Note: 8.4.2 Clock Submodule Block Diagram Must be low leakage capacitor. Clock Synthesizer The clock synthesizer (Figure 8-7) can operate from an on-chip phase locked loop (PLL) using an external crystal connected between the EXTAL and XTAL pins as a reference frequency source. A 32.768 kHz watch crystal provides an inexpensive reference, but the reference crystal frequency can be any frequency from 25 - 50 kHz. Outside the 25 - 50 kHz range, an external oscillator can be used with the on-chip synthesizer and VCO, or the frequency can be driven directly into the EXTAL pin (the XTAL pin should be left floating for this case). The system clock frequency is programmable from 131 kHz to the maximum clock frequency with a resolution of 131 kHz. A separate power pin (VDDSYN) is used to allow the clock circuits to run with the rest of the MCU powered down and to provide increased noise immunity for the clock circuits. If for some reason the external signal is removed from the device then the clock synthesizer will generate its own internal clock signal to allow the device to enter some kind of error recovery routine. This is known as LIMP mode. The clock frequency generated will not have an associated timing spec but should be around 9 MHz. 8.4.3 Chip-select Submodule Typical microcomputer systems require external hardware to provide select signals to external peripherals. This MCU integrates these functions on-chip in order to provide the cost, speed, and reliability benefits of a higher level of integration. The chip-select signals can also be programmed as output enable, read or write strobe, or IACK signals. Since initialization software would probably reside in a peripheral memory device controlled by the chip-select circuits, a CSBOOT register provides default reset values to support bootstrap operation. The chip-select submodule supports the following programmable features: 40 TS68332 2118A–HIREL–11/05 TS68332 8.4.3.1 Twelve Programmable Chip-select Circuits Twelve chip select signals are available (CSBOOT) and CS10 tro CSO). These signals use the CSBOOT pin, bus arbitration pins BR, BG, and BGACK, function code pins FC2-FC0, and address pins A23-A19. The (CSBOOT) pin is dedicated to a single function because it must function after a reset with no initialization, the other chip select circuits share functions on their output pins. All 12 chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base register and option register which contain the programmable characteristics of that chip select. Using these address lines as chip select signals does not restrict the large linear address space of the MCU since the chip select logic always uses the internal address lines. 8.4.3.2 Variable Block Sizes The block size starting from the specified base address can be programmed as 2K, 8K, 16K, 64K, 128K, 256K, 512Kbytes or 1-Mbyte. 8.4.3.3 Both 8-bit and 16-bit Ports Supported Eight-bit ports are accessible on both odd and even addresses when connected to data bus bits 15-8. Sixteen-bit ports can be accessed as odd bytes, even bytes, or words. 8.4.3.4 Read Only, Write Only, or Read/write Capability Chip selects can be asserted synchronized with read, write, or both read and write. 8.4.3.5 Address Strobe and Data Strobe Timing Option Chip-select signals can be synchronized with either address strobe or data strobe, so that control signals such as output enable or write enable can be easily generated. 8.4.3.6 Internal DSACK Generation with Wait States The port programmed in the pin assignment register can be referenced for generating DSACK and the proper number of wait states for a particular device programmed by the user. 8.4.3.7 Address Space Checking Supervisor, user, and CPU space accesses can be optionally checked. 8.4.3.8 Interrupt Priority Level Checking In the IACK cycle, the acknowledged interrupt level can be compared with the user-specified level programmed in the option field. If autovector option is selected, AVEC is internally asserted. 8.4.3.9 Discrete Output Port C pins A22-A19 and FC2-FC0 can be programmed for discrete output, with data stored in the pin data register (CSPDR). 8.4.3.10 68000-type Peripheral Support 68000-type peripherals that require an E clock for synchronization can be supported. Chip select is asserted, synchronized with the E clock on pin A23, providing correct data bus timing for the MCU. 41 2118A–HIREL–11/05 8.4.4 Test Submodule The test submodule is a primary tool to support all types of testing, such as production test and user self-test, that is integrated into the MCU. The submodule supports scan-based testing of various modules in the MCU. The scan test employed here consists of the test submodule performing the following steps: • serially shifting stimulus data to an idle Module Under Test (MUT) • activating the module under test • serially shifting response data back from the module under test • latching the response data for interrogation by the bus master The further information to the System Integration Module Manual. 8.5 QSM Queued Serial Module The queued serial module (QSM) provides the microcontroller unit (MCU) with two serial communication interfaces divided into two submodules: the queued serial peripheral interface (QSP) and the serial communications interface (SCI). The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals and other MCUs. It is enhanced by the addition of a RAM queue for receive and transmit data. The SCI is a full-duplex universal asynchronous receiver transmitter (UART) serial interface. These submodules operate independently (see Figure 8-8 on page 43). 8.5.1 QSM Pins The QSM has nine external pins. Eight of these pins can be used as general-purpose I/O pins. If the pin is not being user for its submodule function. The ninth pin, RXD, is an input-only pin used exclusively by the SCI submodule. The pins are identified as follows: MISO – Master In Slave Out MOSI – Master Out Slave In SCK – Serial Clock PCS0/SS – Peripheral Chip-Select 0/Slave Select PCS3-PCS1 – Peripheral Chip Selects 3-1 TXD – Transmit Data – RXD – Receive Data 8.5.2 42 QSPI Submodule The QSPI submodule communicates with external peripherals and other MCUs via a synchronous serial bus. The QSPI is fully compatible with the Serial Peripheral Interface (SPI) systems found on other Atmel-Grenoble devices such as the 68HC11 and 68HC05 families. It has all of the capabilities of the standard SPI system as well as several new features. The following paragraphs describe the main feature of the QSPI. TS68332 2118A–HIREL–11/05 TS68332 Figure 8-8. 8.5.3 QSM Block Diagram QSPI Features Standard SPI features are listed below, followed by a list of the additional features offered on the QSPI: • full duplex, three-wire synchronous transfers • half-duplex, two-wire synchronous transfers • master or slave operation • programmable master bit rates • programmable clock polarity and phase • end-of-transmission interrupt flag • master-master mode fault flag • easily interfaces to simple expansion parts (A/D converters, EEPROMs, display drivers, etc.) 8.5.4 QSPI Enhanced Features A programmable queue allows the QSPI to perform up to 16 serial transfers without CPU intervention. Each transfer corresponds to a queue entry containing all the information needed by the QSPI to independently complete one serial transfer. This unique feature greatly reduces CPU/QSPI interaction, resulting in increased CPU and system throughput. Once the CPU has set up the queue of QSPI commands and enables the QSPI, the QSPI operates independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating that it has finished, and then either interrupts the CPU or waits for CPU intervention. Programmable Peripheral Chip Selects: Four peripheral chip-select pins allow the QSPI to access up to 16 independent peripherals by decoding the four peripheral chip-select signals. Up to four independent peripherals can be selected by direct connection to a chip-select pin. The peripheral chip selects simplify interfacing to two or more serial peripherals by providing dedicated peripheral chip-select signals and thus alleviating the need for CPU intervention. 43 2118A–HIREL–11/05 Wraparound Transfer Mode: Wraparound transfer mode allows for automatic, continuous reexecution of the preprogrammed queue entries. Newly transferred data replaces previously transferred data. Wraparound simplifies interfacing with A/D converters by automatically providing the CPU with the latest conversions in the QSPI RAM. Consequently, serial peripherals appear as memory-mapped parallel devices to the CPU. Programmable Transfer Length: The number of bits in a serial transfer is programmable from 8 to 16 bits, inclusive. For example, 10-bit could be used for communicating with an external 10-bit A/D convertor. Likewise, a vacuum fluorescent display driver might require a 12-bit serial transfer. The programmable length simplifies interfacing to serial peripherals that require different data lengths. Programmable Transfer Delay: An inter-transfer delay may be programmed from approximately 1 to 500 µs (using a 16.78 MHz system clock). For example, an A/D convertor may require time between transfers to complete a new conversion. The default delay is 1 µs. The programmable length of delay simplifies interfacing to serial peripherals that require delay time between data transfers. Programmable Queue Pointer: The QSPI has a pointer that points to the queue location containing the data for the next serial transfer. The CPU can switch from one task to another in the QSPI by writing to the queue pointer, changing the location in the queue that is to be transferred next. Otherwise, the pointer increments after each serial transfer. By segmenting the queue, multiple-task support can be provided by the QSPI. Continuous Transfer Mode: The continuous transfer mode allows the user to exchange an uninterrupted bit stream with a peripheral. A minimum of 8-bit and a maximum of 256-bit may be transferred in a single burst without CPU intervention. Longer transfers are possible; however, minimal CPU intervention is required to prevent loss of data. A 1microsecond pause (using a 16.78 MHz system clock) is inserted between each entry transfer. QSPI RAM: The QSPI uses an 80-byte block of dual-access static RAM that can be accessed by both the QSPI and the CPU. Because of sharing, the length of time taken by the CPU to access the QSPI RAM, when the QSPI is enabled, may be longer than when the QSPI is disabled. From one to four CPU wait states may be inserted by the QSPI in the process of reading or writing. The RAM is divided into three segments: receive data, transmit data, and command control. Receive data is information received from a serial device external to the MCU. Transmit data is information stored by the CPU for transmission to an external peripheral chip. Command control contains all the information needed by the QSPI to perform the transfer. Figure 8-9 on page 45 illustrates the organization of the RAM. 44 TS68332 2118A–HIREL–11/05 TS68332 Figure 8-9. 8.5.5 Organization of the QSPI RAM SCI Submodule The SCI submodule is used to communicate with external devices and other MCUs via an asynchronous serial bus. The SCI is fully compatible with the SCI systems found on other Atmel MCUs such as the 68HC11 and 68HC05 families. It has all of the capabilities of previous SCI systems as well as several significant new features. • Features Standard SCI features are listed below, followed by a list of additional features offered: Standard SCI Two-wire Systems Feature: • Standard Non Return to Zero (NRZ) mark/space format • Advanced error detection mechanism (detects noise duration up to 1/16 of a bit-time) • Full-duplex operation • Software selectable word length (8- or 9-bit words) • Separate transmitter and receiver enable bits • May be interrupt driven • Four separate interrupt enable bits Standard SCI Receiver Features: • Receiver wake up function (idle or address mark bit) • Idle-line detect • Framing error detect • Noise detect • Overrun detect • Receive data register full flag Standard SCI Transmitter Features: • Transmit data register empty flag • Transmit complete flag • Send break 45 2118A–HIREL–11/05 QSM-enhanced SCI Two-wire Systems Features: • 13-bit programmable baud rate modulus counter • Even/odd parity generation and detection QSM-enhanced SCI Receiver Features • Two idle-line detect modes • Receiver active flag 13-bit Programmable Baud Rate Modulus Counter: A baud rate modulus counter has been added to provide the user with more flexibility in choosing the crystal frequency for the system clock. The modulus counter allows the SCI baud rate generator to produce standard transmission frequencies for a wide range of system clocks. The user is no longer constrained to select crystal frequencies based on the desired serial baud rate. This counter baud rates from 64 baud to 524 baud with a 16.78 MHz system clock. Even/odd Parity Generation and Detection: The user now has the choice either of seven or eight data bits plus one parity bit, or of eight or nine data bits with no parity bit. Even or odd parity is available. The transmitter automatically generates the parity bit for a transmitted byte. The receiver detects when a parity error has occurred on a received byte and sets a parity error flag. Two Idle-line Detect Modes: Standard Atmel-Grenoble SCI systems detect an idle line when 10 or 11 consecutive bit-times are all ones. Used with the receiver wake up mode, the receiver can be awakened prematurely if the message preceding the start of the idle line contained ones in advance of its stop bit. The new (second) idle-line detect mode only starts counting idle time after a valid stop bit is received, which ensures correct idle-line detection. Receiver Active Flag (RAF): Receiver Active Flag (RAF) indicates the status of the receiver. It is set when a possible start bit is detected and is cleared when an idle line is detected. RAF is also cleared if the start bit is determined to be line noise. This flag can be used to prevent collisions in systems with multiple masters. For further information refer to the System Integration Module Manual. 8.6 Standby RAM (with TPU emulation) The TS68332 contains 2-Kbytes of standby RAM. This section describes the operation and control of the RAM module. 8.6.1 Overview The Ram module contains 2048 bytes of fully static RAM, powered by VDD in normal operation. The entire array may be used as standby RAM if power is supplied to the VSTBY pin. Switching between VDD and VSTBY occurs automatically. The RAM may be used as general-purpose memory for the MCU, providing fast, two-clock accesses to the CPU. Typically, the RAM is used for program control stacks and frequently modified data variables. The CPU may read or write byte, word, or long-word data. The RAM may also be used as microcode control memory for the Time Processor Unit (TPU). The TPU must be placed in emulation mode to use the RAM in this manner which allows users to develop their own microcode primitives. 46 TS68332 2118A–HIREL–11/05 TS68332 8.6.2 RAM Array Addressing The RAM array can be placed anywhere in the address map of the array base address (RAMBAR), provided that it is on a 2-Kbytes boundary and does not overlap the three RAM module control registers used for control and testing. RAMBAR can be written only once after reset. This prevents the RAM array being accidentally remapped by software. 8.6.3 TPU Emulation Mode Operation The RAM array may be used as the microcode control store for the TPU module. This mode of operation is selected from within the TPU. See Development support in the TPU manual for a complete description. The TPU is connected to the RAM via a dedicated bus. While in emulation mode, the access timing of the RAM module matches the timing of the TPU microinstruction ROM to ensure accurate emulation. Normal accesses via the IMB are inhibited and the control register have to effect, allowing external RAM to emulate the 2K RAM array at the same addresses. The further information refer to the System Integration Module Manual. 8.7 TPU Overview The TPU performs simple as well as complex timing tasks, independently from the CPU, making it the latest advance in timer systems. Viewed as a special purpose microcomputer, this processor performs two operations, match and capture, on one operand: TIME. Every occurrence of either action is called an event. The servicing of these events by the TPU replaces the servicing of interrupts by the host Central Processing Unit (CPU). The timing functions currently synthesized are the following: • Discrete input/output • Input capture /input transition counter • Output compare • Pulse width modulation • Synchronized pulse width modulation • Period measurement with additional transition defect • Period measurement with missing transition detect • Position-synchronized pulse generator • Stepper motor • Period/pulse-width accumulator The previous pre-programmed functions are related to the TPU Rom mask set A, currently in use for the TS68332 MCU, as the “standard” TPU maskset. The advanced TPU affords for the first time high-resolution timing and multiple time function capability (flexibility) in the timer system pins. 47 2118A–HIREL–11/05 8.7.1 High-resolution Timing High-resolution timing is limited by CPU overhead required for servicing timing tasks such as period measurement, pulse measurement, pulse-width modulated waveform generation, etc. On the TPU, high-resolution timing is achieved by two main capabilities: • reduced latency • reduced service time, which free the CPU to focus on other responsibilities The TPU provides a higher resolution than the CPU could achieve, and creates no CPU overhead for servicing timing tasks. 8.7.1.1 Latency Latency is the interval of time from an even to the start of event servicing. The ability of the TPU to service its own interrupts or events reduces latency and the CPU is not required to service each input transition capture that occurs on a pin, or to determine each match time required for waveform synthesis. Once configured by the host CPU, the self-contained TPU performs complex time functions requiring high resolution with little or no CPU intervention. 8.7.1.2 8.7.2 Service Time Service is the time expended servicing an event. In older microcontroller unit (MCU) timer functions, the service time is constrained because the MCU instruction set is not optimized for time function synthesis. The TPU instruction set is optimized, and time functions are synthesized with fewer instructions than the CPU. Instructions execute faster and service time is reduced. Instructions executed by the TPU are not user software, but firmware, special-purpose microcode written by Atmel-Grenoble to perform as set time functions. Microcode is placed into the TPU control store (ROM) when the device is manufactured. Features • 16 channels; each channel associated with a pin. • Each channel can perform any time function. • Each time function may be assigned to more than one channel at a given time. • Each channel has an event register comprised of the following: – 16-bit capture register – 16-bit compare/match register – 16-bit greater-than or equal-to comparator • Each channel can be synchronized to one or both of the two 16-bit free-running timer count registers (TCR1 and TCR2). • TCR1 is clocked from the output of a prescaler. The prescaler’s input is the internal TPU system clock divided by either 4 or 32. The four settings of the prescaler are divide by 1, 2, 4 and 8. Channels using TRC1 have the capability to resolve down to the TPU system clock divided by four. • TCR2 is clocked from the output of a prescaler. The prescaler’s input is the external TCR2 pin. The four settings of the prescaler are divide by 1, 2, 4 and 8. Channels using the TCR1 have the capability to resolve down to the PRU system clock divided by 8. • TCR2 may be used as a hardware pulse accumulator clocked from the external TCR2 pin, or as a gated pulse accumulator or the clock that increments TCR1. 48 TS68332 2118A–HIREL–11/05 TS68332 • All channels have at least six 16-bit parameter registers. Channels 14 and 15 each have eight 16-bit parameter registers. All parameter registers are contained in a dual-port RAM, accessible from both the TPU and CPU. • A scheduler with three priority levels segregates high, middle, and low-priority time functions. Any channel may be assigned to one of these three priority levels. • All time functions are microcoded. • Emulation and development support is provided for all time function features such as breakpoint, freeze and single step, giving internal register accessibility. • Coherent transfer capability for two parameter is provided in hardware. • Coherent transfer capability for N parameters may be performed as a TPU microcode function. (Refer to development support in the TPU reference manual for further details on this feature). 8.7.3 General Concept The TPU is an intelligent, semi-autonomous peripheral dedicated to timing control. Its intelligence enables the servicing of timing events without CPU intervention. This device uses a private microengine for a processor, a scheduler, input/output channels, ROM instructions, and shared-access data RAM to operate independently and simultaneously with the CPU (see Figure 8-10 on page 50). Consequently, the setup and service time for each timer event is minimized. A “time-of-delay” approach is used where all time functions are related to one of two 16-bit freerunning TCRs. Time functions are synthesized by combining the two time primitives, match and capture events. By performing these time primitives in hardware, the TPU can precisely determine the time when a match event is to occur and then specify the state of the output pin accordingly. The TPU can also accurately record the time at which an input transition occurs and can perform calculations based on the time of the occurrence. An event register for each channel provides for simultaneity of match/capture-event occurrences on all channels. When a match or input capture event requiring service occurs on a channel, the channel generates a service request to the scheduler. The scheduler prioritizes the request with other pending service requests. When the microengine is idle, the scheduler causes the microengine to execute a microcode sequence. When the microengine is busy, the new sequence begins when the code being executed ends. The microengine performs the function, which is defined by the content of the control store, using parameters from the parameter RAM and from the event registers, etc., as needed. The following is an example. Channel X is generating a periodic waveform and presently the output is high. When the value of the TCR used by that channel increments to match the value of the event register of channel X, a match event occurs. The event switches the output to low and generates a new service request to the scheduler. The scheduler than schedules and initiates service of channel X by the microengine. 49 2118A–HIREL–11/05 When execution of the sequence begins, the microengine uses the execution unit: • To obtain (from the parameter RAM) the value representing the duration of counts for which channel X should remain low, and • To add to this value the value from the content of the event register of channel X. The content of the event register is then replaced by this sum; the channel control is set for a match event on the same TCR; and the pin control is set to cause the output pin for channel X to switch high when the event occurs. A channel interrupt, which signals the end of service to the CPU, may be asserted (if the time function provides for it and the interrupt is enabled). The microengine is then free to service the next event determined by the scheduler. Figure 8-10. TPU Simplified Block Diagram HOST INTERFACE CONTROL SCHEDULER SERVICE REQUESTS TIMER CHANNELS CHANNEL 0 CHANNEL SYSTEM CONFIGURATION TCR1 T2CLK CHANNEL 1 TCR2 DEVELOPMENT SUPPORT AND TEST IMB PINS MICROENGINE CHANNEL CONTROL PARAMETER RAM DATA 8.7.4 CONTROL STORE DATA EXECUTION UNIT CONTROL AND DATA CHANNEL 15 Flexibility The TPU has the flexibility to be configured to directly solve the user’s timer requirements. This flexibility is attained through five capabilities: • channel orthogonality • inter-channel communication • programmable channel service priority • selection of timing functions • emulation capability 8.7.4.1 50 Channel Orthogonality Traditionally, timer systems have been limited by the specific functions of channel pins dedicated to perform time functions such as input capture, output compare, or pulse accumulation. All channels of the TPU contain identical hardware and are functionally equivalent in operation, such that any channel can be configured to perform any time function. The user controls the combination of time functions; the only constraint is the number of pins available for timing functions. TS68332 2118A–HIREL–11/05 TS68332 8.7.4.2 Inter-channel Communication The TPU’s ability to service itself requires a continuous flow of direct and indirect communication. Direct communication is accomplished through a “change channel” feature in which any channel of the TPU can operate another channel to affect its state. Indirect communication is provided by a link feature in which any channel can lonk to one more channels, including itself, to signal a need for future service. As a result, the user can reference the operation of one channel to the occurrence of a specific action on another channel. 8.7.4.3 Programmable Channel Service Priority Applications may require different priorities of event service. The channel service priority may be programmed to one of three levels: high, middle, and low. The scheduler allows calculation of worst-case latency for event servicing and ensures servicing of all channels by preventing permanent blockage. 8.7.4.4 Selection of Timing Functions The available timing functions can be programmed to operate on any channel. Parameter registers associated with each channel are used as general-purpose time operands. 8.7.4.5 Emulation Capability The TPU cannot resolve all timer problems using predefined time functions alone; therefore, development of user-defined time functions is allowed in emulation mode. Using the RAM module of the MCU as a “writable control store” provides TPU emulation. In TPU emulation mode, an auxiliary bus connection is made between the RAM module and the TPU module, and access to the RAM module via the intermodule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer information between the modules. To ensure exact emulation, the access timing of the RAM module remains consistent with the TPU ROM control store. 8.7.5 Applications The TPU’s high speed, versatile architecture, and time functions facilitate its use in many control applications, such as stepper motors and angle-based engine control. Control of a stepper motor or an angle-based automotive engine usually requires high CPU overhead. These applications show how the SM, PMA/PPM, and time functions minimize the overhead associated with these applications, and provide sophistication and flexibility for a wide variety of applications. Further detailed information on the TPU is found in the TPU reference manual. 9. Preparation For Delivery 9.1 Packaging Microcircuit are prepared for delivery in accordance with MIL-M-38510. 9.2 Certificate of Compliance Atmel-Grenoble offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or Atmel-Grenoble standard and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range. 51 2118A–HIREL–11/05 10. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Device should be handled on benches with conductive and grounded surface. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50%, if practical. 52 TS68332 2118A–HIREL–11/05 TS68332 11. Packaging Information Figure 11-1. 132–ball–Ceramic Pin–Grid Array (PGA) 53 2118A–HIREL–11/05 Figure 11-2. 132–lead CERQUAD Notes: 1. Dimensioning and tolerancing per ansi Y14.5M, 1982. 2. Controlling dimensions: inch. 3. Dim A and B define maximum ceramic body dimensions including glass protrusion and mismatch of ceramic body top and bottom. 4. Datum plane - W - is located at the underside of leads where leads exit package body. 5. Datums X-Y and Z to be determined where center leads exit package body at datum - W -. 6. Dim S and V to be determined at seating plane, datum - T -. 7. Dim A and B to be determined at datum plane - T -. 54 TS68332 2118A–HIREL–11/05 TS68332 12. Ordering Information 12.1 Hi-Rel Product Commercial Atmel Part-Number Norms Package Temperature Range Tc (°C) Frequency (MHz) Drawing Number TS68332MRB/C16 MIL-STD-883 PGA 132 -55/+125 16.78 Atmel-Grenoble datasheet TS68332MR1B/C16 MIL-STD-883 PGA 132 tin -55/+125 16.78 Atmel-Grenoble datasheet TS68332MAB/C16 MIL-STD-883 CERQUAD 132 -55/+125 16.78 Atmel-Grenoble datasheet TS68332MRB/C20 MIL-STD-883 PGA 132 -55/+125 20.97 Atmel-Grenoble datasheet TS68332MR1B/C20 MIL-STD-883 PGA 132 tin -55/+125 20.97 Atmel-Grenoble datasheet TS68332MAB/C20 MIL-STD-883 CERQUAD 132 -55/+125 20.97 Atmel-Grenoble datasheet TS68332DESC01ZA MIL-STD-883 PGA 132 tin -55/+125 16.78 5962-9150101MZA TS68332DESC01ZC MIL-STD-883 PGA 132 -55/+125 16.78 5962-9150101MZC TS68332DESC02ZC MIL-STD-883 PGA 132 -55/+125 20.97 5962-9150102MZC TS68332DESC01XA MIL-STD-883 CERQUAD 132 -55/+125 16.78 5962-9150101MXA TS68332DESC02XA MIL-STD-883 CERQIAD 132 -55/+125 20.97 5962-9150102MXA 12.2 Standard Product Commercial Atmel Part-Number Norms Package Temperature Range Tc (°C) Frequency (MHz) Drawing Number TS68332VR16 Atmel-Grenoble Standard PGS 132 -40/+85 16.78 Atmel-Grenoble datasheet TS68332MR16 Atmel-Grenoble Standard PGS 132 -55/+125 16.78 Atmel-Grenoble datasheet TS68332VA16 Atmel-Grenoble Standard CERQUAD 132 -40/+85 16.78 Atmel-Grenoble datasheet TS68332MA16 Atmel-Grenoble Standard CERQUAD 132 -55/+125 16.78 Atmel-Grenoble datasheet TS68332VR20 Atmel-Grenoble Standard PGS 132 -40/+85 20.97 Atmel-Grenoble datasheet TS68332MR20 Atmel-Grenoble Standard PGS 132 -55/+125 20.97 Atmel-Grenoble datasheet TS68332VA20 Atmel-Grenoble Standard CERQUAD 132 -40/+85 20.97 Atmel-Grenoble datasheet TS68332MA20 Atmel-Grenoble Standard CERQUAD 132 -55/+125 20.97 Atmel-Grenoble datasheet 55 2118A–HIREL–11/05 TS 68332 M R B/C 16 A Revision level Manufacturer's Prefix Type Speed (MHz) 16 : 16 MHz 20 : 20 MHz Temperature range: Tc M : -55, +125˚C V : -40, +85˚C C : 0, +70˚C Screening level : __ : Standard B/C : MIL-STD-883, class B DSCC : DESCOx Mxx * Package : Standard lead finish R: Pin grid Array 132 Gold A: CERQUAD 132 (Gullwing leads) Hot solder dip Note: 56 Lead finish : 1 : Tinned for PGA _ : Gold for PGA or Tinned for CERQUAD For availability of different versions, contact your Atmel sales office. TS68332 2118A–HIREL–11/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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