I2C to USB Bridge Guide(pdf)

CY3240-I2USB
I2C-USB Bridge Guide
Author: Petro Kobluk, Valeriy Kyrynyuk
Associated Project: Yes
Associated Part Family: CY8C24894
Software Version: PSoC Designer™ v. 4.3
Associated Application Notes: AN2352
Introduction
Description of I2C-USB Bridge
The main purpose of the I2C-USB bridge is to test, tune,
2
and debug programs that have an I C slave interface. This
application can also be useful for data acquisition and
regulation under PC control. A wide variety of devices can
be connected to the PC using this bridge. Among them
are: EEPROMs, realtime clocks, ADC/DAC converters,
LCD displays, regulated DC/DC converters, port
2
expanders and many other devices incorporating the I C
interface. The number of devices that can be connected is
2
constrained only by the I C address limit and physical
2
ability of the I C bus.
The external pins are shown in Figure 2.
The I2C-USB bridge is connected to the PC in the same
way as an HID device and requires no additional driver
when connected to a PC installed with Windows®. This
I2C-USB bridge works as a master in the I2C bus and is
controlled by a PC program via the USB. In addition, a
demonstration PC program is included with the project to
2
demonstrate bridge operation with connected I C slaves.
2
Figure 1. I2C-USB Bridge Between PC and I C Slaves
I2C
USB
I2C-USB
Bridge
`
I2 C Slave
Device
I2 C Slave
Device
2k
22
D-
21
USB
D+
Vss
20
CY8C24894
2k
15
SCL
16
SDA
I2C
INT
19
2k
50
Vss
2
The device meets the requirements of the I C specification
2
for standard and fast speed I C devices and the
requirements for USB HID devices. The bridge is powered
by the USB and consumes less than 500 mA. The device
can be configured to several I2C clock rates: 50 kHz, 100
kHz, and 400 kHz.
The USB communication function uses two packet types:
one for input, and another for output data flow. The size of
both packets is 64 bytes. The maximum bandwidth of this
configuration is 64 bytes/s. This is enough for most I2CUSB bridge applications.
I2 C Slave
Device
Because this I2C-USB bridge uses only a small subset of
the PSoC device’s resources, it has a substantial potential
for implementation of additional functions or support of
other interfaces.
September 13, 2006
49
Vdd
2
Several factors determine the maximum limit of I C
devices that can be connected to the bus and the bus wire
length: bus clock rate, capacitance and resistance of the
2
bus wire, and capacitance of the I C device’s pins. For
2
details refer to the THE I C -BUS SPECIFICATION [1].
……….
PC
Figure 2. Simplified Schematic of I2C-USB Bridge
The “Int” pin is a pulled-down bidirectional pin that can be
2
used as additional signal between the bridge and I C slave
device, for sleep mode control, etc.
Revision. **
-1-
CY3240-I2USB
Bridge Circuit
Internal Structure
Appendix B shows the bridge schematic.
The flowchart schematic of the bridge operation algorithm
is depicted in Figure 3. The main program continuously
checks for the presence of a new input packet from the
2
USB. During processing of this packet, the I C transfer is
completed and the result is sent in a USB output packet.
Both packets should be formed according to the I2C-USB
bridge protocol, which is described below.
The bridge has over-voltage and over-current protection
on the USB and I2C slave sides, provides three power
modes for a connected slave device, and includes a level
translator between “I2C” and “Int” pins on the slave and
bridge sides, which allows it to work with any slave device
regardless of the power supply voltage.
There are three power modes that can be chosen: external
power (bridge does not provide power supply on Vdev
pin), +3.3V, and +5V of bridge power supply (U1). The
PSoC® device takes control over U1 by use of the
“Enable” and “VoltCnt” pins. PSoC can detect the
presence of a power supply on Vdev using the “Vsense”
pin. The bridge also turns off the internal power supply if
external voltage is connected.
U4 provides over-voltage protection of the USB line from
the bridge side. U6 provides over-current protection of the
bridge from the slave device. U5 provides voltage level
translation for the I2C lines.
Two LEDs show information about bridge status. “Status”
LED (green) lights when bridge is enumerated into USB,
and blinks during communication between the PC and the
bridge. The “Dev Pow” LED (red) lights vividly if +5V of
internal power is connected to Vdev, a weak light informs
of a connection of +3.3V to Vdev, and the light blinks when
external power is connected to Vdev.
September 13, 2006
The input packets can contain information about the
reconfiguration or initialization of the I2C bus driver. In this
2
case, the I C transfer is not performed. The device also
complies with the USB specification for switching
connected devices into suspend mode. If there is no
activity on the USB bus then the device will switch to sleep
mode.
We examine the worst-case situation, which can occur
2
during I C transfer. After sending the address byte, if the
2
I C slave device does not confirm by ACK or if the bridge
device receives NACK while sending the data bytes, then
2
the program breaks the current I C transfer and outputs a
USB packet containing information about the error status
2
of the last transaction. If during the I C transfer the bus
2
does not respond (starvation of I C bus) then the new
incoming USB packet breaks the current transaction and
the program jumps to processing the new packet.
Revision. **
-2-
CY3240-I2USB
Figure 3. Flowchart of Bridge Program
Initialization of
I2C-USB Bridge
Turn to
sleep mode?
YES
Turn to sleep mode
USB packet
arrive?
YES
Config I2C?
YES
Configure I2C
clock
Reinit I2C?
YES
Restart I2C bus
Send
I2C Start ?
Handling:
“Int” pin status,
“Int” pin generation
power control
YES
Internal
Transaction?
YES
Make Start condition,
send address byte
Send I2C
Restart?
YES
Make ReStart condition,
send address byte
NO
Slave send
ACK?
Read from I2C?
YES
Read data from the
slave device. Send
ACK
Write data to the slave
device.
Read ACK
I2C Stop?
YES
Make Stop condition
YES
BURST mode?
YES
Buffer Full?
Next transfer?
YES
SendToUSB
September 13, 2006
Revision. **
-3-
CY3240-I2USB
Protocol Description
The protocol describes the structure of USB input and
output packets (Figure 4). The USB packet can contain
2
2
several I C transfers. The total size of I C transfers into
input/output packet cannot exceed 64 bytes. The 80h bitmask into the “length” byte indicates whether the current
transfer is the last into packet (bit = 0) or next transfer is
present (bit = 1). This algorithm allows the bridge to attain
the maximum speed and flexibility during communication
2
with I C devices. The first byte in the transfer of an
incoming packet is always a “control” byte. The “control”
byte determines how the program will treat the subsequent
bytes in the packet. The details of the “control” byte are
shown in Tables 1 and 2.
Figure 4. Format of I2C Transfer
I2 C Data Write Transfer
USB Input Packet
USB Output Packet
control
length
[Addr]
data0
data1
status
data0
ACK
data1
ACK
data2…..dataN
ACK
data2…..dataN-1
dataN
dataN
ACK
I2C Data Read Transfer
USB Input Packet
USB Output Packet
control
length
[Addr]
status
data0
data1
Table 1. “Control“ Byte Description
Bit
Description
2
0
Write/read I C operation
1
Make “Start” condition, send address byte
2
Make “ReStart” condition, send address byte
3
Make “Stop” condition after data transfer
4
Reinitialize I C bus
data2…..dataN
dataN
When bit 5 is set, bits 2 and 3 define the I2C clock rate and
all other low bits will not be processed. If bit 4 is set, the
low 4 bits also will not be processed and there will be no
2
I C transfer (refer to Figure 3).
Table 2. “Control” Byte Bits during I2C Reconfiguration
Control Byte Bit 3, 2
2
I C Clock Rate
2
00
100 kHz
5
Make I C Reconfiguration
01
400 kHz
6, 7
Choose bus
2
00 – I C
01 – SPI (reserved)
10 – UART (reserved)
11 – LIN (reserved)
10
50 kHz
11
Reserved
2
September 13, 2006
Revision. **
-4-
CY3240-I2USB
The next byte of the incoming packet contains the length
of the data array in bytes. This is the array of bytes to be
2
written to or read from the I C slave device. The address
byte, if present, is not included in the “length” byte. The
maximum length of data in one packet is 61 bytes. If more
than 61 data bytes need to be sent or received then the
transfer will be performed using several USB packets. In
the first packet the “Start” or “Restart” flags must be set
and in the last packet the “Stop” flags in the “control” byte
must be set.
If the “Restart” bit is set into the “control” byte then the “Int”
pin generates a short interrupt positive pulse, which can
be used to awaken the slave device.
After the “length” byte, an “Address” byte might be
2
present. This byte holds the address of the I C slave that
2
will be used in the I C transfer. The “Address” byte will be
present in the packet only if the “Start” or “Restart” flag is
set in the “control” byte. Its value must be in the range
0..127. The 128..255 address is reserved for internal
bridge operation, as power control or “Int” pin control.
The first byte in the transfer of the output packet always
contains the “status” byte of the I2C transfer. If status is
2
zero then the bridge cannot find the I C slave device and
all transfer with the device is canceled. In this case, all
packet bytes that follow must be ignored. If the “status”
byte is non-zero then the slave device is present and the
bytes that follow are valid. If data was written to the slave
device then the output frame contains an array of bytes
that indicate the ACK (‘1’) or NACK (‘0’) status of each
byte that was written. The last byte received by a slave
device has a NACK status (zero value). All bytes that
follow are ignored by the slave (perhaps the device’s read
buffer is full). The length of the response data array is the
same length as the input packet data array.
For Power and “Int” pin control, the address byte should
be 0x80. If the “read operation” bit into the “control” byte is
set, then the current power mode and current I2C speed
value will be returned. Also, the “status” byte will indicate
the presence of Vdev voltage on the bridge (0x04 mask in
“status” byte) and “Int” pin status (0x02 mask in “status”
byte). When a write operation is performed, the data byte
should contain the power mode byte. Power mode byte
options include:
•
0: external power
•
1: +5V internal power
•
2: +3.3V internal power
September 13, 2006
Interpretation of data in the input/output packet will depend
2
on whether the I C performs a read or write operation. If
2
data is to be written to the I C slave then the data bytes
will go immediately after the “address” or “length” byte. If
data is to be read from the I2C slave then the input packet
will contain no additional information.
2
If there is read data from the I C slave device then the
bytes containing this data follow the “status” byte in the
output packet. The I2C-USB bridge sends an ACK signal
while reading the data from the slave device and sends a
NACK once the last byte has been read.
Also, BURST mode was implemented into the bridge. This
mode is necessary for high-speed data acquisition and
allows the device to read 1000..5000 samples per second
from the I2C slave. To switch the bridge to this mode only
the one header transfer should be sent with 40h bit set in
the “length” byte – and after this the bridge will switch to
BURST mode and continuously send the results of the
header transfer into the output packet. The output packet
2
contains several transfer results. For example, if I C
transfer reads 8 bytes from the slave, the output packet
62
will contain N = INT (
) = 6 read slave samples. Each
1+ 8
time the output buffer is filled it will be sent to the USB
host.
Revision. **
-5-
CY3240-I2USB
Figure 5. BURST Mode Format
USB Input Packet
control
length
Addr
USB Output Packets
status
data0
data1
data2…..dataN
dataN
status
data0
data1
data2…..dataN
dataN
N < 62 bytes per packet
…………………………………………… ..
status
data0
data1
data2…..dataN
dataN
Appendix A. References
[1]. THE I2C-BUS SPECIFICATION.
http://www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf
September 13, 2006
Revision. **
-6-
CY3240-I2USB
Appendix B. Schematic of Cypress I2C-USB Bridge
Figure 6. Schematic of Cypress I2C-USB Bridge
Figure 7. Cypress I2C-USB Bridge Board
September 13, 2006
Revision. **
-7-
CY3240-I2USB
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone: 408-943-2600
Fax: 408-943-4730
http://www.cypress.com
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
September 13, 2006
Revision. **
-8-