STMICROELECTRONICS ST24W04M6TR

ST24C04, ST25C04
ST24W04, ST25W04
4 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x04 versions
– 2.5V to 5.5V for ST25x04 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W04 and ST25W04
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers a range of 4 Kbits I2C bus
EEPROM products, the ST24/25C04 and the
ST24/25W04. In the text, products are referred to
as ST24/25x04, where "x" is: "C" for Standard
version and "W" for hardware Write Control version.
8
8
PSDIP8 (B)
0.25mm Frame
PRE
Write Protect Enable
E1-E2
Chip Enable Inputs
SDA
Serial Data Address Input/Output
SCL
Serial Clock
MODE
Multibyte/Page Write Mode
(C version)
WC
Write Control (W version)
VCC
Supply Voltage
VSS
Ground
February 1999
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
2
E1-E2
PRE
SCL
Table 1. Signal Names
1
1
SDA
ST24x04
ST25x04
MODE/WC*
VSS
AI00851E
Note: WC signal is only available for ST24/25W04 products.
1/16
ST24/25C04, ST24/25W04
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24x04
ST25x04
PRE
E1
E2
VSS
8
7
6
5
1
2
3
4
ST24x04
ST25x04
VCC
MODE/WC
SCL
SDA
PRE
E1
E2
VSS
AI00852E
1
2
3
4
8
7
6
5
VCC
MODE/WC
SCL
SDA
AI01107E
Table 2. Absolute Maximum Ratings (1)
Symbol
Value
Unit
Ambient Operating Temperature
–40 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
TLEAD
Lead Temperature, Soldering
215
260
°C
TA
Parameter
VIO
Input or Output Voltages
VCC
Supply Voltage
VESD
(SO8 package)
(PSDIP8 package)
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
(3)
(2)
40 sec
10 sec
–0.6 to 6.5
V
–0.3 to 6.5
V
4000
V
500
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
The ST24/25x04 are 4 Kbit electrically erasable
programmable memories (EEPROM), organized
as 2 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endurance of one million erase/write cycles with a data
retention of 40 years.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2C standard, two wire serial interface which uses a bi-directional data bus and serial clock. The memories
2/16
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus definition. This is used together with 2 chip enable inputs
(E2, E1) so that up to 4 x 4K devices may be
attached to the I2C bus and selected individually.
The memories behave as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
ST24/25C04, ST24/25W04
Table 3. Device Select Code
Device Code
Chip Enable
Block
Select
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
E2
E1
A8
RW
Note: The MSB b7 is sent first.
Table 4. Operating Modes (1)
Mode
RW bit
MODE
Bytes
Current Address Read
’1’
X
1
X
1
Random Address Read
’0’
’1’
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Sequential Read
’1’
X
1 to 512
Byte Write
’0’
X
1
START, Device Select, RW = ’0’
’0’
VIH
4
START, Device Select, RW = ’0’
’0’
VIL
8
START, Device Select, RW = ’0’
Multibyte Write
Page Write
(2)
Similar to Current or Random Mode
Notes: 1. X = VIH or VIL
2. Multibyte Write not available in ST24/25W04 versions.
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are terminated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E1 - E2). These chip enable inputs
are used to set the 2 least significant bits (b2, b3)
of the 7 bit device select code. These inputs may
be driven dynamically or tied to VCC or VSS to
establish the device select code.
Protect Enable (PRE). The PRE input pin, in addition to the status of the Block Address Pointer bit
(b2, location 1FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynamically. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W04 and
ST25W04 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When unconnected, the WC input is internally read as VIL and
the memory area is not write protected.
3/16
ST24/25C04, ST24/25W04
SIGNAL DESCRIPTIONS (cont’d)
The devices with this Write Control feature no
longer support the Multibyte Write mode of operation, however all other write modes are fully supported.
Refer to the AN404 Application Note for more detailed information about Write Control feature.
DEVICE OPERATION
I2C Bus Background
The ST24/25x04 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for synchronisation. The ST24/25x04 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x04 continuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition terminates communication between the ST24/25x04
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x04
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication between the bus master and the slave ST24/25x04,
the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
VCC
16
RL max (kΩ)
RL
12
RL
SDA
MASTER
CBUS
SCL
8
CBUS
4
VCC = 5V
0
100
200
CBUS (pF)
4/16
300
400
AI01100
ST24/25C04, ST24/25W04
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
20
kΩ
ZWCL
WC Input Impedance (ST24/25W04)
VIN ≤ 0.3 VCC
5
ZWCH
WC Input Impedance (ST24/25W04)
VIN ≥ 0.7 VCC
500
tLP
Low-pass filter input time constant
(SDA and SCL)
kΩ
100
ns
Max
Unit
Note: 1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±2
µA
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
SDA in Hi-Z
±2
µA
Supply Current (ST24 series)
VCC = 5V, fC = 100kHz
(Rise/Fall time < 10ns)
2
mA
Supply Current (ST25 series)
VCC = 2.5V, fC = 100kHz
1
mA
VIN = VSS or VCC,
VCC = 5V
100
µA
VIN = VSS or VCC,
VCC = 5V, fC = 100kHz
300
µA
VIN = VSS or VCC,
VCC = 2.5V
5
µA
VIN = VSS or VCC,
VCC = 2.5V, fC = 100kHz
50
µA
ICC
ICC1
ICC2
Supply Current (Standby)
(ST24 series)
Supply Current (Standby)
(ST25 series)
Min
VIL
Input Low Voltage (SCL, SDA)
–0.3
0.3 VCC
V
VIH
Input High Voltage (SCL, SDA)
0.7 VCC
VCC + 1
V
VIL
Input Low Voltage
(E1-E2, PRE, MODE, WC)
–0.3
0.5
V
VIH
Input High Voltage
(E1-E2, PRE, MODE, WC)
VCC – 0.5
VCC + 1
V
VOL
Output Low Voltage (ST24 series)
IOL = 3mA, VCC = 5V
0.4
V
Output Low Voltage (ST25 series)
IOL = 2.1mA, VCC = 2.5V
0.4
V
5/16
ST24/25C04, ST24/25W04
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
Symbol
Alt
tCH1CH2
tR
tCL1CL2
Max
Unit
Clock Rise Time
1
µs
tF
Clock Fall Time
300
ns
tDH1DH2
tR
Input Rise Time
1
µs
tDL1DL1
tF
Input Fall Time
300
ns
tCHDX
(1)
tSU:STA
Parameter
Min
4.7
µs
Clock Pulse Width High
4
µs
Clock High to Input Transition
tCHCL
tHIGH
tDLCL
tHD:STA
Input Low to Clock Low (START)
4
µs
tCLDX
tHD:DAT
Clock Low to Input Transition
0
µs
tCLCH
tLOW
Clock Pulse Width Low
4.7
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
250
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
4.7
µs
tDHDL
tBUF
Input High to Input Low (Bus Free)
4.7
µs
tCLQV (2)
tAA
Clock Low to Next Data Out Valid
0.3
tCLQX
tDH
Data Out Hold Time
300
fC
fSCL
Clock Frequency
100
kHz
tW (3)
tWR
Write Time
10
ms
3.5
µs
ns
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
DEVICE OPERATION (cont’d)
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
6/16
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 2 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1. Thus up to 4 x 4K
memories can be connected on the same bus
giving a memory capacity total of 16 Kbits. After a
START condition any memory on the bus will identify the device code and compare the following 2
bits to its chip enable inputs E2, E1.
The 7th bit sent is the block number (one block =
256 bytes). The 8th bit sent is the read or write bit
(RW), this bit is set to ’1’ for read and ’0’ for write
operations. If a match is found, the corresponding
memory will acknowledge the identification on the
SDA bus during the 9th bit time.
ST24/25C04, ST24/25W04
Figure 5. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
tCHDH
SDA IN
tCHDX
START
CONDITION
tCLDX
tDHDL
SDA
INPUT
SDA
CHANGE
STOP &
BUS FREE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
STOP
CONDITION
tCHDX
WRITE CYCLE
START
CONDITION
AI00795B
Write Operations
The Multibyte Write mode (only available on the
ST24/25C04 versions) is selected when the MODE
pin is at VIH and the Page Write mode when MODE
pin is at VIL. The MODE pin may be driven dynamically with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides access to one block of 256 bytes of the memory. After
receipt of the byte address the device again responds with an acknowledge.
For the ST24/25W04 versions, any write command
with WC = 1 will not modify the memory content.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either VIH
or VIL, to minimize the stand-by current.
7/16
ST24/25C04, ST24/25W04
Figure 6. I2C Bus Protocol
SCL
SDA
START
CONDITION
SCL
1
SDA
MSB
SDA
INPUT
2
SDA
CHANGE
STOP
CONDITION
3
7
8
9
ACK
START
CONDITION
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
CONDITION
AI00792
Multibyte Write. For the Multibyte Write mode, the
MODE pin must be at VIH. The Multibyte Write
mode can be started from any address in the
memory. The master sends from one up to 4 bytes
of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a STOP condition. The duration of the write
cycle is tW = 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 6 most significant address bits A7A2), the programming time is then doubled to a
maximum of 20ms. Writing more than 4 bytes in the
8/16
Multibyte Write mode may modify data bytes in an
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutive bytes as soon as the first address of
these 8 bytes is the first address of the row, the 7
following bytes being written in the 7 following bytes
of this same row.
Page Write. For the Page Write mode, the MODE
pin must be at VIL. The Page Write mode allows up
to 8 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the 5 most significant mem-
ST24/25C04, ST24/25W04
ory address bits (A7-A3) are the same inside one
block. The master sends from one up to 8 bytes of
data, which are each acknowledged by the memory. After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory disconnects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the
master.
Figure 7. Memory Protection
Protect Location
8 byte
boundary
address
b7
Protect Flag
Enable = 0
Disable = 1
b3 b2
1FFh
X
X
Block 1
100h
Block 0
AI00855B
Figure 8. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by ST24xxx
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01099B
9/16
ST24/25C04, ST24/25W04
Figure 9. Write Modes Sequence (ST24/25C04)
ACK
BYTE ADDR
DATA IN
R/W
ACK
MULTIBYTE
AND
PAGE WRITE
ACK
STOP
DEV SEL
START
BYTE WRITE
ACK
START
DEV SEL
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
ACK
ACK
STOP
DATA IN N
AI00793
DEVICE OPERATION (cont’d)
The sequence is as follows:
– Initial condition: a Write is in progress (see Figure
8).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of the
new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it will respond with an ACK, indicating that the memory
is ready to receive the second part of the next
instruction (the first byte of this instruction was
already sent during Step 1).
Write Protection. Data in the upper block of 256
bytes of the memory may be write protected. The
memory is write protected between a boundary
address and the top of memory (address 1FFh)
when the PRE input pin is taken high and when the
Protect Flag (bit b2 in location 1FFh) is set to ’0’.
The boundary address is user defined by writing it
in the Block Address Pointer. The Block Address
Pointer is an 8 bit EEPROM register located at the
address 1FFh. It is composed by 5 MSBs Address
Pointer, which defines the bottom boundary address, and 3 LSBs which must be programmed at
10/16
’0’. This Address Pointer can therefore address a
boundary in steps of 8 bytes.
The sequence to use the Write Protected feature
is:
– write the data to be protected into the top of the
memory, up to, but not including, location 1FFh;
– set the protection by writing the correct bottom
boundary address in the Address Pointer (5
MSBs of location 1FFh) with bit b2 (Protect flag)
set to ’0’. Note that for a correct fonctionality of
the memory, all the 3 LSBs of the Block Address
Pointer must also be programmed at ’0’.
The area will now be protected when the PRE input
pin is taken High. While the PRE input pin is read
at ’0’ by the memory, the location 1FFh can be used
as a normal EEPROM byte.
Caution: Special attention must be used when
using the protect mode together with the Multibyte
Write mode (MODE input pin High). If the Multibyte
Write starts at the location right below the first byte
of the Write Protected area, then the instruction will
write over the first 3 bytes of the Write Protected
area. The area protected is therefore smaller than
the content defined in the location 1FFh, by 3 bytes.
This does not apply to the Page Write mode as the
address counter ’roll-over’ and thus cannot go
above the 8 bytes lower boundary of the protected
area.
ST24/25C04, ST24/25W04
Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W04)
WC
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
ACK
AI01101B
Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read. The memory has an internal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition.
Random Address Read. A dummy write is performed to load the address into the address
counter, see Figure 11. This is followed by another
START condition from the master and the byte
address is repeated with the RW bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Address Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
11/16
ST24/25C04, ST24/25W04
DEVICE OPERATION (cont’d)
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25x04 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x04 terminate the
data transfer and switches to a standby state.
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automatically incremented after each byte output. After a
count of the last memory address, the address
Figure 11. Read Modes Sequence
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
RANDOM
ADDRESS
READ
BYTE ADDR
R/W
ACK
START
DEV SEL
DATA OUT
R/W
ACK
ACK
DATA OUT 1
NO ACK
DATA OUT N
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
R/W
ACK
ACK
DEV SEL *
START
SEQUENTIAL
RANDOM
READ
NO ACK
STOP
SEQUENTIAL
CURRENT
READ
ACK
DEV SEL *
START
START
DEV SEL *
ACK
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI00794C
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
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ST24/25C04, ST24/25W04
ORDERING INFORMATION SCHEME
Example:
ST24C04
Operating Voltage
ST24C04
1
TR
Range
3V to 5.5V
Standard
ST24W04
3V to 5.5V
Hardware Write Control
ST25C04
2.5V to 5.5V
Standard
ST25W04
2.5V to 5.5V
Hardware Write Control
Package
Notes:
M
B
PSDIP8
0.25mm Frame
M
SO8 150mil Width
Temperature Range
1
0 to 70 °C
5
–20 to 85 °C
6
–40 to 85 °C
3*
–40 to 125 °C
Option
TR
Tape & Reel
Packing
3 * Temperature range on special request only.
Parts are shipped with the memory content set at all "1’s" (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) or for further information on any
aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
13/16
ST24/25C04, ST24/25W04
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Symb
Typ
inches
Min
Max
A
3.90
A1
Min
Max
5.90
0.154
0.232
0.49
–
0.019
–
A2
3.30
5.30
0.130
0.209
B
0.36
0.56
0.014
0.022
B1
1.15
1.65
0.045
0.065
C
0.20
0.36
0.008
0.014
D
9.20
9.90
0.362
0.390
E
7.62
–
–
6.00
6.70
–
–
eA
7.80
eB
Typ
–
–
0.236
0.264
–
–
–
0.307
–
–
10.00
–
0.394
L
3.00
3.80
0.118
0.150
N
8
E1
e1
2.54
0.100
8
A2
A1
B
0.300
A
L
e1
eA
eB
B1
D
C
N
E1
E
1
PSDIP-a
Drawing is not to scale
14/16
ST24/25C04, ST24/25W04
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Symb
Typ
inches
Min
Max
A
1.35
A1
Min
Max
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
1.27
Typ
0.050
8
CP
0.10
0.004
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Drawing is not to scale
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ST24/25C04, ST24/25W04
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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