Freescale Semiconductor Data Sheet: Technical Data Document Number: MKMxxZxxCxx5 Rev. 7, 01/2014 MKMxxZxxCxx5 KM Family Supports the following: MKM14Z64CHH5, MKM14Z128CHH5, MKM33Z64CLH5, MKM33Z128CLH5, MKM33Z64CLL5, MKM33Z128CLL5, MKM34Z128CLL5 Features • Operating Characteristics – Voltage range: 1.71 V to 3.6 V (when Analog Front End (AFE) is not used) – Voltage range: 2.7 V to 3.6 V (when Analog Front End (AFE) is used) – iRTC battery supply voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40°C to 85°C • Performance – Up to 50 MHz ARM Cortex-M0+ core delivering 0.95 Dhrystone MIPS per MHz • Memories and memory interfaces – 128/64 KB program flash memory. There is no FlexMemory on these devices – 16 KB of single access RAM • Clocks – 1 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator • System peripherals – Multiple low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 4-channel DMA controller, supporting up to 64 request sources – External watchdog monitor – Robust watchdog monitor – Low-leakage wakeup unit – Asynchronous wakeup unit – Peripheral Crossbar (allows internal signals to be connected to other on-chip modules) • Security and integrity modules – Hardware programmable CRC module to support fast cyclic redundancy checks – Hardware random-number generator – 128-bit unique identification (ID) number per chip • Human-machine interface – Segment LCD controller supporting up to 36 frontplanes and 8 backplanes or 40 frontplanes and 4 backplanes – General-purpose input/output which can acts as Rapid GPIO (single cycle access) • Analog modules – 16-bit SAR ADC – 24-bit Analog Front End comprising of 24-bit Sigma Delta ADCs (after averaging) – Programmable Gain Amplifier (PGA with gains upto 32) – Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input – 1.2V Voltage reference • Timers – 4 channel Quad Timer with 16-bit counters – Periodic interrupt timers – 16-bit low-power timer – Independent Real Time Clock with calendaring and compensation • Communication interfaces – One SPI module with FIFO support (supports 5V AMR operation) – One SPI module without FIFO (no AMR operation) – Two I2C modules with SMBus support – Two UART modules with ISO7816 support and Two UART without ISO 7816 support – Any one SCI can be used for IrDA operation. 5V AMR support on one SCI. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2014 Freescale Semiconductor, Inc. KM Family Data Sheet, Rev. 7, 01/2014. 2 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................4 5.3 Switching specifications.....................................................18 1.1 Determining valid order-able parts....................................4 5.3.1 Device clock specifications...................................18 2 Part identification......................................................................4 5.3.2 General switching specifications...........................18 2.1 Description.........................................................................4 5.4 Thermal specifications.......................................................19 2.2 Format...............................................................................4 5.4.1 Thermal operating requirements...........................19 2.3 Fields.................................................................................4 5.4.2 Thermal attributes.................................................19 2.4 Example............................................................................5 6 Peripheral operating requirements and behaviors....................20 3 Terminology and guidelines......................................................5 6.1 Core modules....................................................................21 3.1 Definition: Operating requirement......................................5 6.1.1 Single Wire Debug (SWD)....................................21 3.2 Definition: Operating behavior...........................................6 6.1.2 Analog Front End (AFE)........................................21 3.3 Definition: Attribute............................................................6 6.2 Clock modules...................................................................22 3.4 Definition: Rating...............................................................7 6.2.1 MCG specifications...............................................22 3.5 Result of exceeding a rating..............................................7 6.2.2 Oscillator electrical specifications.........................24 3.6 Relationship between ratings and operating 6.2.3 32 kHz oscillator electrical characteristics.............27 requirements......................................................................7 3.7 Guidelines for ratings and operating requirements............8 3.8 Definition: Typical value.....................................................8 6.3 Memories and memory interfaces.....................................28 6.3.1 Flash electrical specifications................................28 6.4 Analog...............................................................................29 3.9 Typical value conditions....................................................9 6.4.1 ADC electrical specifications.................................29 4 Ratings......................................................................................10 6.4.2 CMP and 6-bit DAC electrical specifications.........33 4.1 Thermal handling ratings...................................................10 6.4.3 Voltage reference electrical specifications............35 4.2 Moisture handling ratings..................................................10 6.4.4 AFE electrical specifications.................................36 4.3 ESD handling ratings.........................................................10 6.5 Timers................................................................................40 4.4 Voltage and current operating ratings...............................11 6.6 Communication interfaces.................................................40 5 General.....................................................................................11 6.6.1 I2C switching specifications..................................40 5.1 AC electrical characteristics..............................................11 6.6.2 UART switching specifications..............................40 5.2 Nonswitching electrical specifications...............................11 6.6.3 SPI switching specifications..................................40 5.2.1 Voltage and current operating requirements.........11 6.7 Human-Machine Interfaces (HMI).....................................43 5.2.2 LVD and POR operating requirements.................12 5.2.3 Voltage and current operating behaviors..............13 7 Dimensions...............................................................................44 5.2.4 Power mode transition operating behaviors..........14 7.1 Obtaining package dimensions.........................................45 5.2.5 Power consumption operating behaviors..............15 8 Pinout........................................................................................45 5.2.6 EMC radiated emissions operating behaviors.......17 8.1 KM Signal multiplexing and pin assignments....................45 5.2.7 Designing with radiated emissions in mind...........17 8.2 KM Family Pinouts.............................................................48 5.2.8 Capacitance attributes..........................................18 9 Revision History........................................................................51 6.7.1 LCD electrical characteristics................................43 KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 3 Ordering parts 1 Ordering parts 1.1 Determining valid order-able parts Valid order-able part numbers are provided on the web. To determine the order-able part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: • MKM13Z64CHH5 • MKM14Z64CHH5 • MKM14Z128CHH5 • MKM32Z64CLH5 • MKM33Z64CLH5 • MKM33Z128CLH5 • MKM32Z64CLL5 • MKM33Z64CLL5 • MKM33Z128CLL5 • MKM34Z128CLL5 • MKM38Z128CLL5 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K M S R FFF T PP CC N KM Family Data Sheet, Rev. 7, 01/2014. 4 Freescale Semiconductor, Inc. Terminology and guidelines 2.3 Fields Following table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Pre-qualification (Proto) K Main family • K = Kinetis M Sub family • M1 = Metering only (No LCD support) • M3 = Metering with LCD support S Number of Sigma Delta (SD) ADC • • • • R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main FFF Program flash memory size • 64 = 64 KB • 128 = 128 KB T Temperature range (°C) • C = –40 to 85 PP Package identifier • HH = 44 LGA (5 mm x 5 mm) • LH = 64 LQFP (10 mm x 10 mm) • LL = 100 LQFP (14 mm x 14 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2 = 1 SD ADC with PGA and 1 SD ADC 3 = 2 SD ADC with PGA and 1 SD ADC 4 = 2 SD ADC with PGA and 2 SD ADC 8 = Same as '4'. 2.4 Example This is an example part number: • MKM34Z128CLL5 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 5 Terminology and guidelines 3.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF KM Family Data Sheet, Rev. 7, 01/2014. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. 1.2 Unit V 3.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 7 Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .) r Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) g lin nd Ha in rat n.) mi g( nd Ha g lin ing rat ax (m .) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. KM Family Data Sheet, Rev. 7, 01/2014. 8 Freescale Semiconductor, Inc. Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 9 Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Min. Max. Unit Notes Electrostatic discharge voltage, human body model (All pins except RESET pin) -4000 +4000 V 1 Electrostatic discharge voltage, human body model (RESET pin only) -2500 +2500 V 1 VCDM Electrostatic discharge voltage, charged-device model (for corner pins) -750 +750 V 2 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 3 VPESD Powered ESD voltage -6000 +6000 V Latch-up current at ambient temperature of 105°C -100 +100 mA VHBM ILAT Description 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. KM Family Data Sheet, Rev. 7, 01/2014. 10 Freescale Semiconductor, Inc. General 4.4 Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.6 V VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V Tamper input voltage –0.3 VBAT + 0.3 V Analog1, –0.3 VDD + 0.3 V –25 25 mA VDD – 0.3 VDD + 0.3 V –0.3 3.6 V VDTamper VAIO ID RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) VDDA Analog supply voltage VBAT RTC battery supply voltage 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference 5.2 Nonswitching electrical specifications KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 11 General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit Supply voltage when AFE is operational 2.7 3.6 V Supply voltage when AFE is NOT operational 1.71 3.6 V Analog supply voltage 2.7 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V -5 — mA • VIN < VSS-0.3V (Negative current injection) -3 — • VIN > VDD+0.3V (Positive current injection) — +3 -25 — — +25 VPOR_VBAT — VDD VDDA VBAT VIH VIL RTC battery supply voltage Input low voltage Input hysteresis IICDIO Digital pin negative DC injection current — single pin • VIN < VSS-0.3V IICcont Analog2, EXTAL, and XTAL pin DC injection current — single pin mA Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection VRFVBAT 1 Input high voltage VHYS IICAIO Notes VBAT voltage required to retain the VBAT register file mA V 1. VBAT always needs to be there for the chip to be operational. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 12 Freescale Semiconductor, Inc. General Table 2. VDD supply LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V — 80 — mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V — 60 — mV VHYSL Low-voltage inhibit reset/recover hysteresis — low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = 20 mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = 10 mA VDD – 0.5 — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = 5 mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = 2.5 mA VDD – 0.5 — V — 100 mA Notes Output high voltage — high-drive strength Output high voltage — low-drive strength IOHT Output high current total for all ports Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 13 General Table 4. Voltage and current operating behaviors (continued) Symbol VOL Description Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — 0.5 V • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — 0.5 V Notes Output low voltage — high-drive strength Output low voltage — low-drive strength IOLT Output low current total for all ports — 100 mA IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 30 60 kΩ 1, RPD Internal pulldown resistors 30 60 kΩ 2 1. Measured at Vinput = VSS 2. Measured at Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • • • • • CPU and system clocks = 50 MHz Bus clock = 25 MHz Flash clock = 25 MHz Temp: -40 °C, 25 °C, and 85 °C VDD: 1.71 V, 3.3 V, and 3.6 V Table 5. Power mode transition operating behaviors Symbol tPOR Description Min. Max. Unit Notes After a POR event, amount of time from the point VDD reaches 1.71 V to execute the first instruction across the operating temperature range of the chip. 563 659 μs 1 — 372 μs — 372 μs — 273 μs — 273 μs — 5.0 μs • VLLS0 → RUN • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • VLPS → RUN Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 14 Freescale Semiconductor, Inc. General Table 5. Power mode transition operating behaviors (continued) Symbol Description • STOP → RUN Min. Max. Unit — 5.0 μs Notes 1. Normal boot (FTFA_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Min. Typ. Max. Unit Notes — — See note mA 1 Run mode current — all peripheral clocks disabled, code executing from flash 2 • @ 3.0 V • 25 °C • -40 °C • 105 °C IDD_RUN — 6.17 7.1 mA — 6.39 6.7 mA — 6.93 8.3 mA Run mode current — all peripheral clocks enabled, code executing from flash 2 • @ 3.0 V • 25 °C • -40 °C • 105 °C IDD_WAIT IDD_WAIT IDD_VLPR IDD_VLPR Wait mode high frequency current at 3.0 V— all peripheral clocks disabled and Flash is not in low-power • 25 °C • -40 °C • 105 °C Wait mode high frequency current at 3.0 V— all peripheral clocks disabled and Flash disabled (put in low-power) • 25 °C • -40 °C • 105 °C Very-low-power run mode current at 3.0 V — all peripheral clocks disabled • 25 °C • -40 °C • 105 °C Very-low-power run mode current at 3.0 V — all peripheral clocks enabled • 25 °C • -40 °C • 105 °C — 8.24 10.4 mA — 8.26 9.8 mA — 9.00 11.5 mA 2 — 3.95 4.65 mA — 4.4 mA — 6 mA 2, 3 — 3.81 4.4 mA — 4.2 mA — 5.8 mA 4 — 248.8 500 μA — 245.30 470 μA — 535.40 1800 μA 5 — 343.4 530 μA — 336.62 500 μA — 626.18 2000 μA Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 15 General Table 6. Power consumption operating behaviors (continued) Symbol Description IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled • 25 °C • -40 °C • 105 °C IDD_STOP IDD_VLPS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VLLS0 IDD_VLLS0 IDD_VBAT Min. Stop mode current at 3.0 V • 25 °C • -40 °C • 105 °C Very-low-power stop mode current at 3.0 V • 25 °C • -40 °C • 105 °C Very low-leakage stop mode 3 current at 3.0 V • 25 °C • -40 °C • 105 °C Very low-leakage stop mode 2 current at 3.0 V • 25 °C • -40 °C • 105 °C Very low-leakage stop mode 1 current at 3.0 V • 25 °C • -40 °C • 105 °C Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled • 25 °C • -40 °C • 105 °C Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled • 25 °C • -40 °C • 105 °C Average current with RTC and 32 kHz disabled at 3.0 V and VDD is OFF • 25 °C • -40 °C • 105 °C Typ. Max. Unit Notes 6 — 162 350 μA — 158.50 330 μA — 446.94 1700 μA — 311.90 730 μA — 364 700 μA — 645.13 2250 μA — 8.56 46 μA — 44 μA — 1500 μA 3.5 μA — 3.3 μA — 85 μA 2.6 μA — 2.5 μA — 59.5 μA 1.7 μA — 1.6 μA — 38.8 μA 0.67 μA — 0.64 μA — 38 μA 0.76 μA — 0.72 μA — 38.4 μA 1 μA — 0.95 μA — 15 μA — — — — — — 1.98 1.24 0.89 0.35 0.472 0.3 Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 16 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VBAT Average current when VDD is OFF and LFSR and Tamper clocks set to 2 Hz. • @ 3.0 V • 25 °C • -40 °C • 105 °C Typ. Max. Unit Notes 8, 9 — 1.3 7 3 μA 2.5 μA 16 μA 1. See AFE specification for IDDA. 2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FBE mode. All peripheral clocks disabled. 3. Should be reduced by 500 μA. 4. 2 MHz core, system, bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing while (1) loop from flash. 5. 2 MHz core, system and bus clock, and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing while (1) loop from flash. 6. 2 MHz core, system and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. No flash accesses; some activity on DMA & RAM assumed. 7. Current consumption will vary with number of CPU accesses done and is dependent on the frequency of the accesses and frequency of bus clock. Number of CPU accesses should be optimized to get optimal current value. 8. Includes 32 kHz oscillator current and RTC operation. 9. An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in all conditions. There is no internal power switch in RTC. 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15–50 14 dBμV VRE2 Radiated emissions voltage, band 2 50–150 16 dBμV VRE3 Radiated emissions voltage, band 3 150–500 12 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 5 dBμV IEC level 0.15–1000 M — VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 50 MHz, fBUS = 25 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 17 General 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF Input capacitance: fast digital pins — 9 pF CIN_D_io60 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode fSYS System and core clock 50 MHz fBUS Bus clock 25 MHz Flash clock 25 MHz 6.5 MHz fFLASH fAFE AFE Modulator clock VLPR mode1 fSYS System and core clock 2 MHz fBUS Bus clock 1 MHz 1 MHz 1.6 MHz fFLASH fAFE Flash clock AFE Modulator clock2 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 2. AFE working in low-power mode. KM Family Data Sheet, Rev. 7, 01/2014. 18 Freescale Semiconductor, Inc. General 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 GPIO pin interrupt pulse width (digital glitch filter disabled) — Asynchronous path 16 — ns 2 External reset pulse width (digital glitch filter disabled) 100 — ns 2 Port rise and fall time—Low (All pins) and high drive (only PTC2) strength • Slew disabled • 1.71 ≤ VDD ≤ 2.7 V 3 — 8 ns — 5 ns — 27 ns — 16 ns • 2.7 ≤ VDD ≤ 3.6 V • Slew enabled • 1.71 ≤ VDD ≤ 2.7 V • 2.7 ≤ VDD ≤ 3.6 V 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. Only PTC2 has high drive capability and load is 75 pF, other pins load (low drive) is 25 pF. 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 105 °C TA Ambient temperature –40 85 °C KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 19 Peripheral operating requirements and behaviors 5.4.2 Thermal attributes Board type Symbol Description 44 LGA Unit Notes Single-layer (1s) RθJA Thermal 63 resistance, junction to ambient (natural convection) 95 °C/W 1 Four-layer (2s2p) RθJA Thermal 50 resistance, junction to ambient (natural convection) 50 °C/W 1 Single-layer (1s) RθJMA Thermal 53 resistance, junction to ambient (200 ft./ min. air speed) 79 °C/W 1 Four-layer (2s2p) RθJMA Thermal 44 resistance, junction to ambient (200 ft./ min. air speed) 45 °C/W 1 — RθJB Thermal resistance, junction to board 36 35 °C/W 2 — RθJC Thermal resistance, junction to case 18 28 °C/W 3 — ΨJT Thermal 3 characterization parameter, junction to package top outside center (natural convection) 4 °C/W 4 1. 2. 3. 4. 100 LQFP Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors KM Family Data Sheet, Rev. 7, 01/2014. 20 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Single Wire Debug (SWD) Table 12. SWD switching characteristics at 2.7 V (2.7-3.6 V) Symbol Description Value Unit Notes SWD CLK Frequency of SWD operation 20 MHz 1 Inputs, tSUI Data setup time 5 ns 1 inputs,tHI Data hold time 0 ns 1 after clock edge, tDVO Data valid Time 32 ns 1 tHO Data Valid Hold 0 ns 1 1. Input transition assumed =1 ns. Output transition assumed = 50 pf. Table 13. Switching characteristics at 1.7 V (1.7-3.6 V) Symbol Description Value Unit SWD CLK Frequency of SWD operation 18 MHz Inputs, tSUI Data setup time 4.7 ns inputs,tHI Data hold time 0 ns after clock edge, tDVO Data valid Time 49.4 ns tHO Data Valid Hold 0 ns Notes 2 1. Frequency of SWD clock (18 Mhz) is applicable only in case the input setup time of the device outside is not more than 6.15 ns, else the frequency of SWD clock would need to be lowered. 6.1.2 Analog Front End (AFE) AFE switching characteristics at (2.7 V-3.6 V) Case1: Clock is coming In and Data is also coming In (XBAR ports timed with respect to the XBAR ports timed with respect to AFE clock defined at pad ptb[7] and pte[3]) Table 14. AFE switching characteristics (2.7 V-3.6 V) Symbol Description Value Unit Notes AFE CLK Frequency of operation 10 MHz 1 Inputs, tSUI Data setup time 5 ns 1 inputs,tHI Data hold time 0 ns 1 1. Input Transition: 1ns. Output Load: 50 pf. KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 21 Peripheral operating requirements and behaviors Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to generated clock defined at the XBAR out ports) Table 15. AFE switching characteristics (2.7V-3.6V) Symbol Description Value Unit AFE CLK Frequency of operation 6.2 MHz Inputs, tSUI Data setup time 36 ns inputs,tHI Data hold time 0 ns Notes AFE switching characteristics at (1.7 V-3.6 V) Case1: Clock is coming In and Data is also coming In ( XBAR ports timed with respect to AFE clock defined at pad ptb[7] and pte[3]) Table 16. AFE switching characteristics (1.7 V-3.6 V) Symbol Description Value Unit AFE CLK Frequency of operation 10 MHz Inputs, tSUI Data setup time 5.1 ns inputs,tHI Data hold time 0 ns Notes Case 2: Clock is going Out and Data is coming In ( XBAR ports timed with respect to generated clock defined at XBAR out ports) Table 17. AFE switching characteristics (1.7 V-3.6 V) Symbol Description Value Unit AFE CLK Frequency of operation 6.2 MHz Inputs, tSUI Data setup time 54 ns inputs,tHI Data hold time 0 ns Notes 6.2 Clock modules 6.2.1 MCG specifications Table 18. MCG specifications Symbol fints_ft Description Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C Min. Typ. Max. Unit — 32.768 — kHz Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Δfints_t fints_t Description Total deviation of internal reference frequency (slow clock) over voltage and temperature Internal reference frequency (slow clock) — user trimmed Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Min. Typ. Max. Unit Notes — ±4 ± 15 % 31.25 — 33.4234 kHz — ± 0.3 ± 0.6 %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — %fdco 1 fintf_ft Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C Δfintf_t Total deviation of internal reference frequency (fast clock) over voltage and temperature — Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C fintf_t 4 MHz ± 10 ± 15 % 3 — 5 MHz floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 20 20.97 22 MHz 40 41.94 45 MHz 60 62.91 67 MHz 80 83.89 90 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz FLL period jitter — 70 140 ps 7 FLL target frequency acquisition time — — 1 ms 8 FLL fdco DCO output frequency range Low-range (DRS=00) 2, 3 640 × fints_t Mid-range (DRS=01) 1280 × fints_t Mid-high range (DRS=10) 1920 × fints_t High-range (DRS=11) 2560 × fints_t fdco_t_DMX32 DCO output frequency Low-range (DRS=00) 4, 5, 6 732 × fints_t Mid-range (DRS=01) 1464 × fints_t Mid-high range (DRS=10) 2197 × fints_t High-range (DRS=11) 2929 × fints_t Jcyc_fll tfll_acquire PLL Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description fvco VCO operating frequency Ipll PLL operating current • IO 3.3 V current • Max core voltage current fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) Min. Typ. Max. Unit 11.71875 12.288 14.648437 5 MHz — 300 — µA 31.25 32.768 39.0625 kHz Notes 9 100 10 • fvco = 12 MHz 700 ps ± 2.98 % Dlock Lock entry frequency tolerance ± 1.49 — Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 11 12 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. Chip max freq is 50 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be configured. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. Chip max freq is 50 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be configured. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. Will be updated later 12. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.2.2 Oscillator electrical specifications 6.2.2.1 Oscillator DC electrical specifications Table 19. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description IDDOSC Supply current — low-power mode (HGO=0) IDDOSC Min. Typ. Max. Unit Notes 1 • 32 kHz — 500 — nA • 1 MHz — 200 — μA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high-gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 1 MHz — 300 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 — — Capacitance of EXTAL 247 • Die level (100 LQFP) • Package level (100 LQFP) Capacitance of XTAL pF — 265 • Die level (100 LQFP) • Package level (100 LQFP) RF 0.495 ff — 0.495 ff pF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ 2, 4 Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol RS Description Min. Typ. Max. Unit Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 6.6 — kΩ — 3.3 — kΩ — 0 — kΩ — 0 — kΩ — 0 — kΩ — 0 — kΩ — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V Notes Series resistor — high-frequency, high-gain mode (HGO=1) • 1 MHz resonator • 2 MHz resonator • 4 MHz resonator • 8 MHz resonator • 16 MHz resonator • 20 MHz resonator • 32 MHz resonator 5 Vpp 1. 2. 3. 4. 5. VDD=3.3 V, Temperature =25 °C See crystal or resonator manufacturer's recommendation Cx and Cy can be provided by using either integrated capacitors or external components. When low-power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other device. 6.2.2.2 Symbol Oscillator frequency specifications Table 20. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — highfrequency mode (low range) (MCG_C2[RANGE]=01) 1 — 8 MHz Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 20. Oscillator frequency specifications (continued) Symbol Description Min. Typ. Max. Unit fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.2.3 32 kHz oscillator electrical characteristics 6.2.3.1 32 kHz oscillator DC electrical specifications Table 21. 32kHz oscillator DC electrical specifications Symbol Description Min. VBAT Supply voltage Typ. Max. Unit 1.71 — 3.6 V Internal feedback resistor — 100 — MΩ Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation — 0.6 — V RF 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.2.3.2 Symbol fosc_lo 32 kHz oscillator frequency specifications Table 22. 32 kHz oscillator frequency specifications Description Oscillator crystal Min. Typ. Max. Unit — 32.768 — kHz Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors Table 22. 32 kHz oscillator frequency specifications (continued) Symbol tstart Description Crystal start-up time vec_extal32 Externally provided input clock amplitude Min. Typ. Max. Unit Notes — 1000 — ms 1 700 — VBAT mV 2,3 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3 Memories and memory interfaces 6.3.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.3.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 23. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time — 7.5 18 μs thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 6.3.1.2 Flash timing specifications — commands Table 24. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes tpgm4 Program Longword execution time — 65 145 μs tersscr Erase Flash Sector execution time — 14 114 ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 88 650 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tpgmonce 2 1 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 6.3.1.3 Flash high voltage current behaviors Table 25. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.3.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 26. NVM reliability specifications Description Typ.1 Max. Unit 50 — years 20 100 — years 10 K 50 K — cycles Min. Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k Data retention after up to 1 K cycles nnvmcycp Cycling endurance 5 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 6.4 Analog 6.4.1 ADC electrical specifications All ADC channels meet the 12-bit single-ended accuracy specifications. KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors 6.4.1.1 16-bit ADC operating conditions Table 27. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage VREFL — VREFH V CADIN Input capacitance • 16-bit mode — 8 10 pF • 8-bit / 10-bit / 12-bit modes — 4 5 — 2 5 RADIN RAS Input series resistance Notes kΩ Analog source resistance (external) 12-bit modes fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion clock frequency ≤ 12-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 12-bit modes No ADC hardware averaging 3 5 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode No ADC hardware averaging 5 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. KM Family Data Sheet, Rev. 7, 01/2014. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection Z AS R AS ADC SAR ENGINE R ADIN V ADIN C AS V AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 2. ADC input impedance equivalency diagram 6.4.1.2 16-bit ADC electrical characteristics Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE DNL INL Conditions1. Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 –1.1 to +1.9 • <12-bit modes — ±0.2 • 12-bit modes — ±1.0 • <12-bit modes — ±0.5 Integral nonlinearity –0.3 to 0.5 –2.7 to +1.9 –0.7 to +0.5 Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EFS Full-scale error EQ Quantization error ENOB Conditions1. Min. Typ.2 Max. Unit Notes • 12-bit modes — –4 –5.4 LSB4 • <12-bit modes — –1.4 –1.8 VADIN = VDDA5 • 16-bit modes — –1 to 0 — • 12-bit modes — — ±0.5 Effective number 16-bit single-ended mode of bits • Avg = 32 • Avg = 4 SINAD THD SFDR EIL Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit single-ended mode Spurious free dynamic range • Avg = 32 LSB4 6 12.8 14.5 — bits 11.9 13.8 — bits 12.2 13.9 — bits 11.4 13.1 — bits 6.02 × ENOB + 1.76 dB 7 — -94 — dB — -85 — dB 16-bit single-ended mode • Avg = 32 7 82 95 — dB 78 90 — dB Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. KM Family Data Sheet, Rev. 7, 01/2014. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 8. ADC conversion clock < 3 MHz Figure 3. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.4.2 CMP and 6-bit DAC electrical specifications Table 29. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.3 — VDD V VAIO Analog input offset voltage — — 20 mV • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV VH Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDHS Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors Table 29. Comparator and 6-bit DAC electrical specifications (continued) Symbol tDLS IDAC6b Description Min. Typ. Max. Unit Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 0.06 HYSTCTR Setting CM P Hystereris (V) 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 4. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) KM Family Data Sheet, Rev. 7, 01/2014. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 5. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 6.4.3 Voltage reference electrical specifications Table 30. 1.2 VREF full-range operating requirements Symbol VDDA Description Min. Max. Unit Supply voltage 1.711 3.6 V −40 85 °C TA Temperature CL Output load capacitance 100 nF Notes 2, 3 1. AFE is enabled. 2. CL must be connected between VREFH and VREFL. 3. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. Table 31. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit VREFH Voltage reference output with factory trim at nominal VDDA and temperature = 25 °C 1.1915 1.2 1.2027 V VREFH Voltage reference output with — factory trim 1.1584 — 1.2376 V Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors Table 31. VREF full-range operating behaviors (continued) Symbol Description Min. Typ. Max. Unit VREFH Voltage reference output — user trim 1.178 — 1.202 V VREFL Voltage reference output 0.38 0.4 0.42 V Vstep Voltage reference trim step — 0.5 — mV Vtdrift Temperature drift (Vmax - Vmin across the full temperature range) — 5 — mV Ac Aging coefficient — — 400 uV/yr Ibg Bandgap only current — — 80 µA 2 Ilp Low-power buffer current — — 0.19 µA 2 Ihp High-power buffer current — — 0.5 mA 2 VREF buffer current — — 1 mA 3 mV 2, 4 ILOAD ΔVLOAD Load regulation • current = + 1.0 mA — 2 • current = - 1.0 mA 1. 2. 3. 4. Notes 1 — 5 Tstup Buffer startup time — — 20 ms Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 0.5 — mV 2 For temp range -40 °C to 105 °C, this value is 15 mV See the chip's Reference Manual for the appropriate settings of VREF Status and Control register. See the chip's Reference Manual for the appropriate settings of SIM Miscellaneous Control Register. Load regulation voltage is the difference between VREFH voltage with no load vs. voltage with defined load. Table 32. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 50 °C Notes Table 33. VREF limited-range operating behaviours Symbol Description Min. Max. Unit VREFH Voltage reference output with factory trim 1.173 1.225 V VREFL Voltage reference output 0.38 0.42 V Notes 6.4.4 AFE electrical specifications KM Family Data Sheet, Rev. 7, 01/2014. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.4.1 ΣΔ ADC + PGA specifications Symbo Description l fNyq VCM VINdiff SNR Input bandwidth Table 34. ΣΔ ADC + PGA specifications Conditions Min Typ1 Max Unit Normal Mode 1.5 1.5 1.5 kHz Low-Power Mode 1.5 1.5 1.5 Input Common Mode Reference Differential input range Signal to Noise Ratio 0 0.8 V Gain = 1 (PGA ON/OFF)2 +/- 500 mV Gain = 2 +/- 250 mV Gain = 4 +/- 125 mV Gain = 8 +/- 62 mV Gain = 16 +/- 31 mV Gain = 32 +/- 15 mV Normal Mode • fIN=50Hz; gain=01, common mode=0V, Vpp=1000mV (full range diff.) • fIN=50Hz; gain=02, common mode=0V, Vpp= 500mV (differential ended ) • fIN=50Hz; gain=04, common mode=0V, Vpp= 250mV (differential ended ) • fIN=50Hz; gain=08, common mode=0V, Vpp= 125mV (differential ended ) • fIN=50Hz; gain=16, common mode=0V, Vpp= 62mV (differential ended ) • fIN=50Hz; gain=32, common mode=0V, Vpp= 31mV (differential ended ) Low-Power Mode • fIN=50Hz; gain=01, common mode=0V, Vpp=1000mV (full range diff.) • fIN=50Hz; gain=02, common mode=0V, Vpp= 500mV (differential ended ) • fIN=50Hz; gain=04, common mode=0V, Vpp= 250mV (differential ended ) • fIN=50Hz; gain=08, common mode=0V, Vpp= 125mV (differential ended ) • fIN=50Hz; gain=16, common mode=0V, Vpp= 62mV (differential ended ) • fIN=50Hz; gain=32, common mode=0V, Vpp= 31mV (differential ended ) Notes dB 90 92 88 90 82 86 76 82 70 78 64 74 82 82 76 78 70 74 64 70 58 66 52 62 dB Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors Table 34. ΣΔ ADC + PGA specifications (continued) Symbo Description l Conditions Min SINAD Signal-to-Noise + Distortion Normal Mode Ratio • fIN=50Hz; gain=01, common mode=0V, Vpp=500mV (differential ended ) Eoffset Offset Error ΔOffset Offset Temperature Drift3 Temp ΔGainTe Gain Temperate Drift - Gain error caused by mp temperature drifts4 fMCLK Crosstalk (with the input of the affected channel grounded) dB dB 70 70 Gain=01, Vpp=1000 mV (full range diff.) +/- 5 mV Gain=01, Vpp=1000mV (full range diff.) +/- 25 ppm/oC +/- 75 ppm/oC • Gain=01, Vpp=500mV (differential ended ) • Gain=32, Vpp=15mV (differential ended ) 60 Gain=01, Vid = 500 mV, fIN = 50 Hz dB -100 dB 0.03 6.5 MHz 0.03 1.6 Normal Mode (fMCLK = 6.144 MHz, OSR= 2048) Low-Power Mode (fMCLK = 0.768MHz, OSR= 256) IDDA_AD Current Consumption by ADC (each chanel) C Notes 74 • fIN=50Hz; gain=01, common mode=0V, Vid=100 mV • fIN=50Hz; gain=32, common mode=0V, Vid=100 mV Modulator Clock Frequency Normal Mode Range Low-Power Mode IDDA_PG Current consumption by PGA (each channel) A Unit dB PSRRA AC Power Supply Rejection Gain=01, VCC = 3V ± 100mV, fIN = Ratio 50 Hz C XT Max 78 Low-Power Mode • fIN=50Hz; gain=01, common mode=0V, Vpp=500mV (differential ended ) CMMR Common Mode Rejection Ratio Typ1 Normal Mode (fMCLK = 6.144 MHz, OSR= 2048) Low-Power Mode (fMCLK = 0.768MHz, OSR= 256) 2.6 mA 5 0 1.4 mA 0.5 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fMCLK = 6.144 MHz, OSR = 2048 for Normal mode and fMCLK = 768 kHz, OSR = 256 for Low-Power Mode unless otherwise stated. Typical values are for reference only and are not tested in production. 2. The full-scale input range in single-ended mode is 0.5Vpp 3. Represents combined offset temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks; Defined by shorting both differential inputs to ground. 4. Represents combined gain temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks. 5. PGA is disabled in low-power modes. KM Family Data Sheet, Rev. 7, 01/2014. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.4.2 ΣΔ ADC Standalone specifications Table 35. ΣΔ ADC standalone specifications Symbo Description l fNyq VCM VINdiff SNR Input bandwidth Conditions Min Typ1 Max Unit Normal Mode 1.5 1.5 1.5 kHz Low-Power Mode 1.5 1.5 1.5 Input Common Mode Reference Input range Signal to Noise Ratio 0 0.8 V Differential +/- 500 mV Single Ended +/- 250 mV Normal Mode • fIN=50Hz; common mode=0V, Vpp= 500mV (differential ended ) • fIN=50Hz; common mode=0V, Vpp= 500mV (full range se.) Notes dB 88 90 76 78 Low-Power Mode • fIN=50Hz; common mode=0V, Vpp=500mV (diff.) • fIN=50Hz; common mode=0V, Vpp=500mV (full range se.) ΔGainTe Gain Temperate Drift - Gain error caused by mp temperature drifts 2 • Gain bypassed Vpp = 500 mV (differential) • PGA bypassed Vpp = 500 mV (differential), VCM = 0 V 55 ppm/oC ΔOffset Offset Temperate Drift Offset error caused by Temp temperature drifts 3 • Gain bypassed Vpp = 500 mV (differential), VCM = 0 V 30 ppm/oC SINAD Signal-to-Noise + Distortion Normal Mode Ratio • fIN=50Hz; common mode=0V, Vpp= 500mV (diff.) • fIN=50Hz; common mode=0V, Vpp= 500mV (full range se.) dB 80 74 Low-Power Mode • fIN=50Hz; common mode=0V, Vpp=500mV (diff.) • fIN=50Hz; common mode=0V, Vpp=500mV (full range se.) CMMR Common Mode Rejection Ratio • fIN=50Hz; common mode=0V, Vid=100 mV 90 dB PSRRA AC Power Supply Rejection Gain=01, VCC = 3V ± 100mV, fIN = Ratio 50 Hz C 60 dB XT fMCLK Crosstalk Gain=01, Vid = 500 mV, fIN = 50 Hz Modulator Clock Frequency Normal Mode Range Low-Power Mode IDDA_AD Current Consumption by ADC (each channel) C -100 dB 0.03 6.5 MHz 0.03 1.6 Normal Mode (fMCLK = 6.144 MHz, OSR= 2048) Low-Power Mode (fMCLK = 0.768MHz, OSR= 256) 1.4 mA 0.5 KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fMCLK = 6.144 MHz, OSR = 2048 for Normal mode and fMCLK = 768 kHz, OSR = 256 for Low-Power Mode unless otherwise stated. Typical values are for reference only and are not tested in production. 2. Represent combined gain temperature drift of the SD ADC, and Internal 1.2 VREF blocks. 3. Represent combined offset temperature drift of the SD ADC, and Internal 1.2 VREF blocks; Defined by shorting both differential inputs to ground. 6.4.4.3 External modulator interface The external modulator interface on this device comprises of a Clock signal and 1-bit data signal. Depending on the modulator device being used the interface works as follows: • Clock supplied to external modulator which drives data on rising edge and the KM device captures it on falling edge or next rising edge. • Clock and data are supplied by external modulator and KM device can sample it on falling edge or next rising edge. Depending on control bit in AFE, the sampling edge is changed. 6.5 Timers See General switching specifications. 6.6 Communication interfaces 6.6.1 I2C switching specifications See General switching specifications. 6.6.2 UART switching specifications See General switching specifications. KM Family Data Sheet, Rev. 7, 01/2014. 40 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.3 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following table provides some reference values to be met on SoC. Table 36. SPI switching characteristics at 2.7 V ( 2.7 - 3.6) Description Min. Max. Unit Notes Frequency of operation (Fsys) — 50 MHz 1 SCK frequency • Master • Slave 2 12.5 MHz 12.5 Mhz SCK Duty Cycle 50% — — Data Setup Time (inputs, tSUI) • Master • Slave ns 25 3 Input Data Hold Time (inputs, tHI) • Master • Slave ns 0 1 Data hold time (outputs, tHO) • Master • Slave ns 0 0 Data Valid Out Time (after SCK edge, tDVO) • Master • Slave Rise time input • Master • Slave 3 ns 13 28 ns 1 1 Fall time input • Master • Slave ns 1 1 Rise time output • Master • Slave ns 8.9 8.9 Fall time output • Master • Slave ns 7.8 7.8 1. SPI modules will work on core clock. 2. Fsys/(Max Divider Value from registers) 3. FSYS/2 in Master mode and FSYS/4 in Slave mode. FSYS/4 in Master as well as Slave Modes, where FSYS=50Mhz NOTE The values assumed for input transition and output load are: Input transition = 1 ns Output load = 50 pF Table 37. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) Description Frequency of operation (Fsys) Min. Max. Unit — 50 MHz Notes Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 41 Peripheral operating requirements and behaviors Table 37. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) (continued) Description Min. Max. Unit 9 MHz 9 Mhz — — SCK frequency • Master • Slave SCK Duty Cycle 50% Data Setup Time (inputs, tSUI) • Master • Slave Input Data Hold Time (inputs, tHI) • Master • Slave Data hold time (outputs, tHO) • Master • Slave Data Valid Out Time (tDVO) • Master • Slave Rise time input • Master • Slave Notes ns 42 3.5 ns 0 1 ns -3 0 ns 16 1 44 ns 1 1 Fall time input • Master • Slave ns 1 1 Rise time output • Master • Slave ns 14.4 14.4 Fall time output • Master • Slave ns 12.4 12.4 1. SCK frequency of 9 Mhz is applicable only in the case that the input setup time of the device outside is not more than 11.5 ns, else the frequency would need to be lowered. The following table represents SPI Switching specification in OD cells Table 38. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) Description Data Setup Time (inputs, tSUI) • Master • Slave Input Data Hold Time (inputs, tHI) • Master • Slave Data hold time (outputs, tHO) • Master • Slave Data Valid Out Time (tDVO) • Master • Slave Min. Max. 51 Unit Notes ns 4 0 ns 1 -15 ns 0 61 ns 93 Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 42 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 38. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) (continued) Description Min. Rise time input • Master • Slave Max. Unit Notes ns 1 1 Fall time input • Master • Slave ns 1 1 Rise time output • Master • Slave ns 30.4 30.4 Fall time output • Master • Slave ns 33.5 29.0 Table 39. SPI switching characteristics at 2.7 V ( 2.7 - 3.6) Description Min. Data Setup Time (inputs, tSUI) • Master • Slave 29 0 0 Fall time output • Master • Slave ns ns ns 0 Data Valid Out Time (after SCK edge, tDVO) • Master • Slave Rise time output • Master • Slave Notes 1 Data hold time (outputs, tHO) • Master • Slave Fall time input • Master • Slave Unit 4 Input Data Hold Time (inputs, tHI) • Master • Slave Rise time input • Master • Slave Max. 49 ns 49 1 ns 1 1 ns 1 17.3 ns 17.3 16.6 ns 16.0 6.7 Human-Machine Interfaces (HMI) KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 43 Dimensions 6.7.1 LCD electrical characteristics Table 40. LCD electricals Symbol Description Min. Typ. Max. Unit Notes fFrame LCD frame frequency 28 30 58 Hz CLCD LCD charge pump capacitance — nominal value — 100 — nF 1 CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1 CGlass LCD glass capacitance — 2000 8000 pF 2 VIREG VIREG 3 • HREFSEL=0, RVTRIM=1111 — 1.11 — V • HREFSEL=0, RVTRIM=1000 — 1.01 — V • HREFSEL=0, RVTRIM=0000 — 0.91 — V ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG IVIREG VIREG current adder — RVEN = 1 — 1 — µA IRBIAS RBIAS current adder — 15 — µA — 3 — µA 2.0 − 5% 2.0 — V 3.0 − 5% 3.0 — V • LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF) 4 • LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) VLL2 VLL2 voltage • HREFSEL = 0 VLL3 VLL3 voltage 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V. 4. 2000 pF load LCD, 32 Hz frame frequency. NOTE KM family devices have a 1/3 bias controller that works with a 1/3 bias LCD glass. To avoid ghosting, the LCD OFF threshold should be greater than VLL1 level. If the LCD glass has an OFF threshold less than VLL1 level, use the internal VREG mode and generate VLL1 internally using RVTRIM option. This can reduce VLL1 level to allow for a lower OFF threshold LCD glass. 7 Dimensions KM Family Data Sheet, Rev. 7, 01/2014. 44 Freescale Semiconductor, Inc. Pinout 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 44-pin LGA 98ASA00239D 64-pin LQFP 98ASS23234W 100-pin LQFP 98ASS23308W 8 Pinout NOTE VSS also connects to flag on 44 LGA. 8.1 KM Signal multiplexing and pin assignments 100 QFP 64 QFP 44 LGA DEFAULT ALT0 ALT1 ALT2 1 1 — Disabled LCD23 PTA0 2 2 — Disabled LCD24 PTA1 3 3 — Disabled LCD25 PTA2 4 — — Disabled LCD26 PTA3 5 4 1 NMI_B LCD27 PTA4 LLWU_P15 6 5 2 Disabled LCD28 PTA5 CMP0OUT 7 6 3 Disabled LCD29 PTA6 XBAR_IN0 8 7 4 Disabled LCD30 PTA7 XBAR_OUT0 9 — — Disabled LCD31 PTB0 10 8 5 VDD VDD 11 9 6 VSS VSS 12 — — Disabled LCD32 PTB1 13 — — Disabled LCD33 PTB2 14 — — Disabled LCD34 PTB3 15 — — Disabled LCD35 PTB4 16 — — Disabled LCD36 PTB5 17 — — Disabled LCD37/ CMP1P0 PTB6 ALT3 ALT4 ALT5 ALT6 ALT7 NMI_B LLWU_P14 KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 45 Pinout 100 QFP 64 QFP 44 LGA DEFAULT ALT0 18 10 — Disabled LCD38 PTB7 AFE_CLK 19 11 — Disabled LCD39 PTC0 UART3_RTS 20 12 — Disabled LCD40/ CMP1P1 PTC1 UART3_CTS 21 13 — Disabled LCD41 PTC2 UART3_TxD XBAR_OUT1 22 14 — Disabled LCD42/ CMP0P3 PTC3 UART3_RxD LLWU_P13 23 — — Disabled LCD43 PTC4 24 15 7 VBAT VBAT 25 16 8 XTAL32K XTAL32K 26 17 9 EXTAL32K EXTAL32K 27 18 10 VSS VSS 28 — — TAMPER2 TAMPER2 29 — — TAMPER1 TAMPER1 30 19 11 TAMPER0 TAMPER0 31 20 12 VDDA VDDA 32 21 13 VSSA VSSA 33 22 14 SDADP0 SDADP0 34 23 15 SDADM0 SDADM0 35 24 16 SDADP1 SDADP1 36 25 17 SDADM1 SDADM1 37 26 18 VREFH VREFH 38 27 19 VREFL VREFL 39 28 20 SDADP2/ CMP1P2 SDADP2/ CMP1P2 40 29 21 SDADM2/ CMP1P3 SDADM2/ CMP1P3 41 30 22 VREF VREF 42 — 24 SDADP3/ CMP1P4 SDADP3/ CMP1P4 43 — 23 SDADM3/ CMP1P5 SDADM3/ CMP1P5 44 — — Disabled AD0 PTC5 UART0_RTS LLWU_P12 45 — — Disabled AD1 PTC6 UART0_CTS TMR_1 46 — — Disabled AD2 PTC7 UART0_TxD XBAR_OUT2 47 — — Disabled CMP0P0 PTD0 UART0_RxD XBAR_IN2 LLWU_P11 48 31 — Disabled PTD1 UART1_TxD SPI0_SS_B XBAR_OUT3 TMR_3 49 32 — Disabled PTD2 UART1_RxD SPI0_SCK XBAR_IN3 LLWU_P10 50 33 — Disabled PTD3 UART1_CTS SPI0_MOSI 51 34 — Disabled AD3 PTD4 UART1_RTS SPI0_MISO LLWU_P9 52 — — Disabled AD4 PTD5 LPTMR2 TMR_0 UART3_CTS 53 — — Disabled AD5 PTD6 LPTMR1 CMP1OUT UART3_RTS LLWU_P8 54 — — Disabled CMP0P4 PTD7 I2C0_SCL XBAR_IN4 UART3_RxD LLWU_P7 CMP0P1 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 XBAR_IN1 KM Family Data Sheet, Rev. 7, 01/2014. 46 Freescale Semiconductor, Inc. Pinout 100 QFP 64 QFP 44 LGA DEFAULT ALT0 55 — — Disabled PTE0 56 35 25 RESET_B PTE1 57 — 26 EXTAL1 EXTAL1 PTE2 EWM_IN XBAR_IN6 I2C1_SDA 58 — 27 XTAL1 XTAL1 PTE3 EWM_OUT AFE_CLK I2C1_SCL 59 36 28 VSS VSS 60 — 29 SAR_VSSA SAR_VSSA 61 — 30 SAR_VDDA SAR_VDDA 62 37 31 VDD VDD 63 — — Disabled PTE4 LPTMR0 UART2_CTS EWM_IN 64 — — Disabled PTE5 TMR_3 UART2_RTS EWM_OUT 65 38 32 SWD_IO CMP0P2 PTE6 XBAR_IN5 UART2_RxD LLWU_P5 66 39 33 SWD_CLK AD6 PTE7 XBAR_OUT5 UART2_TxD 67 40 — Disabled AD7 PTF0 RTCCLKOUT TMR_2 68 41 34 Disabled LCD0/ AD8 PTF1 TMR_0 XBAR_OUT6 69 42 35 Disabled LCD1/ AD9 PTF2 CMP1OUT RTCCLKOUT 70 43 — Disabled LCD2 PTF3 SPI1_SS_B LPTMR1 UART0_RxD 71 44 — Disabled LCD3 PTF4 SPI1_SCK LPTMR0 UART0_TxD 72 45 — Disabled LCD4 PTF5 SPI1_MISO I2C1_SCL LLWU_P4 73 46 — Disabled LCD5 PTF6 SPI1_MOSI I2C1_SDA LLWU_P3 74 47 — Disabled LCD6 PTF7 TMR_2 CLKOUT 75 48 — Disabled LCD7 PTG0 TMR_1 LPTMR2 76 49 36 Disabled LCD8/ AD10 PTG1 LLWU_P2 LPTMR0 77 50 37 Disabled LCD9/ AD11 PTG2 SPI0_SS_B LLWU_P1 78 51 38 Disabled LCD10 PTG3 SPI0_SCK I2C0_SCL 79 52 39 Disabled LCD11 PTG4 SPI0_MOSI I2C0_SDA 80 53 40 Disabled LCD12 PTG5 SPI0_MISO LPTMR1 81 54 — Disabled LCD13 PTG6 LLWU_P0 LPTMR2 82 — — Disabled LCD14 PTG7 83 — — Disabled LCD15 PTH0 84 — — Disabled LCD16 PTH1 85 — — Disabled LCD17 PTH2 86 — — Disabled LCD18 PTH3 87 — — Disabled LCD19 PTH4 88 — — Disabled LCD20 PTH5 89 — 41 Disabled PTH6 UART1_CTS SPI1_SS_B XBAR_IN7 90 — 42 Disabled PTH7 UART1_RTS SPI1_SCK XBAR_OUT7 91 55 43 Disabled PTI0 UART1_RxD XBAR_IN8 SPI1_MISO SPI1_MOSI 92 56 44 Disabled PTI1 UART1_TxD XBAR_OUT8 SPI1_MOSI SPI1_MISO CMP0P5 ALT1 ALT2 I2C0_SDA ALT3 XBAR_OUT4 ALT4 UART3_TxD ALT5 ALT6 ALT7 CLKOUT RESET_B LLWU_P6 SWD_IO SWD_CLK CMP0OUT KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 47 Pinout 100 QFP 64 QFP 44 LGA DEFAULT ALT0 ALT1 93 57 — Disabled LCD21 PTI2 94 58 — Disabled LCD22 PTI3 95 59 — VSS VSS 96 60 — VLL3 VLL3 97 61 — VLL2 VLL2 98 62 — VLL1 VLL1 99 63 — VCAP2 VCAP2 100 64 — VCAP1 VCAP1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 8.2 KM Family Pinouts 8.2.1 100-pin LQFP The following figure represents the KM 100 LQFP pinouts: KM Family Data Sheet, Rev. 7, 01/2014. 48 Freescale Semiconductor, Inc. PTI1/UART1_TxD/XBAR_OUT8/SPI1_MOSI/SPI1_MISO PTI0/UART1_RxD/XBAR_IN8/SPI1_MISO/SPI1_MOSI/CMP0P5 PTH7/UART1_RTS/SPI1_SCK/XBAR_OUT7 PTH6/UART1_CTS/SPI1_SS_B/XBAR_IN7 PTH5/LCD20 PTH4/LCD19 PTH3/LCD18 PTH2/LCD17 PTH1/LCD16 PTH0/LCD15 PTG7/LCD14 PTG6/LLWU_P0/LPTMR2/LCD13 PTG5/SPI0_MISO/LPTMR1/LCD12 92 91 90 89 88 87 86 85 84 83 82 81 80 PTG1/LLWU_P2/LPTMR0/LCD8/AD10 PTI2/LCD21 93 PTG2/SPI0_SS_B/LLWU_P1/LCD9/AD11 PTI3/LCD22 94 76 VSS 95 77 VLL3 96 PTG4/SPI0_MOSI/I2C0_SDA/LCD11 VLL2 97 PTG3/SPI0_SCK/I2C0_SCL/LCD10 VLL1 98 78 VCAP2 99 79 VCAP1 100 Pinout PTA0/LCD23 1 75 PTG0/TMR_1/LPTMR2/LCD7 PTA1/LCD24 2 74 PTF7/TMR_2/CLKOUT/LCD6 PTA2/LCD25 3 73 PTF6/SPI1_MOSI/I2C1_SDA/LLWU_P3/LCD5 PTA3/LCD26 4 72 PTF5/SPI1_MISO/I2C1_SCL/LLWU_P4/LCD4 NMI_B/PTA4/LLWU_P15/LCD27 5 71 PTF4/SPI1_SCK/LPTMR0/UART0_TxD/LCD3 PTA5/CMP0OUT/LCD28 6 70 PTF3/SPI1_SS_B/LPTMR1/UART0_RxD/LCD2 PTA6/XBAR_IN0/LLWU_P14/LCD29 7 69 PTF2/CMP1OUT/RTCCLKOUT/LCD1/AD9 PTA7/XBAR_OUT0/LCD30 8 68 PTF1/TMR_0/XBAR_OUT6/LCD0/AD8 48 49 50 PTD2/UART1_RxD/SPI0_SCK/XBAR_IN3/LLWU_P10/CMP0P1 PTD3/UART1_CTS/SPI0_MOSI PTD4/UART1_RTS/SPI0_MISO/LLWU_P9/AD3 PTD1/UART1_TxD/SPI0_SS_B/XBAR_OUT3/TMR_3 51 47 25 PTD0/UART0_RxD/XBAR_IN2/LLWU_P11/CMP0P0 PTD5/LPTMR2/TMR_0/UART3_CTS/AD4 XTAL32K 46 PTD6/LPTMR1/CMP1OUT/UART3_RTS/LLWU_P8/AD5 52 PTC7/UART0_TxD/XBAR_OUT2/AD2 53 24 45 23 VBAT PTC6/UART0_CTS/TMR_1/AD1 PTC4/LCD43 44 PTD7/I2C0_SCL/XBAR_IN4/UART3_RxD/LLWU_P7/CMP0P4 PTC5/UART0_RTS/LLWU_P12/AD0 54 43 22 SDADM3/CMP1P5 PTE0/I2C0_SDA/XBAR_OUT4/UART3_TxD/CLKOUT PTC3/UART3_RxD/LLWU_P13/LCD42/CMP0P3 42 55 SDADP3/CMP1P4 21 41 RESET_B/PTE1 PTC2/UART3_TxD/XBAR_OUT1/LCD41 VREF PTE2/EWM_IN/XBAR_IN6/I2C1_SDA/EXTAL1 56 40 57 20 SDADM2/CMP1P3 19 PTC1/UART3_CTS/LCD40/CMP1P1 39 PTC0/UART3_RTS/XBAR_IN1/LCD39 SDADP2/CMP1P2 PTE3/EWM_OUT/AFE_CLK/I2C1_SCL/XTAL1 38 58 VREFL 18 37 VSS PTB7/AFE_CLK/LCD38 VREFH 59 36 17 SDADM1 SAR_VSSA PTB6/LCD37/CMP1P0 35 60 SDADP1 16 34 SAR_VDDA PTB5/LCD36 SDADM0 61 33 15 SDADP0 VDD PTB4/LCD35 32 PTE4/LPTMR0/UART2_CTS/EWM_IN 62 VSSA 63 14 31 13 PTB3/LCD34 VDDA PTB2/LCD33 30 PTE5/TMR_3/UART2_RTS/EWM_OUT/LLWU_P6 TAMPER0 64 29 12 TAMPER1 SWD_IO/PTE6/XBAR_IN5/UART2_RxD/LLWU_P5/CMP0P2 PTB1/LCD32 28 65 TAMPER2 11 27 SWD_CLK/PTE7/XBAR_OUT5/UART2_TxD/AD6 VSS 26 PTF0/RTCCLKOUT/TMR_2/CMP0OUT/AD7 66 VSS 67 10 EXTAL32K 9 VDD PTB0/LCD31 Figure 6. 100-pin LQFP Pinout Diagram 8.2.2 64-pin LQFP The following figure represents 64-pin LQFP pinouts: KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 49 PTA0/LCD23 PTI0/UART1_RxD/XBAR_IN8/CMP0P5 PTG6/LLWU_P0/LPTMR2/LCD13 PTG5/SPI0_MISO/LPTMR1/LCD12 PTG4/SPI0_MOSI/I2C0_SDA/LCD11 PTG3/SPI0_SCK/I2C0_SCL/LCD10 PTG2/SPI0_SS_B/LLWU_P1/LCD9/AD11 PTG1/LLWU_P2/LPTMR0/LCD8/AD10 53 52 51 50 49 PTI1/UART1_TxD/XBAR_OUT8 56 54 PTI2/LCD21 57 55 VSS PTI3/LCD22 59 58 VLL2 VLL3 VLL1 62 61 VCAP2 63 60 VCAP1 64 Pinout 1 48 PTG0/TMR_1/LPTMR2/LCD7 PTA1/LCD24 2 47 PTF7/TMR_2/CLKOUT/LCD6 PTA2/LCD25 3 46 PTF6/SPI1_MOSI/I2C1_SDA/LLWU_P3/LCD5 NMI_B/PTA4/LLWU_P15/LCD27 4 45 PTF5/SPI1_MISO/I2C1_SCL/LLWU_P4/LCD4 PTA5/CMP0OUT/LCD28 5 44 PTF4/SPI1_SCK/LPTMR0/UART0_TxD/LCD3 PTA6/XBAR_IN0/LLWU_P14/LCD29 6 43 PTF3/SPI1_SS_B/LPTMR1/UART0_RxD/LCD2 PTA7/XBAR_OUT0/LCD30 7 42 PTF2/CMP1OUT/RTCCLKOUT/LCD1/AD9 VDD 8 41 PTF1/TMR_0/XBAR_OUT6/LCD0/AD8 VSS 9 40 PTF0/RTCCLKOUT/TMR_2/CMP0OUT/AD7 PTB7/AFE_CLK/LCD38 10 39 SWD_CLK/PTE7/XBAR_OUT5/UART2_TxD/AD6 PTC0/UART3_RTS/XBAR_IN1/LCD39 11 38 SWD_IO/PTE6/XBAR_IN5/UART2_RxD/LLWU_P5/CMP0P2 29 30 31 32 VREF PTD1/UART1_TxD/SPI0_SS_B/XBAR_OUT3/TMR_3 PTD2/UART1_RxD/SPI0_SCK/XBAR_IN3/LLWU_P10/CMP0P1 28 SDADP2/CMP1P2 SDADM2/CMP1P3 26 27 VREFL 25 VREFH 24 SDADP1 VSS EXTAL32K SDADM1 PTD3/UART1_CTS/SPI0_MOSI 22 PTD4/UART1_RTS/SPI0_MISO/LLWU_P9/AD3 33 23 34 SDADP0 15 16 SDADM0 VBAT XTAL32K 21 RESET_B/PTE1 20 35 VSSA 14 VDDA VSS PTC3/UART3_RxD/LLWU_P13/LCD42/CMP0P3 19 VDD 36 18 37 TAMPER0 12 13 17 PTC1/UART3_CTS/LCD40/CMP1P1 PTC2/UART3_TxD/XBAR_OUT1/LCD41 Figure 7. 64-pin LQFP Pinout Diagram 8.2.3 44-pin LGA The following figure represents44-pin LGA pinouts: KM Family Data Sheet, Rev. 7, 01/2014. 50 Freescale Semiconductor, Inc. PTI1/UART1_TxD/XBAR_OUT8/SPI1_MOSI/SPI1_MISO PTI0/UART1_RxD/XBAR_IN8/SPI1_MISO/SPI1_MOSI/CMP0P5 PTH7/UART1_RTS/SPI1_SCK/XBAR_OUT7 PTH6/UART1_CTS/SPI1_SS_B/XBAR_IN7 PTG5/SPI0_MISO/LPTMR1 PTG4/SPI0_MOSI/I2C0_SDA PTG3/SPI0_SCK/I2C0_SCL PTG2/SPI0_SS_B/LLWU_P1/AD11 PTG1/LLWU_P2/LPTMR0/AD10 PTF2/CMP1OUT/RTCCLKOUT/AD9 PTF1/TMR_0/XBAR_OUT6/AD8 44 43 42 41 40 39 38 37 36 35 34 Revision History 28 VSS VBAT 7 27 PTE3/EWM_OUT/AFE_CLK/I2C1_SCL/XTAL1 XTAL32K 8 26 PTE2/EWM_IN/XBAR_IN6/I2C1_SDA/EXTAL1 EXTAL32K 9 25 RESET_B/PTE1 VSS 10 24 SDADP3/CMP1P4 TAMPER0 11 23 SDADM3/CMP1P5 22 6 VREF VSS 21 SAR_VSSA 20 29 SDADM2/CMP1P3 5 19 VDD SDADP2/CMP1P2 SAR_VDDA 18 30 VREFL 4 VREFH PTA7/XBAR_OUT0 17 VDD SDADM1 31 16 3 SDADP1 PTA6/XBAR_IN0/LLWU_P14 15 SWD_IO/PTE6/XBAR_IN5/UART2_RxD/LLWU_P5/CMP0P2 SDADM0 32 14 2 SDADP0 PTA5/CMP0OUT 13 SWD_CLK/PTE7/XBAR_OUT5/UART2_TxD/AD6 VSSA 33 12 1 VDDA NMI_B/PTA4/LLWU_P15 Figure 8. 44-pin LGA Pinout Diagram NOTE VSS also connects to flag on 44 LGA. 9 Revision History The following table provides a revision history for this document. KM Family Data Sheet, Rev. 7, 01/2014. Freescale Semiconductor, Inc. 51 Revision History Table 41. Revision History Rev. No. Date Substantial Changes Rev1 10/2012 Initial release Rev2 01/2013 Updated part numbers Updated Table: Power mode transition operating behaviors Updated Table: Power consumption operating behaviors. Included readings for temperature - 40 °C, 25 °C, and 85 °C Updated AFE Modulator clock maximum value in table “Device clock specifications” Updated Table: General switching specifications Updated Table: Thermal operating requirements Updated Table: SWD switching specifications Added Table: AFE (Analog Frontend ) Switching characteristics Updated Table: Oscillator DC electrical specifications Updated Table: ΣΔ ADC + PGA specifications Under section SPI switching specification, • Table SPI timing renamed to SPI switching characteristics at 2.7 V ( 2.7 3.6) • Modified row: “Data Hold Time (inputs, tHI)” to “Input Data Hold Time (inputs, tHI)” • Modified row: “Data valid time (after SCK edge, tDVO)” to “Data Valid Out Time (after SCK edge, tDVO)” Added table: SPI Switching characteristics at 1.7V (1.7 - 3.6V) NOTE added to KM Signal Multiplexing and Pin Assignments topic Rev3 04/2013 Updated orderable part numbers Updated Table: ESD handling ratings • Add new row: Electrostatic discharge voltage, charged-device mode Updated Table: Voltage and current operating behaviors Updated Table: Power consumption operating behaviors Updated "Inputs, tSUI" row in Table: SWD switching characteristics at 2.7 V (2.7 3.6 V) Updated "Inputs, tSUI" row in Table: AFE switching characteristics (1.7 V - 3.6 V) Updated "Supply voltage" minimum value in table: Voltage reference electrical specifications Added table: OD cells in SPI Switching specification Updated Table: VREF full-range operating behaviors Updated Table: ΣΔ ADC + PGA specifications Updated Table: ADC standalone specifications Table continues on the next page... KM Family Data Sheet, Rev. 7, 01/2014. 52 Freescale Semiconductor, Inc. Revision History Table 41. Revision History (continued) Rev. No. Rev4 Date 07/2013 Substantial Changes Editorial changes through out the document. Values of table "Power mode transition operating behaviors" updated. In table "Power consumption operating behaviors": • Row IDD_RUN value updated • Row IDD_WAIT value updated • Row IDD_VLPR value updated • Row IDD_VLPW value updated • Row IDD_STOP value updated • Row IDD_VLPS value updated • Row IDD_VLLS3 value updated • Row IDD_VLLS2 value updated • Row IDD_VLLS1 value updated • Row IDD_VLLS0 value updated • Row IDD_VBAT value updated • New row "IDD_VLLS0 with POR enabled" added. Values of table "General switching specifications" updated. In table "VREF full-range operating behaviors": • Row Vtdrift: value updated and footnote added. In table "LCD electricals": • Row IRBIAS: values updated. Rev5 10/2013 Table: Obtaining package dimensions updated Rev6 11/2013 Updated Section Fields: • Row: Temperature range values updated. Rev7 1/2014 Updated Table: Power consumption operating behaviors • Table: Power consumption operating behaviors • All rows with temperature 110 °C updated to 105 °C • Footnote 9 updated: An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in all conditions. There is no internal power switch in RTC. • Row IDD_VLPR: Minimum value updated • Row IDD_VLLS1: Typ value updated • Row IDD_VLLS0 with POR circuit disabled: Typ value updated • Row IDD_VLLS0 with POR circuit enabled: Typ value updated • Table: EMC radiated emissions operating behaviors • All TBD updated • Footnote 2: fosc value updated to 10 MHz • Table: ADC + PGA specifications • Row CMMR: Vid value updated • Table: ADC standalone specifications • Row CMMR: Vid value updated KM Family Data Sheet, Rev. 7, 01/2014. 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