Freescale Semiconductor Application Note Document Number:AN4568 Rev. 0, 09/2012 Understanding the 16-bit ADC PGA in Kinetis K series by: Martin Mienkina, Han Lin, and Alejandra Guzman Automotive and Industrial Solutions Group Contents 1 Introduction 1 Introduction................................................................1 Freescale's Kinetis microcontrollers integrate a 16-bit analogto-digital converter (ADC16) with built-in programmable gain amplifier (PGA), which is capable to operate in several modes. 2 Kinetis PGA integration............................................2 3 PGA dynamic input examples...................................5 4 16-bit ADC measurement use-case ..........................7 5 Conclusion.................................................................9 6 References.................................................................9 The Programmable Gain Amplifier (PGA) is designed to increase the dynamic range by amplifying low-amplitude signals before they are fed to the 16-bit ADC. 1.1 Abstract Whenever a gain stage is included in the converter path, the Signal to Noise Ratio (SNR) will go down. This effect occurs because the PGA induces noise into the system. Therefore, question may arise why would an application include PGA on the system? The main reason to include a PGA stage before an ADC conversion is to increase the dynamic range. Dynamic range indicates the minimum resolvable step size and the ratio between the largest and smallest possible inputs. Resolution is the number of bits in the result, and is often confused with dynamic range. © 2012 Freescale Semiconductor, Inc. Kinetis PGA integration 1.2 Objective This document describes technical observations and transfer functions of the ADC16 and ADC16-PGA measurement chains in typical measurement use-cases. The information provided in this application note has been validated by experimental measurements on TWR-K60N512 board. 2 Kinetis PGA integration Kinetis K series 72 MHz and 100 MHz microcontrollers feature up to two 16-bit ADCs. Each ADC contains a PGA channel for a total of two separate PGAs as shown in Figure 1. Figure 1. Dual ADC PGA integration Kinetis K series120 MHz and 150 MHz have up to four ADCs. Each ADC contains a PGA channel for a total of four separate PGAs as shown in Figure 2. Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 2 Freescale Semiconductor, Inc. Kinetis PGA integration Figure 2. Quad ADC PGA integration 2.1 PGA voltage range PGA reference option is the only 1.2 V V REF_OUT source. The VREF_OUT signal can either be driven by an external voltage source1 via the VREF_OUT pin or from the output of the VREF module. The PGA differential mode operation takes a differential input voltage. ADC results will be the amplified difference between PGA Differential Plus (PGA_DP) and PGA Differential Minus (PGA_DM) with the common mode correction. Eqn. 1 shows that the PGA common mode voltage2, Vx, is set to 700 mV The formula at Eqn. 2 describes the maximum PGA differential input signal swing3 for the ADC16-PGA 1. Ensure that the VREF module is disabled when an external voltage is used (applied at the VREF_OUT pin) instead of the VREF module. 2. The expected variations of the PGA common mode voltage are in the range +–15–20 mV. Those variations are caused by PGA common mode control circuit. The increase of common mode voltage causes decrease of the maximum differential input swing, expressed by Eqn. 2 Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 Freescale Semiconductor, Inc. 3 Kinetis PGA integration where: Vx is 700 mV VVREFis 1.2 V Gain represents the possible PGA gains (1, 2, 4, 8, 16, 32, 64) Theoretically,16-bit ADC digital output range can be calculated by where:N is the number of bits (resolution) selected for the current conversion PGA_DP and PGA_DM peak-to-peak maximum permitted voltages where: VppDP,ppDM is the peak-to-peak voltage at the PGA inputs VPPADC,DIF is the peak-to-peak PGA differential input swing VppDP is the maximum peak-to-peak voltage at the PGA plus-side input pin VppDM is the maximum peak-to-peak voltage at the PGA minus-side input pin VREFPGA is the PGA voltage reference (VREF_OUT) Table 1 summarizes differential input signal swing and respective digital output range of the ADC16 for all PGA gain stages. Table 1. PGA input ranges 3. PGA Gain VPPADC,DIF × 01 2000 mV × 02 1000 mV × 04 500 mV × 08 250 mV × 16 125 mV × 32 62.5 mV × 64 31.25 mV ADCOUT 54613 LSB Formula describes maximum differential input swing taking into account the overall ADC16-PGA measurement chain. Note that it differs from datasheet formula, VPPADC,DIF=((min(Vx,VDDA – Vx) – 0.2) ×4)/Gain, which expresses PGA maximum differential input swing. Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 4 Freescale Semiconductor, Inc. PGA dynamic input examples 3 PGA dynamic input examples The following sections show the maximum differential input swing of the ADC16-PGA measurement chain using two different PGA gain stage settings. For the first, PGA gain is set to one (x1), then measurement is made with PGA gain set to the maximum gain (x64). 3.1 PGA enable (gain = 01) A differential 2000 mVpp sinusoidal signal is applied on the positive (PGA_DP) and negative (PGA_DM) inputs of the PGA. Both ADC16 and PGA have been set to 1.2 V reference driven by the internal VREF module (measured reference voltage 1.1972 V). When the PGA gain is set to 1, the experiment shows what is in Figure 3. Figure 3. Differential input waveform setup (PGA enable, gain = 01) At the PGA output, the common voltage is switched to 700 mV. Because the inputs are always corrected to the PGA common voltage, it does not matter if PGA_DP and PGA_DM go above 1.2 V, as long as the signal swing is inside the permitted value as shown in Table 1. The ADC16 output range for differential sine waveform input 2000 mVpp PGA gain of 1 is shown in Figure 4. Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 Freescale Semiconductor, Inc. 5 PGA dynamic input examples Figure 4. Digital output range at full input swing (PGA enable, gain = 01) The range of the ADC digital output codes is 53369 LSB. It is close to the expected digital output range (54613 LSB) given in Table 1. 3.2 PGA enable (gain = 64) A differential 31.25 mVpp sinusoidal signal has been applied on the positive and negative inputs of the PGA. Both ADC16 and PGA have been set to 1.2 V reference driven by the internal VREF module (measured reference voltage 1.1972 V). The PGA gain was set to 64. The experiment setup is shown in Figure 5. Figure 5. Differential input waveform setup (PGA enable, gain = 64) Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 6 Freescale Semiconductor, Inc. 16-bit ADC measurement use-case The ADC16 output range for differential sine waveform input 31.25 mVpp PGA gain of 64 is shown in Figure 6. Figure 6. Digital output range at full input swing (PGA enable, gain = 64) The ADC digital output code range measured on the ADC is 53489 LSB, which is close to the theoretical range of 54613 LSB shown in Table 1. 4 16-bit ADC measurement use-case This section shows typical ADC16 differential measurement use-casewith PGA disable. The purpose of this experiment is to show the tradeoffs between ADC16 differential measurements and PGA-ADC16 conversions. Figure 7 shows a differential 2400 mVpp sinusoidal signal applied to an ADC16 differential inputs with PGA bypassed. The ADC16 voltage reference is set to 1.2 V driven by the internal VREF module (measured reference voltage 1.1972 V) Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 Freescale Semiconductor, Inc. 7 16-bit ADC measurement use-case Figure 7. Differential input waveform setup (PGA disable) The ADC16 output range for differential sine waveform input 2.4 Vpp is shown in Figure 8. Figure 8. Digital output range at full input swing (PGA disable) Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 8 Freescale Semiconductor, Inc. Conclusion The ADC digital output code range measured on the ADC is 64753 LSB, which is close to the theoretical range of 65536 LSB shown in Table 1. 5 Conclusion The comparison of input signal swings and maximum digital output ranges of typical ADC16 measurement use-cases has been performed. When amplifiers are used the application needs to take into account that there are no ideal responses, accuracy lost or error will always be present. Kinetis PGA has a common mode voltage reference different to the ideal VREF/2 and there is also an offset error VOFS. Therefore, the theoretical input swing is higher when PGA is disabled – see Table 2 (bold entries). Although ADC16 with PGA disabled increases the input swing, dynamic range will always be the same because there is no pre-amplification stage. Table 2. PGA impact on 16-bit ADC input voltage range Use-Case VPPADC,DIF Theoretical ADCOUT Measure ADCOUT ADC16-PGA MEASUREMENT (PGA enabled, gain=x64) 31.25 mVpp 54613 LSB 53489 LSB ADC16-PGA MEASUREMENT (PGA enabled, gain=x01) 2000 mVpp 54613 LSB 53369 LSB ADC16 MEASUREMENT (PGA disabled) 2400 mVpp 65536 LSB 64753 LSB Conversion results, obtained from ADC16 result registers, shown at Figure 4, Figure 6, and Figure 8 show difference between theoretical and measurement values. ADC16 results in conversion error when positive input is near upper rail reference voltage. It occurs only in 16-bit differential mode while other modes of operation are unaffected. Such behavior of the analog converter, its root cause and workaround is known and described under errata e38634. The conversion error attributed to given errata can be considered as the deviation between “ADCOUT Theoretical” and “ADCOUT Measure” – see Table 2. 6 References Freescale's “KINETIS_4N30D - Mask Set Errata for Mask 4N30D”, Rev.15 MAY 2012, available in freescale.com 4. Freescale's “KINETIS_4N30D - Mask Set Errata for Mask 4N30D”, Rev.15 MAY 2012, freescale.com Understanding the 16-bit ADC PGA in Kinetis K series, Rev. 0, 09/2012 Freescale Semiconductor, Inc. 9 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Document Number: AN4568 Rev. 0, 09/2012 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.