Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny261/461/861) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861) Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny261/461/861) – Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features – 8/16-bit Timer/Counter with Prescaler and Two PWM Channels – 8/10-bit High Speed Timer/Counter with Separate Prescaler 3 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time Generator – Universal Serial Interface with Start Condition Detector – 10-bit ADC 11 Single Ended Channels 16 Differential ADC Channel Pairs 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator I/O and Packages – 16 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC and 32-pad MLF Operating Voltage: – 1.8 - 5.5V for ATtiny261V/461V/861V – 2.7 - 5.5V for ATtiny261/461/861 Speed Grade: – ATtiny261V/461V/861V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny261/461/861: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption – Active Mode: 1 MHz, 1.8V: 380μA – Power-down Mode: 0.1μA at 1.8V 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny261/V ATtiny461/V ATtiny861/V Preliminary Summary 2588BS–AVR–11/06 1. Pin Configurations Figure 1-1. Pinout ATtiny261/461/861 PDIP/SOIC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1) PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND AVCC PA4 (ADC3/ICP0/PCINT4) PA5 (ADC4/AIN2/PCINT5) PA6 (ADC5/AIN0/PCINT6) PA7 (ADC6/AIN1/PCINT7) 32 31 30 29 28 27 26 25 PB2 (SCK/USCK/SCL/OC1B/PCINT10) PB1 (MISO/DO/OC1A/PCINT9) PB0 (MOSI/DI/SDA/OC1A/PCINT8) NC NC NC PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1) (MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (OC1B/PCINT11) PB3 VCC GND (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 1 2 3 4 5 6 7 8 QFN/MLF 24 23 22 21 20 19 18 17 NC PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND NC NC AVCC PA4 (ADC3/ICP0/PCINT4) NC (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 NC (ADC6/AIN1/PCINT7) PA7 (ADC5/AIN0/PCINT6) PA6 (ADC4/AIN2/PCINT5) PA5 NC 9 10 11 12 13 14 15 16 NC (OC1B/PCINT11) PB3 NC VCC GND NC (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. 1.1 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 2. Overview The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Block Diagram GND Figure 2-1. VCC 2.1 Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET debugWIRE Flash SRAM PROGRAM LOGIC CPU EEPROM AVCC AGND AREF Timer/Counter1 A/D Conv. USI Analog Comp. Internal Bandgap DATABUS Timer/Counter0 3 PORT B (8) 11 PORT A (8) RESET XTAL[1..2] PB[0..7] PA[0..7] 3 2588BS–AVR–11/06 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny261/461/861 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 2.2.1 Pin Descriptions VCC Supply voltage. 2.2.2 GND Ground. 2.2.3 AVCC Analog supply voltage. 2.2.4 AGND Analog ground. 2.2.5 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny261/461/861 as listed on page 65. 4 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 2.2.6 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny261/461/861 as listed on page 61. 2.2.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page 189. Shorter pulses are not guaranteed to generate a reset. 5 2588BS–AVR–11/06 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 6 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 4. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F (0x5F) SREG I T H S V N Z C Page page 9 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 page 12 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 12 0x3C (0x5C) Reserved 0x3B (0x5B) GIMSK INT1 INT0 PCIE1 PCIE0 – – – – page 51 0x3A (0x5A) GIFR INTF1 INTF0 PCIF – – – – – page 51 0x39 (0x59) TIMSK OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 page 86, page 123 0x38 (0x58) TIFR OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 page 87, page 124 0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SPMEN page 166 0x36 (0x56) PRR PRTIM1 PRTIM0 PRUSI PRADC page 35 0x35 (0x55) MCUCR – PUD SE SM1 SM0 – ISC01 ISC00 page 37, page 68, page 50 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF page 44, 0x33 (0x53) TCCR0B – – – TSM PSR0 CS02 CS01 CS00 page 70 0x32 (0x52) TCNT0L Timer/Counter0 Counter Register Low Byte 0x31 (0x51) OSCCAL Oscillator Calibration Register 0x30 (0x50) TCCR1A COM1A1 COM1A0 COM1B1 PWM1X PSR1 DTPS11 – page 85 page 32 COM1B0 FOC1A FOC1B PWM1A PWM1B page 113 DTPS10 CS13 CS12 CS11 CS10 page 166 0x2F (0x4F) TCCR1B 0x2E (0x4E) TCNT1 Timer/Counter1 Counter Register page 121 0x2D (0x4D) OCR1A Timer/Counter1 Output Compare Register A page 121 0x2C (0x4C) OCR1B Timer/Counter1 Output Compare Register B page 122 0x2B (0x4B) OCR1C Timer/Counter1 Output Compare Register C page 122 0x2A (0x4A) OCR1D Timer/Counter1 Output Compare Register D 0x29 (0x49) PLLCSR LSM 0x28 (0x48) CLKPR CLKPCE 0x27 (0x47) TCCR1C COM1A1S COM1A0S COM1B1S 0x26 (0x46) TCCR1D FPIE1 FPEN1 FPNC1 0x25 (0x45) TC1H 0x24 (0x44) DT1 0x23 (0x43) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 0x22 (0x42) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 0x21 (0x41) WDTCR WDIF WDIE WDP3 WDCE WDE 0x20 (0x40) DWDR 0x1F (0x3F) EEARH 0x1E (0x3E) EEARL 0x1D (0x3D) EEDR 0x1C (0x3C) EECR – – EEPM1 EEPM0 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 0x19 (0x39) PINA PINA7 PINA6 0x18 (0x38) PORTB PORTB7 0x17 (0x37) DDRB 0x16 (0x36) DT1H3 DT1H2 DT1H1 page 123 PCKE PLLE PLOCK CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 32 COM1B0S COM1D1 COM1D0 FOC1D PWM1D page 117 FPES1 FPAC1 FPF1 WGM11 WGM10 page 119 TC19 TC18 page 121 DT1L2 DT1L1 DT1L0 page 124 PCINT3 PCINT2 PCINT1 PCINT0 page 52 PCINT11 PCINT10 PCINT9 PCINT8 page 52 WDP2 WDP1 WDP0 page 44 DT1H0 DT1L3 DWDR[7:0] EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 page 89 page 35 EEAR8 page 21 EEAR2 EEAR1 EEAR0 page 21 EERIE EEMPE EEPE EERE page 22 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 page 68 DDA4 DDA3 DDA2 DDA1 DDA0 page 68 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 page 68 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 68 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 68 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 68 0x15 (0x35) TCCR0A TCW0 ICEN0 ICNC0 ICES0 ACIC0 WGM00 page 84 0x14 (0x34) TCNT0H Timer/Counter0 Counter Register High Byte page 85 0x13 (0x33) OCR0A Timer/Counter0 Output Compare Register A page 85 0x12 (0x32) OCR0B Timer/Counter0 Output Compare Register B 0x11 (0x31) USIPP EEPROM Data Register page 22 page 85 USIPOS page 137 0x10 (0x30) USIBR USI Buffer Register 0x0F (0x2F) USIDR USI Data Register 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 134 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 135 0x0C (0x2C) GPIOR2 General Purpose I/O Register 2 page 23 0x0B (0x2B) GPIOR1 General Purpose I/O Register 1 page 23 0x0A (0x2A) GPIOR0 General Purpose I/O Register 0 0x09 (0x29) ACSRB HSEL HLEV page 134 page 133 page 23 ACM2 ACM1 ACM0 page 141 0x08 (0x28) ACSRA ACD ACBG ACO ACI ACIE ACME ACIS1 ACIS0 page 138 0x07 (0x27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 154 0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 157 0x05 (0x25) ADCH ADC Data Register High Byte 0x04 (0x24) ADCL ADC Data Register Low Byte 0x03 (0x23) ADCSRB BIN GSEL 0x02 (0x22) DIDR1 ADC10D ADC9D 0x01 (0x21) DIDR0 ADC6D ADC5D ADC4D ADC3D AREFD ADC2D ADC1D ADC0D page 160 0x00 (0x20) TCCR1E – - OC1OE5 OC1OE4 OC1OE3 OC1OE2 OC1OE1 OC1OE0 page 120 REFS2 ADC8D MUX5 page 158 page 158 ADTS2 ADTS1 ADTS0 ADC7D page 158 page 160 7 2588BS–AVR–11/06 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 8 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 2 BRANCH INSTRUCTIONS RJMP k IJMP RCALL k Relative Jump PC ← PC + k + 1 None Indirect Jump to (Z) PC ← Z None 2 Relative Subroutine Call PC ← PC + k + 1 None 3 3 ICALL Indirect Call to (Z) PC ← Z None RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 1/2/3 1 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 9 2588BS–AVR–11/06 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 SES Set Signed Test Flag S←1 S 1 CLS Clear Signed Test Flag S←0 S 1 SEV Set Twos Complement Overflow. V←1 V 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 Load Program Memory R0 ← (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 Store Program Memory (z) ← R1:R0 None IN Rd, P In Port Rd ← P None OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 SPM 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/Timer) For On-chip Debug Only None None 1 N/A 10 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 6. Ordering Information 6.1 ATtiny261 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code(2) Package(1) 1.8 - 5.5V ATtiny261V-10MU ATtiny261V-10PU ATtiny261V-10SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny261-20MU ATtiny261-20PU ATtiny261-20SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 187 Package Type 32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 11 2588BS–AVR–11/06 6.2 ATtiny461 Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) 10 1.8 - 5.5V ATtiny461V-10MU ATtiny461V-10PU ATtiny461V-10SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) 20 2.7 - 5.5V ATtiny461-20MU ATtiny461-20PU ATtiny461-20SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) Notes: Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 187 Package Type 32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 12 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 6.3 ATtiny861 Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) 10 1.8 - 5.5V ATtiny861V-10MU ATtiny861V-10PU ATtiny861V-10SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) 20 2.7 - 5.5V ATtiny861-20MU ATtiny861-20PU ATtiny861-20SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) Notes: Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 187 Package Type 32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 13 2588BS–AVR–11/06 7. Packaging Information 7.1 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b K 0.20 REF 0.18 e L BOTTOM VIEW D1 4.75 BSC 2.95 E1 E2 3.10 3.25 5.00 BSC 4.75BSC 2.95 e Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 0.30 5.00 BSC E b 0.23 D D2 NOTE 3.10 3.25 0.50 BSC L 0.30 0.40 0.50 P – – 0.60 o 12 0 – K 0.20 – – – 8/19/04 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. D ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 7.2 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.493 – 25.984 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e NOTE Note 2 Note 2 2.540 TYP 1/12/04 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C 15 2588BS–AVR–11/06 7.3 16 20S2 ATtiny261/461/861 2588BS–AVR–11/06 ATtiny261/461/861 8. Errata 8.1 Errata ATtiny261 The revision letter in this section refers to the revision of the ATtiny261 device. 8.1.1 Rev A No known errata. 8.2 Errata ATtiny461 The revision letter in this section refers to the revision of the ATtiny461 device. 8.2.1 Rev B Yield improvement. No known errata. 8.2.2 Rev A No known errata. 8.3 Errata ATtiny861 The revision letter in this section refers to the revision of the ATtiny861 device. 8.3.1 Rev B No known errata. 8.3.2 Rev A Not sampled. 17 2588BS–AVR–11/06 9. Datasheet Revision History 9.1 Rev. 2588A – 11/06 1. 2. 9.2 Rev. 2588A – 10/06 1. 18 Updated ”Ordering Information” on page 222. Updated ”Packaging Information” on page 225. Initial Revision. ATtiny261/461/861 2588BS–AVR–11/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. ATMEL ®, logo and combinations thereof, Everywhere You Are ®, AVR ®, AVR Studio ®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2588BS–AVR–11/06