Features • • • • • • • • • • • • • • Supply Voltage up to 40V RDSon Typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C Up to 1.0A Output Current Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers Capable of Switching Loads such as DC Motors, Bulbs, Resistors, Capacitors, and Inductors PWM Capability up to 25 kHz for Each High-side Output Controlled by External PWM Signal No Shoot-through Current Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range Outputs Short-circuit Protected Selective Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency QFN18 Package Triple Half-bridge Driver with SPI and PWM ATA6831 1. Description The ATA6831 provides fully protected driver interfaces designed in SOI technology. They are used to allow a microcontroller to control up to 3 different loads in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 1.0A. Due to the enhanced PWM signal (up to 25 kHz) it is possible to generate a smooth control of, for example, a DC motor without any noise. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface, enabling all kinds of loads, such as bulbs, resistors, capacitors and inductors, to be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed with respect to short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. 4908E–AUTO–06/07 Figure 1-1. Block Diagram S I O S C O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 10 VS1 11 Input register Ouput register DI 4 P S F I N H O V L n. u. Serial interface n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 Charge pump L S 1 VS2 T P CLK 5 CS 3 Fault detector DO Fault detector UV protection Fault detector 9 7 Control logic PWM 6 VCC Power on reset 8 GND 14 Fault detector Fault detector Fault detector GND Thermal protection 17 GND 18 2 1 2 13 OUT3S OUT3F OUT2S 12 OUT2F 16 OUT1S 15 GND OUT1F ATA6831 4908E–AUTO–06/07 ATA6831 2. Pin Configuration Pinning QFN18 PGND3 PGND1 OUT1S OUT1F PGND2 OUT2S Figure 2-1. OUT3S OUT3F CS DI CLK PWM Table 2-1. 1 2 3 4 5 6 18 17 16 15 14 13 12 11 10 9 8 7 OUT2F VS2 VS1 VCC GND DO Pin Description Pin Symbol Function 1 OUT3S Used only for final testing, to be connected to OUT3F 2 OUT3F Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 3 CS Chip select input; 5V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled 4 DI Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control device; DI expects a 16-bit control word with LSB transferred first 5 CLK Serial clock input; 5V CMOS logic level input with internal pull-down; controls serial data input interface and internal shift register (fmax = 2 MHz) 6 PWM PWM input; 5V CMOS logic level input with internal pull-down 7 DO 8 GND Ground 9 VCC Logic supply voltage (5V) 10 VS1 Power supply for output stages OUT1 and OUT2; internal supply 11 VS2 Power supply for output stages OUT2 and OUT3; internal supply 12 OUT2F Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 13 OUT2S Used only for final testing, to be connected to OUT2F 14 PGND2 Power ground OUT2 15 OUT1F Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 16 OUT1S Used only for final testing, to be connected to OUT1F 17 PGND1 Power ground OUT1 18 PGND3 Power ground OUT3 Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is selected by CS = low; this allows several ICs to operate on only one data-output line 3 4908E–AUTO–06/07 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer CS DI SRR 0 LS1 1 HS1 LS2 HS2 2 3 4 S1H S2L S2H LS3 HS3 PL1 5 6 7 8 S3H n. u. n. u. PH1 PL2 9 PH2 10 PL3 11 PH3 12 OCS OLD 13 14 SI 15 CLK DO TP S1L Table 3-1. 4 S3L n. u. n. u. n. u. n. u. OVl INH PSF Input Data Protocol Bit Input Register 0 SRR Function Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 PL1 Output LS1 additionally controlled by PWM Input 8 PH1 Output HS1 additionally controlled by PWM Input 9 PL2 See PL1 10 PH2 See PH1 11 PL3 See PL1 12 PH3 See PH1 13 OLD Open load detection (low = on) 14 OCS Overcurrent shutdown (high = overcurrent shutdown is active) 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because the digital part is still powered) ATA6831 4908E–AUTO–06/07 ATA6831 Table 3-2. Output Data Protocol Bit Output (Status) Register 0 TP Function Temperature prewarning: high = warning Status LS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR 2 Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 OVL Over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch 14 INH Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation 15 PSF Power-supply fail: undervoltage at pin VS detected 5 4908E–AUTO–06/07 After power-on reset, the input register has the following status: Bit 15 SI Bit 14 OCS Bit 13 OLD Bit 12 PH3 Bit 11 PL3 Bit 10 PH2 Bit 9 PL2 Bit 8 PH1 Bit 7 PL1 Bit 6 HS3 Bit 5 LS3 Bit 4 HS2 Bit 3 LS2 Bit 2 HS1 Bit 1 LS1 Bit 0 SRR H H H L L L L L L L L L L L L L The following patterns are used to enable internal test modes of the IC. Do not use these patterns during normal operation. Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 Bit 1 (HS1) (LS1) Bit 0 (SRR) H H H H H L L L L L L L L L L L H H H L L H H L L L L L L L L L H H H L L L L H H L L L L L L L 3.2 Power-supply Fail If undervoltage is detected at pin VS, the power-supply fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when the supply voltage returns to the normal operational value. The PSF bit stays high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If the current through the external load does not reach the open-load detection current, the corresponding bit of the output in the output register is set to high. Switching on an output stage with the OLD bit set to low disables the open-load function for this output. 6 ATA6831 4908E–AUTO–06/07 ATA6831 3.4 Overtemperature Protection If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, T jPW set , the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tjswitch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additionally, the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on, and the SRR bit in the input register is set to high. The hysteresis of thermal prewarning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the overcurrent shutdown bit (OCS) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off, following a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low, the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled. 3.6 Inhibit The SI bit in the input register has to be set to zero to inhibit the ATA6831. In this state, all output stages are then turned off but the serial interface remains active. The current consumption is reduced to less than 5 µA at pin VS and less than 100 µA at pin VCC. The output stages can be reactivated by setting bit SI to “1”. 3.7 PWM Mode The common input for all six outputs is pin PWM (Figure 3-2). The selection of the outputs, which are controlled by PWM, is done by input data register PLx or PHx. In addition to the PWM input register, the corresponding input registers HSx and LSs have to be set. Switching the high side outputs is possible up to 25 kHz, low side switches up to 8 kHz. Figure 3-2. Output Control by PWM Bit LSx/HSx Pin OUTx Bit PLx/PHx Pin PWM 7 4908E–AUTO–06/07 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Pin Symbol Value Unit Supply voltage 10, 11 VVS –0.3 to +40 V Supply voltage t < 0.5s; IS > –2A 10, 11 VVS –1 V 9 VVCC –0.3 to +7 V 3, 4, 5, 6 VCS, VDI, VCLK, VPWM –0.3 to VVCC + 0.3 V 7 VDO –0.3 to VVCC + 0.3 V 3, 4, 5, 6 ICS, IDI, ICLK, IPWM –10 to +10 mA Output current 7 IDO –10 to +10 mA Output current 2, 12, 15 IOut1, IOut2, IOut3 Internally limited, see output specification Output voltage 2, 12, 15 IOut1, IOut2, IOut3 –0.3 to +40 V Reverse conducting current (tpulse = 150 µs) 2, 12, 15 IOut1, IOut2, IOut3 17 A Junction temperature range TJ –40 to +150 °C Storage temperature range TSTG –55 to +150 °C Logic supply voltage Logic input voltage Logic output voltage Input current 5. Thermal Resistance Parameters Test Conditions Thermal resistance from junction to case Thermal resistance from junction to ambient Depends on the PC board Symbol Value Unit RthJC 15 k/W RthJA 40 K/W 6. Operating Range Parameters Symbol Value Unit Supply voltage VVS VUV(1) to 40 V Logic supply voltage VVCC 4.75 to 5.25 V VCS, VDI, VCLK, VPWM –0.3 to VVCC V Serial interface clock frequency fCLK 2 MHz PWM input frequency fPWM max. 25 kHz Tj –40 to +150 °C Logic input voltage Junction temperature range Note: 8 1. Threshold for undervoltage description ATA6831 4908E–AUTO–06/07 ATA6831 7. Noise and Surge Immunity Parameters Test Conditions Value Conducted interferences ISO 7637-1 Level 4(1) Interference suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) ESD S 5.1 2 kV CDM (Charge Device Model) ESD STM5.3.1 500V Note: 1. Test pulse 5: Vsmax = 40V 8. Electrical Characteristics 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 1 Parameters Test Conditions Pin Symbol 10, 11 Min. Typ. Max. Unit Type* IVS 1 5 µA A 9 IVCC 60 100 µA A 10, 11 IVS 4 6 mA A 350 650 µA A Current Consumption VVS < 20V, SI = low 1.1 Quiescent current VS 1.2 4.75V < VVCC < 5.25V, Quiescent current VCC SI = low 1.3 Supply current VS VVS < 20V normal operating, all outputs off, input register bit 13 (OLD) = high 1.4 Supply current VCC 4.75V < VVCC < 5.25V, normal operating 9 IVCC 1.5 Discharge current VS VVS = 32.5V, INH = low 10, 11 IVS 0.5 5.5 mA A 1.6 Discharge current VS VVS = 40V, INH = low 10, 11 IVS 2.5 14 mA A 9 VVCC 3.2 3.9 4.4 V A tdPor 30 95 190 µs A 5.6 7.0 V A V A 40 µs A 2 Undervoltage Detection, Power-on Reset 2.1 Power-on reset threshold 2.2 Power-on reset delay time 2.3 Undervoltage-detection VCC = 5V threshold 10, 11 VUv 2.4 Undervoltage-detection VCC = 5V hysteresis 10, 11 ∆VUv 2.5 Undervoltage-detection delay time 3 After switching on VCC 0.6 tdUV 10 TjPW set 120 145 170 °C B 105 130 155 °C B K B Thermal Prewarning and Shutdown 3.1 Thermal prewarning set 3.2 Thermal prewarning reset TjPW reset 3.3 Thermal prewarning hysteresis ∆TjPW 3.4 Thermal shutdown off Tj switch off 150 175 200 °C B 3.5 Thermal shutdown on Tj switch on 135 160 185 °C B 15 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 9 4908E–AUTO–06/07 8. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Min. Typ. Max. Unit Type* K B Parameters 3.6 Thermal shutdown hysteresis ∆Tj switch off 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ TjPW set 1.05 1.2 B 3.8 Ratio thermal shutdown on/thermal prewarning reset Tj switch on/ TjPW reset 1.05 1.2 B 4 Test Conditions Symbol No. Pin 15 Output Specification (OUT1 to OUT3) 4.1 IOut 1-3 = –0.9 A 2, 12, 15 RDSon1-3H 1.5 Ω A IOut 1-3 = –0.9 A 2, 12, 15 RDSon1-3L 1.5 Ω A µA A On resistance 4.2 4.3 High-side output leakage current VOut 1-3 H = 0V, output stages off 2, 12, 15 IOut1-3H 4.4 Low-side output leakage current VOut 1-3 L = VVS, output stages off 2, 12, 15 IOut1-3L 300 µA A 4.5 High-side switch reverse diode forward voltage IOut = 1.5A 2, 12, 15 VOut1-3 – VVS 2 V A 4.6 Low-side switch reverse IOut 1-3 L = –1.5A diode forward voltage 2, 12, 15 VOut1-3L 2 V A 4.7 High-side overcurrent limitation and shutdown 7.5V < VVS < 20V threshold 2, 12, 15 IOut1-3 1.0 1.3 1.7 A A 4.8 Low-side overcurrent limitation and shutdown 7.5V < VVS < 20V threshold 2, 12, 15 IOut1-3 –1.7 –1.3 –1.0 A A 4.9 High-side overcurrent limitation and shutdown 20V < VVS < 40V threshold 2, 12, 15 IOut1-3 1.0 1.3 2.0 A A 4.10 Low-side overcurrent limitation and shutdown 20V < VVS < 40V threshold 2, 12, 15 IOut1-3 –2.0 –1.3 –1.0 A A 4.11 Overcurrent shutdown delay time tdSd 10 40 µs A 4.12 High-side open load detection current Input register bit 13 (OLD) = low, output off VVS = 13V 2, 12, 15 IOut1-3H –12 –5 mA A 4.13 Low-side open load detection current Input register bit 13 (OLD) = low, output off VVS = 13V 2, 12, 15 IOut1-3L 0.05 1.4 mA A –15 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 10 ATA6831 4908E–AUTO–06/07 ATA6831 8. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Max. Unit Type* tdon 20 µs A Low-side output switch VVS = 13V RLoad = 30Ω on delay(1),(2) tdon 20 µs A 4.17 High-side output switch VVS =13V off delay(1),(2) RLoad = 30Ω tdoff 20 µs A 4.18 Low-side output switch VVS =13V RLoad = 30Ω off delay(1),(2) tdoff 3 µs A 4.19 Dead time between corresponding high-side and low-side switches VVS =13V RLoad = 30Ω tdon – tdoff µs A 4.20 ∆tdPWM low-side switch(3) VVS = 13V RLoad = 30Ω ∆tdPWM = tdon – tdoff 20 µs A 4.21 ∆tdPWM high-side switch(3) VVS = 13V RLoad = 30Ω ∆tdPWM = tdon – tdoff -5 5 µs A 0.3 × VVCC V A 0.7 × VVCC V A No. Parameters 4.15 High-side output switch VVS = 13V RLoad = 30Ω on delay(1),(2) 4.16 5 Test Conditions Pin Symbol Min. Typ. 1 Logic Inputs DI, CLK, CS, PWM 5.1 Input voltage low-level threshold 3, 4, 5, 6 VIL 5.2 Input voltage high-level threshold 3, 4, 5, 6 VIH 5.3 Hysteresis of input voltage 3, 4, 5, 6 ∆VI 50 700 mV A 5.4 Pull-down current pins DI, CLK, PWM VDI, VCLK, VPWM = VCC 4, 5, 6 IPD 10 65 µA A 5.5 Pull-up current pin CS VCS = 0V 3 IPU –65 –10 µA A 7 VDOL 0.4 V A V A 10 µA A 100 µs A 6 Serial Interface – Logic Output DO 6.1 Output-voltage low level IDOL = 2 mA 6.2 Output-voltage high level IDOL = –2 mA 7 VDOH VVCC – 0.7V 6.3 Leakage current (tri-state) VCS = VCC 0V < VDO < VVCC 7 IDO –10 7 7.1 Inhibit Input – Timing Delay time from standby to normal operation tdINH *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 11 4908E–AUTO–06/07 9. Serial Interface Timing No. 8 Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type* Serial Interface Timing 8.1 DO enable after CS CDO = 100 pF falling edge 7 1 tENDO 200 ns D 8.2 DO disable after CS CDO = 100 pF rising edge 7 2 tDISDO 200 ns D 8.3 DO fall time CDO = 100 pF 7 - tDOf 100 ns D 8.4 DO rise time CDO = 100 pF 7 - tDOr 100 ns D 8.5 DO valid time CDO = 100 pF 7 10 tDOVal 200 ns D 8.6 CS setup time 3 4 tCSSethl 225 ns D 8.7 CS setup time 3 8 tCSSetlh 225 ns D 8.8 CS high time 3 9 tCSh 500 ns D 8.9 CLK high time 5 5 tCLKh 225 ns D 8.10 CLK low time 5 6 tCLKl 225 ns D 8.11 CLK period time 5 - tCLKp 500 ns D 8.12 CLK setup time 5 7 tCLKSethl 225 ns D 8.13 CLK setup time 5 3 tCLKSetlh 225 ns D 8.14 DI setup time 4 11 tDIset 40 ns D 8.15 DI hold time 4 12 tDIHold 40 ns D *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 12 ATA6831 4908E–AUTO–06/07 ATA6831 Figure 9-1. Serial Interface Timing with Chart Number 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC 13 4908E–AUTO–06/07 10. Application Circuit Figure 10-1. Application Circuit VCC VS S I Trigger Reset U5021M Watchdog O S C O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R BYV28 10 VBatt VS1 11 Input register Ouput register P S F DI 4 I N H O V L n. u. Serial interface n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 Charge pump L S 1 13V VS2 + T P CLK 5 Microcontroller CS 3 Fault detector Fault detector VCC UV protection Fault detector VCC 9 DO Control logic 7 PWM 6 VCC Power on reset 5V + 8 GND Fault detector Fault detector 14 Fault detector GND Thermal protection VCC 17 GND 18 1 2 13 OUT3F 16 OUT2F M 10.1 12 GND 15 OUT1F M Application Notes • Connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. • Recommended value for capacitors at VS: – Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The value for the electrolytic capacitor depends on external loads, conducted interferences, and the reverse conducting current IOut1,2,3. • Recommended value for capacitors at VCC: – Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. • To reduce thermal resistance, place cooling areas on the PCB as close as possible to the GND pins and to the die pad. 14 ATA6831 4908E–AUTO–06/07 ATA6831 11. Ordering Information Extended Type Number Package Remarks ATA6831-PIQW QFN18, 4 mm × 4 mm Taped and reeled, Pb-free ATA6831-PIPW QFN18, 4 mm × 4 mm Taped and reeled, Pb-free ATA6831-PISW QFN18, 4 mm × 4 mm Tubes, Pb-free 12. Package Information Package: VQFN_4 x 4_18L Exposed pad 2.7 x 3.175 Dimensions in mm Bottom 2.5 Not indicated tolerances ±0.05 Z 0.5 nom. Top 13 18 4 7 0.175 6 0.2 1 2.5 3.175±0.15 Pin 1 identification 1 18 12 6 2.7±0.15 0.9±0.1 Drawing-No.: 6.543-5133.01-4 Issue: 1; 26.04.07 0.23±0.07 0.4±0.1 Z 10:1 technical drawings according to DIN specifications 15 4908E–AUTO–06/07 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 16 Revision No. History 4908E-AUTO-06/07 • • • • • • • Put datasheet into the newest template Package drawing changed Block diagram changed Pin description table changed El. Char. table: rows 1.6, 4.12, 4.13 and 4.21 changed El. Char. table row 4.14 deleted Application circuit drawing changed 4908D-AUTO-09/06 • • • • • • • • • Features on page 1 changed Figure 1-1 “Block Diagram” on page 2 changed Section 2 “Pin Configuration” on pages 2 to 3 changed Section 4 “Absolute Maximum Ratings” on page 8 changed Section 8 “Electrical Characteristics” on pages 9 to 11 changed Section 9 “Serial Interface Timing” on page 12 changed Figure 10-1 “Application Circuit” on page 14 changed Section 11 “Ordering Information” on page 15 changed Section 12 “Package Information” on page 15 changed 4908C-AUTO-08/06 • • • • • • • • • • • • • Title on page 1 changed Features on page 1 changed Figure 1-1 “Block Diagram” on page 1 changed Figure 2-1 “Pinning” on page 3 changed Table 2-1 “Pin Description” on page 3 changed Table 3-2 “Output Data Protocol” on page 5 changed Section 3.7 “PWM Mode” on page 7 added Section 4 “Absolute Maximum Ratings” on page 8 changed Section 8 “Electrical Characteristics” on pages 9 to 12 changed Figure 10-1 “Application Circuit” on page 14 changed Section 10.1 “Application Notes” on page 14 changed Section 11 “Ordering Information” on page 15 changed Section 12 “Package Information” on page 15 changed ATA6831 4908E–AUTO–06/07 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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