Features • • • • • • • • • • Single Supply for Read and Write: 2.7V to 5.5V Fast Read Access Time – 70 ns (VCC = 2.7V to 3.6V); 55 ns (VCC = 4.5V to 5.5V) Internal Program Control and Timer Flexible Sector Architecture – One 16K Bytes Boot Sector with Programming Lockout – Two 8K Bytes Parameter Sectors – Eight Main Memory Sectors (One 32K Bytes, Seven 64K Bytes) Fast Erase Cycle Time – 8 Seconds Byte-by-Byte Programming – 10 µs/Byte Typical Hardware Data Protection DATA Polling or Toggle Bit for End of Program Detection Low Power Dissipation – 20 mA Active Current – 25 µA CMOS Standby Current for VCC = 2.7V to 3.6V – 30 µA CMOS Standby Current for VCC = 4.5V to 5.5V Minimum 100,000 Write Cycles 4-megabit (512K x 8) Flash Memory AT49BV040B 1. Description The AT49BV040B is a 2.7V to 5.5V in-system reprogrammable Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers an access time of 70 ns (VCC = 2.7V to 3.6V) and an access time of 55 ns (VCC = 4.5V to 5.5V). The power dissipation over the industrial temperature range with VCC = 2.7V to 3.6V is 72 mW and is 110 mW with VCC = 4.5V to 5.5V. When the device is deselected, the CMOS standby current is less than 30 µA. To allow for simple in-system reprogrammability, the AT49BV040B does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV040B is performed by erasing a sector of data and then programming on a byte by byte basis. The byte programming time is a fast 10 µs. The end of a program or erase cycle can be optionally detected by the DATA polling or toggle bit feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 100,000 cycles. The device is erased by executing a chip erase or a sector erase command sequence; the device internally controls the erase operations. The memory array of the AT49BV040B is organized into two 8K byte parameter sectors, eight main memory sectors, and one boot sector. The device has the capability to protect the data in the boot sector; this feature is enabled by a command sequence. The 16K-byte boot sector includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. 3499B–FLASH–4/06 2. Pin Configurations Function A0 - A18 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs 32-lead PLCC Top View 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 A12 A15 A16 A18 VCC WE A17 2.1 Pin Name 2.2 32-lead VSOP or 32-lead TSOP Top View – Type 1 A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 3. Block Diagram DATA INPUTS/OUTPUTS I/O7 - I/O0 VCC GND OE WE CE ADDRESS INPUTS 8 CONTROL LOGIC INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y DECODER Y-GATING X DECODER MAIN MEMORY SECTOR 8 (64K BYTES) MAIN MEMORY SECTOR 7 (64K BYTES) MAIN MEMORY SECTOR 6 (64K BYTES) MAIN MEMORY SECTOR 5 (64K BYTES) MAIN MEMORY SECTOR 4 (64K BYTES) MAIN MEMORY SECTOR 3 (64K BYTES) MAIN MEMORY SECTOR 2 (64K BYTES) MAIN MEMORY SECTOR 1 (32K BYTES) PARAMETER SECTOR 2 (8K BYTES) PARAMETER SECTOR 1 (8K BYTES) BOOT SECTOR (16K BYTES) 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 08000 07FFF 06000 05FFF 04000 03FFF 00000 4. Device Operation 4.1 Read The AT49BV040B is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. 4.2 Command Sequences When the device is first powered on, it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. 3 3499B–FLASH–4/06 4.3 Erasure Before a byte can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. 4.3.1 Chip Erase If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Sector 1, Parameter Sector 2, Main Memory Sectors 1 - 8, but not the boot sector. If the Boot Sector Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. 4.3.2 Sector Erase As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter sectors and eight main memory sectors. The 8K-byte parameter sectors and the eight main memory sectors can be independently erased and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. 4.4 Byte Programming Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4-bus cycle operation (see “Command Definition Table” on page 7). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling or toggle bit feature may also be used to indicate the end of a program cycle. 4.5 Boot Sector Programming Lockout The device has one designated sector that has a programming lockout feature. This feature prevents programming of data in the designated sector once the feature has been enabled. The size of the sector is 16K bytes. This sector, referred to as the boot sector, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot sector’s usage as a write protected region is optional to the user. The address range of the boot sector is 00000 to 03FFF. Once the feature is enabled, the data in the boot sector can no longer be erased or programmed. Data in the main memory and parameter sectors can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. See “Command Definition Table” on page 7. 4 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 4.5.1 4.6 Boot Sector Lockout Detection A software method is available to determine if programming of the boot sector is locked out. When the device is in the software product identification mode (see Software Product Identification Entry/Exit on page 15) a read from address location 00002H will show if programming the boot sector is locked out. If the data on I/O0 is low, the boot sector can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the sector cannot be programmed. The software product identification code should be used to return to standard operation. Product Identification The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. 4.7 Data Polling The AT49BV040B features DATA polling to indicate the end of a program or erase cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the erase operation is completed, a “1” will be read from I/O7. The Data Polling status bit must be used in conjunction with the erase/program status bit as shown in the algorithm in Figure 4-1 on page 6. 4.8 Toggle Bit In addition to DATA polling, the AT49BV040B provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. The toggle bit status bit should be used in conjunction with the erase/program status bit shown in the algorithm in Figure 4-2 on page 6. 4.9 Erase/Program Status Bit The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to verify that an erase or a byte program operation has been successfully performed. If a program (Sector Erase) command is issued to the boot sector and the boot sector programming lockout feature is enabled, the boot sector will not be programmed (erased), and the device will go into the read mode. Once the erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or program operation is still in progress. 4.10 Hardware Data Protection Hardware features protect against inadvertent programs to the AT49BV040B in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 5 3499B–FLASH–4/06 Figure 4-1. Data Polling Algorithm Figure 4-2. START Toggle Bit Algorithm START Read I/O7 - I/O0 Read I/O7 - I/O0 Addr = VA Read I/O7 - I/O0 I/O7 = Data? NO YES NO Toggle Bit = Toggle? I/O5 = 1? YES NO NO I/O5 = 1? YES Read I/O7 - I/O0 Addr = VA YES Read I/O7 - I/O0 Twice YES I/O7 = Data? Toggle Bit = Toggle? NO Program/Erase Operation Not Successful, Write Product ID Exit Command Notes: Program/Erase Operation Successful, Device in Read Mode 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. NO YES Program/Erase Operation Not Successful, Write Product ID Exit Command Note: Program/Erase Operation Successful, Device in Read Mode 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. 2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. 6 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 5. Command Definition Table Command Sequence 1st Bus Cycle Bus Cycles Addr Data Read 1 Addr DOUT Chip Erase 6 555 AA 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data AAA(2) 55 555 80 555 AA AAA 55 555 10 Sector Erase 6 555 AA AAA 55 555 80 555 AA Byte Program 4 555 AA AAA 55 555 A0 Addr DIN Boot Sector Lockout(3) 6 555 AA AAA 55 555 80 555 AA Product ID Entry 3 555 AA AAA 55 555 90 Product ID Exit (4) 3 555 AA AAA 55 555 F0 Product ID Exit (4) 1 XXX F0 Notes: 5th Bus Cycle (5) AAA 55 SA AAA 55 555 30 40 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows: A11 - A0 (Hex); A11 - A18 (don’t care). 2. Since A11 is don’t care, AAA can be replaced with 2AA. 3. The 16K byte boot sector has the address range 00000H to 03FFFH. 4. Either one of the Product ID Exit commands can be used. 5. SA = sector addresses: SA = 00000 to 03FFF for BOOT SECTOR SA = 04000 to 05FFF for PARAMETER SECTOR 1 SA = 06000 to 07FFF for PARAMETER SECTOR 2 SA = 08000 to FFFF for MAIN MEMORY ARRAY SECTOR 1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY SECTOR 2 SA = 20000 to 2FFFF for MAIN MEMORY ARRAY SECTOR 3 SA = 30000 to 3FFFF for MAIN MEMORY ARRAY SECTOR 4 SA = 40000 to 4FFFF for MAIN MEMORY ARRAY SECTOR 5 SA = 50000 to 5FFFF for MAIN MEMORY ARRAY SECTOR 6 SA = 60000 to 6FFFF for MAIN MEMORY ARRAY SECTOR 7 SA = 70000 to 7FFFF for MAIN MEMORY ARRAY SECTOR 8 6. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on A9 with Respect to Ground ...................................-0.6V to +10.0V 7 3499B–FLASH–4/06 7. Sector Address Table Sector Sector Size Sector Address Range Boot Sector 16K Bytes 00000 - 03FFF Parameter Sector 1 8K Bytes 04000 - 05FFF Parameter Sector 2 8K Bytes 06000 - 07FFF Main Memory Sector 1 32K Bytes 08000 - 0FFFF Main Memory Sector 2 64K Bytes 10000 - 1FFFF Main Memory Sector 3 64K Bytes 20000 - 2FFFF Main Memory Sector 4 64K Bytes 30000 - 3FFFF Main Memory Sector 5 64K Bytes 40000 - 4FFFF Main Memory Sector 6 64K Bytes 50000 - 5FFFF Main Memory Sector 7 64K Bytes 60000 - 6FFFF Main Memory Sector 8 64K Bytes 70000 - 7FFFF 8 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 8. DC and AC Operating Range AT49BV040B Operating Temperature (Case) Ind. -40°C - 85°C VCC Power Supply 2.7V - 3.6V or 4.5V to 5.5V 9. Operating Modes Mode Read Program/Erase (2) Standby/Write Inhibit CE OE WE Ai I/O VIL VIL VIH Ai DOUT VIL VIH VIL Ai DIN X X High Z (1) VIH X Program Inhibit X X VIH Program Inhibit X VIL X Output Disable X VIH X High Z Product Identification Hardware VIL VIL VIH A1 - A18 = VIL, A9 = VH,(3), A0 = VIL Manufacturer Code(4) A1 - A18 = VIL, A9 = VH,(3), A0 = VIH Device Code(4) Software(5) Notes: A0 = VIL, A1 - A18 = VIL Manufacturer Code(4) A0 = VIH, A1 - A18 = VIL Device Code(4) 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 9.5V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code: 13H. Additional Device Code: 10H is read from address 0003H. 5. See details under Software Product Identification Entry/Exit on page 15. 10. DC Characteristics VCC = 2.7V to 3.6V Min Typ VCC = 4.5V to 5.5V Max Max Units 1 1 µA 1 1 µA 25 30 µA 15 20 mA 0.1 VCC V Symbol Parameter Condition ILI Input Load Current VIN = 0V to VCC ILO Output Leakage Current VI/O = 0V to VCC ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 15 25 ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 15 20 VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 2.1 mA VOH Output High Voltage IOH = -400 µA Note: Min 0.1 VCC 0.7 VCC 0.7 VCC 0.45 2.4 Typ V 0.45 2.4 V V 1. In the erase mode, ICC is 15 mA. 9 3499B–FLASH–4/06 11. AC Read Characteristics 2.7V to 3.6V Symbol Parameter tACC Min 4.5V to 5.5V Max Min Max Units Address to Output Delay 70 55 ns (1) CE to Output Delay 70 55 ns (2) OE to Output Delay 0 35 0 15 ns tDF(3)(4) CE or OE to Output Float 0 25 0 25 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tCE tOE 0 ns 12. AC Read Waveforms (1)(2)(3)(4) ADDRESS ADDRESS VALID CE OE tCE tOE t DF tACC OUTPUT Notes: HIGH Z tOH OUTPUT VALID 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 10 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 13. Input Test Waveform and Measurement Level 0.7 x VCC AC DRIVING LEVELS AC MEASUREMENT LEVEL VCC/2 0.1 x VCC tR, tF < 5 ns 14. Output Load Test VCC 1.8K OUTPUT PIN 1.3K 30 pF 15. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 1. This parameter is characterized and is not 100% tested. 11 3499B–FLASH–4/06 16. AC Byte Load Characteristics 2.7V to 3.6V Min 4.5V to 5.5V Symbol Parameter Max Min Max Units tAS, tOES Address, OE Set-up Time 0 0 ns tAH Address Hold Time 20 20 ns tCS Chip Select Set-up Time 0 0 ns tCH Chip Select Hold Time 0 0 ns tWP Write Pulse Width (WE or CE) 30 20 ns tDS Data Set-up Time 20 20 ns tDH, tOEH Data, OE Hold Time 0 0 ns tWPH Write Pulse Width High 20 20 ns 17. AC Byte Load Waveforms 17.1 WE Controlled OE tOES tOEH ADDRESS CE WE tAS tAH tCH tCS tWPH tWP tDH tDS DATA IN 17.2 CE Controlled OE tOES tOEH ADDRESS tAS tAH tCH WE tCS CE tWPH tWP tDS tDH DATA IN 12 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 18. Program Cycle Characteristics 2.7V to 3.6V and 4.5V to 5.5V Symbol Parameter Min tBP Byte Programming Time tAS Address Set-up Time 0 ns tAH Address Hold Time 20 ns tDS Data Set-up Time 20 ns tDH Data Hold Time 0 ns tWP Write Pulse Width tWPH Write Pulse Width High tEC Chip Erase Cycle Time tSEC Main Sector Erase Cycle Time Note: 30 Typ Max Units 10 120 µs (1) ns 20 ns 8 seconds 900 ms 1. 20 ns for VCC = 4.5V to 5.5V. 19. Program Cycle Waveforms A0 - A18 20. Sector or Chip Erase Cycle Waveforms OE (1) CE tWP tWPH WE tAS A0 - A18 tAH tDH 555 555 AAA 555 Note 2 AAA tEC tDS DATA AA BYTE 0 Notes: 55 BYTE 1 80 BYTE 2 AA BYTE 3 55 BYTE 4 Note 3 BYTE 5 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase the address depends on what sector is to be erased. (See note 5 under “Command Definition Table” on page 7.) 3. For chip erase, the data should be 10H. For sector erase, the data should be 30H. 13 3499B–FLASH–4/06 21. Data Polling Characteristics Symbol Parameter Min tDH Data Hold Time tOEH OE Hold Time Typ Max Units 10 ns 10 ns (2) tOE OE to Output Delay tOEHP OE High Pulse 50 ns tWR Write Recovery Time 0 ns Notes: ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 22. Data Polling Waveforms WE CE tOEH tOEHP OE tDH tOE I/O7 An A0-A18 tWR HIGH Z An An An An 23. Toggle Bit Characteristics Symbol Parameter Min tDH Data Hold Time tOEH OE Hold Time Typ Max Units 10 ns 10 ns (2) tOE OE to Output Delay tOEHP OE High Pulse 50 ns tWR Write Recovery Time 0 ns Notes: ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 24. Toggle Bit Waveforms(1)(2)(3) WE CE tOEH tOEHP OE tDH tOE I/O6 Notes: HIGH Z tWR 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 14 AT49BV040B 3499B–FLASH–4/06 25. Software Product Identification Entry(1) 27. Boot Block Lockout Feature Enable Algorithm(1) LOAD DATA AA TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA 90 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA 55 TO ADDRESS AAA 26. Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 555 OR LOAD DATA 55 TO ADDRESS AAA LOAD DATA 40 TO ADDRESS 555 LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) PAUSE 1 second(2) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A11 - A0 (Hex). 2. Boot block lockout feature enabled. LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE(4) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A11 - A0 (Hex). 2. A1 - A18 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. Additional Device Code is read for address 0003H 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 13H. Additional Device Code: 10H. 15 AT49BV040B 3499B–FLASH–4/06 28. Ordering Information 28.1 Green Package (Pb/Halide-free) ICC (mA) Active 20 Ordering Code Package AT49BV040B-JU AT49BV040B-TU AT49BV040B-VU 32J 32T 32V Operation Range Industrial (-40° to 85° C) Package Type 32J 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC) 32T 32-lead, Thin Small Outline Package (TSOP) 32V 32-lead, Thin Small Outline Package (VSOP) 16 AT49BV040B 3499B–FLASH–4/06 AT49BV040B 29. Packaging Information 29.1 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) D2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 32J B 17 3499B–FLASH–4/06 29.2 32T – TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e NOTE 0.50 BASIC 10/18/01 R 18 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 32T B AT49BV040B 3499B–FLASH–4/06 AT49BV040B 29.3 32V – VSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 13.80 14.00 14.20 D1 12.30 12.40 12.50 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e NOTE 0.50 BASIC 10/18/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. REV. 32V B 19 3499B–FLASH–4/06 30. Revision History Revision No. History Revision A – Sept. 2005 • Initial Release Revision B – April 2006 • • • Combined the 3V and 5V part into one datasheet (BV). Removed the speed of the part form the ordering information table. Changed the address hold time to 20 ns. 20 AT49BV040B 3499B–FLASH–4/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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