CY62138EV30 MoBL® 2-Mbit (256 K × 8) Static RAM 2-Mbit (256 K × 8) Static RAM Features Functional Description ■ Very high speed: 45 ns ❐ Wide voltage range: 2.20 V to 3.60 V The CY62138EV30 is a high performance CMOS static RAM organized as 256K words by eight bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH). ■ Pin compatible with CY62138CV30 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 36-ball ball grid array (BGA) package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). For a complete list of related documentation, click here. Logic Block Diagram I/O0 Data in Drivers I/O1 256K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A A6 A87 A A109 A11 I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A12 A13 A14 A15 A16 A17 WE OE Cypress Semiconductor Corporation Document Number: 38-05577 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 20, 2015 CY62138EV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05577 Rev. *H Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY62138EV30 MoBL® Pin Configuration Figure 1. 36-ball FBGA pinout (Top View) [1] Top View A0 A1 NC A3 A6 A8 A I/O4 A2 WE A4 A7 I/O0 B NC A5 I/O1 C VSS Vcc D VCC Vss E I/O2 F I/O5 I/O6 NC A17 I/O7 OE CE A16 A15 I/O3 G A9 A10 A11 A12 A13 A14 H Product Portfolio Power Dissipation VCC Range (V) Product CY62138EV30LL Operating ICC (mA) Speed (ns) Min Typ [2] Max 2.2 3.0 3.6 45 f = 1 MHz Standby ISB2 (A) f = fmax Typ [2] Max Typ [2] Max Typ [2] Max 2 2.5 15 20 1 7 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document Number: 38-05577 Rev. *H Page 3 of 17 CY62138EV30 MoBL® DC input voltage [3, 4] ................. –0.3 V to VCC(MAX) + 0.3 V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ..................................... 55 °C to +125 °C Supply voltage to ground potential ...................... –0.3 V to VCC(MAX) + 0.3 V DC voltage applied to outputs in High Z state [3, 4] ..................... –0.3 V to VCC(MAX) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Product CY62138EV30LL Range Ambient Temperature VCC[5] Industrial –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter Description Output HIGH voltage VOH Output LOW voltage VOL Input HIGH voltage VIH Input LOW voltage VIL Test Conditions CY62138EV30-45 Min Typ [6] Max Unit IOH = –0.1 mA VCC = 2.20 V 2.0 – – V IOH = –1.0 mA VCC = 2.70 V 2.4 – – V IOL = 0.1 mA VCC = 2.20 V – – 0.4 V IOL = 2.1 mA VCC = 2.70 V – – 0.4 V VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V VCC = 2.2 V to 2.7 V –0.3 – 0.6 V VCC= 2.7 V to 3.6 V –0.3 – 0.8 V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 A ICC VCC Operating supply current f = fmax = 1/tRC – 15 20 mA – 2 2.5 mA – 1 7 A – 1 7 A f = 1 MHz ISB1[7] Automatic CE power down current – CMOS inputs VCC = VCCmax IOUT = 0 mA CMOS levels CE > VCC –0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (Address and data only), f = 0 (OE, and WE), VCC = 3.60 V ISB2 [7] Automatic CE power down current – CMOS inputs CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V Notes 3. VIL(min.) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min.) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. 7. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating. Document Number: 38-05577 Rev. *H Page 4 of 17 CY62138EV30 MoBL® Capacitance Parameter [8] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 10 pF 10 pF Test Conditions 36-ball BGA Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 72 C/W 8.86 C/W TA = 25 °C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC 30 pF INCLUDING JIG AND SCOPE R2 GND 10% 90% 90% 10% Fall time: 1 V/ns Rise Time: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.50 V 3.0 V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05577 Rev. *H Page 5 of 17 CY62138EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for data retention [10] VCC = 1 V, CE > VCC 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Data retention current Min Typ [9] Max Unit 1 – – V – 0.8 3 A tCDR[11] Chip deselect to data retention time 0 – – ns tR[12] Operation recovery time 45 – – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC (min.) tCDR VDR > 1.0 V VCC (min.) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) 100 s. Document Number: 38-05577 Rev. *H Page 6 of 17 CY62138EV30 MoBL® Switching Characteristics Over the Operating Range Parameter [13, 14] Description 45 ns Unit Min Max 45 – ns Read Cycle tRC Read cycle time tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 45 ns tDOE OE LOW to data valid – 22 ns [15] 5 – ns – 18 ns 10 – ns – 18 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z [15, 16] tLZCE CE LOW to Low Z [15] [15, 16] tHZCE CE HIGH to High Z tPU CE LOW to power-up 0 – ns tPD CE HIGH to power-up – 45 ns Write Cycle [17, 18] tWC Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns tHZWE tLZWE WE LOW to High Z [15, 16] WE HIGH to Low Z [15] Notes 13. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Notes is no longer applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production. 14. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 17. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 18. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05577 Rev. *H Page 7 of 17 CY62138EV30 MoBL® Switching Waveforms Figure 4. Read Cycle No. 1: Address Transition Controlled [19, 20] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [21, 22] ADDRESS tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 19. Device is continuously selected. OE, CE = VIL. 20. WE is HIGH for read cycle. 21. WE is HIGH for read cycle. 22. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05577 Rev. *H Page 8 of 17 CY62138EV30 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1: WE Controlled [23, 24] tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 25 tHD DATAIN VALID tHZOE Figure 7. Write Cycle No. 2: CE Controlled [23, 24] tWC ADDRESS tSCE CE tHA tSA tAW tPWE WE OE tSD DATA I/O tHD DATAIN VALID Notes 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 38-05577 Rev. *H Page 9 of 17 CY62138EV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3: WE Controlled, OE LOW [26, 27] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O tHD DATAIN VALID NOTE 28 tHZWE tLZWE Notes 26. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 27. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. 28. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 38-05577 Rev. *H Page 10 of 17 CY62138EV30 MoBL® Truth Table CE H WE OE [29] Inputs/Outputs Mode Power X X High Z Deselect/power-down Standby (ISB) L H L Data out (I/O0–I/O7) Read Active (ICC) L H H High Z Output disabled Active (ICC) L L X Data in (I/O0–I/O7) Write Active (ICC) Note 29. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating. Document Number: 38-05577 Rev. *H Page 11 of 17 CY62138EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62138EV30LL-45BVXI Package Diagram Package Type 51-85149 36-ball VFBGA (6 mm × 8 mm × 1 mm) (Pb-free) Operating Range Industrial Ordering Code Definitions CY 621 3 8 E V30 LL - 45 BV X I Temperature Grade: I = Industrial Pb-free Package Type: BV = 36-ball VFBGA Speed Grade: 45 ns Low Power Voltage Range: 3 V typical Process Technology: 90 nm Bus width = × 8 Density = 2-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05577 Rev. *H Page 12 of 17 CY62138EV30 MoBL® Package Diagram Figure 9. 36-ball VFBGA (6 × 8 × 1.0 mm) BV36A Package Outline, 51-85149 51-85149 *F Document Number: 38-05577 Rev. *H Page 13 of 17 CY62138EV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BGA ball gird array CE chip enable °C degree Celsius CMOS complementary metal oxide semiconductor MHz megahertz FBGA fine-pitch ball gird array A microampere I/O input/output s microsecond OE output enable mA milliampere SRAM static random access memory mm millimeter VFBGA very fine ball gird array ns nanosecond WE write enable pF picofarad ohm V volt W watt Document Number: 38-05577 Rev. *H Symbol Unit of Measure Page 14 of 17 CY62138EV30 MoBL® Document History Page Document Title: CY62138EV30 MoBL®, 2-Mbit (256 K × 8) Static RAM Document Number: 38-05577 Rev. ECN No. Orig. of Change Submission Date ** 237432 AJU See ECN New data sheet. *A 427817 NXR See ECN Removed 35 ns Speed Bin Removed “L” version Removed 32-pin TSOPII package from product Offering. Changed ball C3 from DNU to NC. Removed the redundant footnote on DNU. Moved Product Portfolio from Page # 3 to Page #2. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from 2.5 A to 7 A. Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed the AC test load capacitance from 50pF to 30pF on Page# 4 Changed VDR from 1.5V to 1V on Page# 4. Changed ICCDR from 1 A to 3 A in the Data Retention Characteristics table on Page # 4. Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tOHA, tLZCE, tLZWE from 6 ns to 10 ns Changed tHZOE, tHZCE, tHZWE from 15 ns to 18 ns Changed tLZOE from 3 ns to 5 ns Changed tSCE and tAW from 40 ns to 35 ns Changed tSD from 20 ns to 25 ns Changed tPWE from 25 ns to 35 ns Updated the Ordering Information table and replaced Package Name column with Package Diagram. *B 2604685 VKN / PYRS 11/12/08 Updated Electrical Characteristics: Added Note 7 and referred the same note in ISB2 parameter. Updated Data Retention Characteristics: Added Note 10 and referred the same note in ICCDR parameter. *C 3143896 RAME 01/17/2011 Converted all tablenotes to Footnote. Added Ordering Code Definitions. Updated Package Diagram: spec 51-85149 – Changed revision from *C to *D. Added Acronyms and Units of Measure. Updated to new template. *D 3284728 AJU 06/16/2011 Updated Functional Description: Removed the Note “For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com website.” and its reference. Updated to new template. *E 3806123 TAVA 11/08/2012 Updated Data Retention Waveform (Updated Figure 3 (Changed “VDR > 1.5 V” to “VDR > 1.0 V”)). Updated Package Diagram (spec 51-85149 (Changed revision from *D to *E)). *F 4099016 VINI 08/19/2013 Updated Switching Characteristics: Added Note 13 and referred the same note in “Parameter” column. Updated to new template. Completing Sunset Review. *G 4576475 VINI 11/19/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Document Number: 38-05577 Rev. *H Description of Change Page 15 of 17 CY62138EV30 MoBL® Document History Page (continued) Document Title: CY62138EV30 MoBL®, 2-Mbit (256 K × 8) Static RAM Document Number: 38-05577 Rev. ECN No. Orig. of Change Submission Date *H 5022355 VINI 11/20/2015 Document Number: 38-05577 Rev. *H Description of Change Updated Document Title to read as “CY62138EV30 MoBL®, 2-Mbit (256 K × 8) Static RAM”. Updated Switching Characteristics: Added Note 18 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 27 and referred the same note in Figure 8. Updated Package Diagram: spec 51-85149 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. Page 16 of 17 CY62138EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05577 Rev. *H Revised November 20, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17