CY7C1061G/CY7C1061GE 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip enable (CE) input LOW. To access dual chip enable devices, assert both chip enable inputs – CE1 as LOW and CE2 as HIGH. ■ High speed ❐ tAA = 10 ns/15 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Low active and standby currents ❐ ICC = 90-mA typical at 100 MHz ❐ ISB2 = 20-mA typical ■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V ■ 1.0-V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages Functional Description CY7C1061G and CY7C1061GE are high-performance CMOS fast static RAM devices with embedded ECC[1]. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY7C1061GE device includes an ERR pin that signals a single-bit error-detection and correction event during a read cycle. To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A19) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH for a single chip enable device and CE1 HIGH / CE2 LOW for a dual chip enable device), or control signals are de-asserted (OE, BLE, BHE). On the CY7C1061GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High). See the Truth Table on page 16 for a complete description of read and write modes. The logic block diagrams are on page 2. The CY7C1061G and CY7C1061GE devices are available in 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages. For a complete list of related documentation, click here. Product Portfolio Current Consumption Product CY7C1061G18 CY7C1061G(E)30 CY7C1061G Features and Options (see “Pin Configurations” on page 4) Range Industrial Single or dual chip enables Optional ERR pins VCC Range (V) Speed Operating ICC, (mA) (ns) f = fmax 10/15 Standby, ISB2 (mA) Typ[2] Max Typ[2] Max 20 30 1.65 V–2.2 V 15 70 80 2.2 V–3.6 V 10 90 110 4.5 V–5.5 V 10 90 110 Address MSB A19 pin placement options compatible with Cypress and other vendors Notes 1. This device does not support automatic write-back on error detection. 2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 001-81540 Rev. *P • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 9, 2015 CY7C1061G/CY7C1061GE Logic Block Diagram – CY7C1061G Logic Block Diagram – CY7C1061GE Document Number: 001-81540 Rev. *P Page 2 of 24 CY7C1061G/CY7C1061GE Contents Pin Configurations ........................................................... 4 Maximum Ratings............................................................. 7 Operating Range............................................................... 7 DC Electrical Characteristics .......................................... 7 Capacitance ...................................................................... 8 Thermal Resistance.......................................................... 8 AC Test Loads and Waveforms....................................... 8 Data Retention Characteristics ....................................... 9 Data Retention Waveform................................................ 9 AC Switching Characteristics ....................................... 10 Switching Waveforms .................................................... 11 Truth Table ...................................................................... 16 ERR Output – CY7C1061GE .......................................... 16 Document Number: 001-81540 Rev. *P Ordering Information...................................................... Ordering Code Definitions ......................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 17 18 19 22 22 22 23 24 24 24 24 24 24 Page 3 of 24 CY7C1061G/CY7C1061GE Pin Configurations Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Dual Chip Enable without ERR, Address MSB A19 at Ball G2, Dual Chip Enable without ERR, Address MSB A19 at Ball H6, CY7C1061G[3] Package/Grade ID: BVJXI CY7C1061G[3] Package/Grade ID: BVXI 1 2 3 4 5 6 A BLE OE A0 A1 A2 CE2 A I/O0 B I/O8 BHE A3 A4 CE1 I/O0 B I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 C VCC D VSS I/O11 A17 A7 VCC D I/O4 VSS E VCC I/O12 NC A16 I/O4 VSS E A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F A12 A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 G A9 A10 A11 NC H A18 A8 A9 A10 A11 A19 H 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 I/O8 BHE A3 A4 CE1 I/O9 I/O10 A5 A6 I/O1 VSS I/O11 A17 A7 VCC I/O12 NC A16 I/O14 I/O13 A14 I/O15 A19 A18 A8 I/O3 I/O3 Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable without ERR, Address MSB A19 at Ball G2, CY7C1061G[3] Package/Grade ID: BV1XI Note 3. NC pins are not connected internally to the die. Document Number: 001-81540 Rev. *P Page 4 of 24 CY7C1061G/CY7C1061GE Pin Configurations (continued) Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) Dual Chip Enable with ERR, Address MSB A19 at Ball G2 CY7C1061GE[4, 5] Package/Grade ID: BVJXI Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable with ERR, Address MSB A19 at Ball G2 CY7C1061GE[4, 5] Package/Grade ID: BV1XI 1 2 3 4 5 6 A BLE OE A0 A1 A2 CE2 A I/O0 B I/O8 BHE A3 A4 CE1 I/O0 B I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 C VCC D VSS I/O11 A17 A7 VCC D I/O4 VSS E VCC ERR A16 I/O4 VSS E A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F A12 A13 WE I/O7 G I/O15 A19 A12 A13 WE I/O7 G A9 A10 A11 NC H A18 A8 A9 A10 A11 NC H 1 2 3 4 5 BLE OE A0 A1 A2 ERR I/O8 BHE A3 A4 CE I/O9 I/O10 A5 A6 I/O1 VSS I/O11 A17 A7 VCC I/O12 NC A16 I/O14 I/O13 A14 I/O15 A19 A18 A8 I/O3 6 I/O12 I/O3 Figure 6. 48-ball VFBGA (6 × 8 × 1.0 mm) Dual Chip Enable with ERR, Address MSB A19 at Ball H6 CY7C1061GE[4, 5] Package/Grade ID: BVXI 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC ERR A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 H Notes 4. NC pins are not connected internally to the die. 5. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 001-81540 Rev. *P Page 5 of 24 CY7C1061G/CY7C1061GE Pin Configurations (continued) Figure 8. 48-pin TSOP I (12 × 18.4 × 1 mm) Single Chip Enable without ERR CY7C1061G[6] Package/Grade ID: ZXI Figure 7. 48-pin TSOP I (12 × 18.4 × 1 mm) Single Chip Enable with ERR CY7C1061GE[6, 7] Package/Grade ID: ZXI A4 A3 A2 A1 A0 ERR CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 9. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Dual Chip Enable without ERR CY7C1061G[6] Package/Grade ID: ZSXI I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 A5 A6 A7 A8 OE BHE BLE I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A6 A7 A8 OE BHE BLE I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 Figure 10. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Dual Chip Enable with ERR CY7C1061GE[6, 7] Package/Grade ID: ZSXI I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 ERR OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 Notes 6. NC pins are not connected internally to the die. 7. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 001-81540 Rev. *P Page 6 of 24 CY7C1061G/CY7C1061GE DC input voltage[8] .............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Operating Range Supply voltage on VCC relative to GND ................................... –0.5 V to VCC + 0.5 V DC voltage applied to outputs in High Z State [8] ................................ –0.5 V to VCC + 0.5 V Grade Ambient Temperature VCC Industrial –40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the operating range of –40 C to 85 C Parameter VOH Description Output HIGH 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA voltage 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA VIH [8] VIL[8] Input LOW voltage Typ [10] Max 1.4 – – 2.0 – – VCC = Min, IOH = –4.0 mA 2.2 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – VCC = Min, IOH = –0.1 mA VCC – 0.4 Output LOW 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA voltage 2.2 V to 2.7 V VCC = Min, IOL = 2 mA Input HIGH voltage 10 ns / 15 ns Min 2.7 V to 3.6 V 4.5 V to 5.5 V VOL Test Conditions [11] Unit V – – – – 0.2 – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4 1.65 V to 2.2 V 1.4 – VCC + 0.2 2.2 V to 2.7 V 2.0 – VCC + 0.3 2.7 V to 3.6 V 2.0 – VCC + 0.3 4.5 V to 5.5 V 2.2 – VCC + 0.5 1.65 V to 2.2 V –0.2 – 0.4 2.2 V to 2.7 V –0.3 – 0.6 2.7 V to 3.6 V –0.3 – 0.8 4.5 V to 5.5 V –0.5 – 0.8 V V V IIX Input leakage current GND < VIN < VCC –1.0 – +1.0 A IOZ Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 A ICC Operating supply current VCC = Max, IOUT = 0 mA, CMOS levels f = 100 MHz – 90.0 110.0 mA f = 66.7 MHz – 70.0 80.0 ISB1 Automatic CE power down current – TTL inputs Max VCC, CE > VIH [9], VIN > VIH or VIN < VIL, f = fMAX – – 40.0 mA ISB2 Automatic CE power down current – CMOS inputs Max VCC, CE > VCC – 0.2 V[9], VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 20.0 30.0 mA Notes 8. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns. 9. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 10. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. 11. This parameter is guaranteed by design and is not tested Document Number: 001-81540 Rev. *P Page 7 of 24 CY7C1061G/CY7C1061GE Capacitance Parameter [12] Description CIN Input capacitance COUT I/O capacitance Test Conditions 54-pin TSOP II 48-ball VFBGA 48-pin TSOP I Unit TA = 25 C, f = 1 MHz, VCC = VCC(typ) 10 10 10 pF 10 10 10 pF Thermal Resistance Parameter [12] Description Test Conditions JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 54-pin TSOP II 48-ball VFBGA 48-pin TSOP I Unit Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 93.63 31.50 57.99 C/W 21.58 15.75 13.42 C/W AC Test Loads and Waveforms Figure 11. AC Test Loads and Waveforms[13] High-Z Characteristics: VCC 50 Output VTH Z0 = 50 Output 30 pF* R2 5 pF* * Including JIG and Scope (a) * Capacitive load consists of all components of the test environment R1 (b) All Input Pulses VHIGH GND 90% 90% 10% Rise Time: > 1 V/ns 10% Fall Time: > 1 V/ns (c) Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317 R2 1538 351 351 VTH 0.9 1.5 1.5 V VHIGH 1.8 3 3 V Notes 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value. Document Number: 001-81540 Rev. *P Page 8 of 24 CY7C1061G/CY7C1061GE Data Retention Characteristics Over the operating range of –40 C to 85 C Parameter VDR Description Conditions Min Max Unit 1.0 – V – 30.0 mA 0 – ns VCC > 2.2 V 10.0 – ns VCC < 2.2 V 15.0 – ns VCC for data retention [14] ICCDR Data retention current tCDR[15] Chip deselect to data retention time tR[15, 16] Operation recovery time VCC = VDR, CE > VCC – 0.2 V , VIN > VCC – 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 12. Data Retention Waveform [14] VCC VCC(min) tCDR DATA RETENTION MODE VDR = 1.0 V VCC(min) tR CE Notes 14. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 15. This parameter is guaranteed by design and is not tested 16. Full-device operation requires linear VCC ramp from VDR to VCC (min) > 100 s or stable at VCC (min) > 100 s. Document Number: 001-81540 Rev. *P Page 9 of 24 CY7C1061G/CY7C1061GE AC Switching Characteristics Over the operating range of –40 C to 85 C Parameter [17] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tPOWER VCC (stable) to the first access [18, 19] 100.0 – 100.0 – µs tRC Read cycle time 10.0 – 15.0 – ns tAA Address to data / ERR valid tOHA Data / ERR hold from address change tACE CE LOW to data / ERR valid tDOE OE LOW to data / ERR valid [20] [21, 22, 23] tLZOE OE LOW to low Z tHZOE OE HIGH to high Z [21, 22, 23] [20, 21, 22, 23] tLZCE CE LOW to low Z tHZCE CE HIGH to high Z [20, 21, 22, 23] [19, 20] tPU CE LOW to power-up tPD CE HIGH to power-down [19, 20] tDBE tLZBE tHZBE – 10.0 – 15.0 ns 3.0 – 3.0 – ns – 10.0 – 15.0 ns – 5.0 – 8.0 ns 0 – 1.0 – ns – 5.0 – 8.0 ns 3.0 – 3.0 – ns – 5.0 – 8.0 ns 0 – 0 – ns – 10.0 – 15.0 ns Byte enable to data valid – 5.0 – 8.0 ns Byte enable to low Z [21, 22] 0 – 1.0 – ns – 6.0 – 8.0 ns Byte disable to high Z [21, 22] Write Cycle [24, 25] tWC Write cycle time 10.0 – 15.0 – ns tSCE CE LOW to write end [20] 7.0 – 12.0 – ns tAW Address setup to write end 7.0 – 12.0 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7.0 – 12.0 – ns tSD Data setup to write end 5.0 – 8.0 – ns tHD Data hold from write end 0 – 0 – ns 3.0 – 3.0 – ns – 5.0 – 8.0 ns 7.0 – 12.0 – ns [21, 22, 23] tLZWE WE HIGH to low Z tHZWE WE LOW to high Z [21, 22, 23] tBW Byte Enable to write end Notes 17. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 11 on page 8, unless specified otherwise. 18. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed. 19. These parameters are guaranteed by design and are not tested. 20. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 21. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 11 on page 8. Hi-Z, Lo-Z transition is measured 200 mV from steady state voltage. 22. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 23. Tested initially and after any design or process changes that may affect these parameters. 24. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 25. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 001-81540 Rev. *P Page 10 of 24 CY7C1061G/CY7C1061GE Switching Waveforms Figure 13. Read Cycle No. 1 of CY7C1061G (Address Transition Controlled) [26, 27] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 14. Read Cycle No. 2 of CY7C1061GE (Address Transition Controlled) [26, 27] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 26. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL. 27. WE is HIGH for read cycle. Document Number: 001-81540 Rev. *P Page 11 of 24 CY7C1061G/CY7C1061GE Switching Waveforms (continued) Figure 15. Read Cycle No. 3 (OE Controlled) [28, 29, 30] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE HIGH IMPEDANCE DATAOUT VALID tLZCE VCC SUPPLY CURRENT tPU ICC ISB Notes 28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 29. WE is HIGH for read cycle. 30. Address valid prior to or coincident with CE LOW transition. Document Number: 001-81540 Rev. *P Page 12 of 24 CY7C1061G/CY7C1061GE Switching Waveforms (continued) Figure 16. Write Cycle No. 1 (CE Controlled) [31, 32, 33] tW C ADDRESS t SA tSCE CE tAW tHA tPW E WE tBW BHE/ BLE OE tHZOE DATA I/O t HD tSD Note 35 DATA IN VALID Figure 17. Write Cycle No. 2 (WE Controlled, OE LOW) [31, 32, 33, 34] tWC ADDRESS tSCE CE tBW BHE/ BLE tAW tSA tHA tPWE WE tHZWE DATA I/O Note 35 tSD tLZWE tHD DATAIN VALID Notes 31. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 32. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 33. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 34. The minimum write cycle pulse width should be equal to sum of tHZWE and tSD. 35. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-81540 Rev. *P Page 13 of 24 CY7C1061G/CY7C1061GE Switching Waveforms (continued) Figure 18. Write Cycle No. 3 (WE controlled)[36, 37, 38] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE tB W B H E /B L E OE tH Z O E D A T A I/O Note39 tH D tS D D A T A IN V A L ID Notes 36. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 37. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 38. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 39. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-81540 Rev. *P Page 14 of 24 CY7C1061G/CY7C1061GE Switching Waveforms (continued) Figure 19. Write Cycle No. 4 (BLE or BHE Controlled) [40, 41, 42] tWC ADDRESS tSCE CE tAW tSA tHA tBW BHE/ BLE tPWE WE tHZWE DATA I/O Note 43 tSD tHD tLZWE DATAIN VALID Notes 40. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 41. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 42. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 43. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-81540 Rev. *P Page 15 of 24 CY7C1061G/CY7C1061GE Truth Table CE [44] OE H [45] X WE BLE BHE [45] [45] [45] High-Z High-Z Power down Standby (ISB) X X X I/O0–I/O7 I/O8–I/O15 Mode Power L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out High-Z Read lower bits only Active (ICC) L L H H L High-Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in High-Z Write lower bits only Active (ICC) L X L H L High-Z Data in Write upper bits only Active (ICC) L H H X X High-Z High-Z Selected, outputs disabled Active (ICC) L X X H H High-Z High-Z Selected, outputs disabled Active (ICC) ERR Output – CY7C1061GE Output [46] 0 Mode Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. High-Z Device deselected or outputs disabled or Write operation Notes 44. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 45. The input voltage levels on these pins should be either at VIH or VIL. 46. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 001-81540 Rev. *P Page 16 of 24 CY7C1061G/CY7C1061GE Ordering Information Speed (ns) Voltage Range Ordering Code Package Package Type Diagram (all Pb-free) CY7C1061G-10BV1XI CY7C1061GE-10BV1XI CY7C1061G-10BVJXI CY7C1061GE-10BVJXI 4.5 V–5.5 V CY7C1061G-10BVXI CY7C1061GE-10BVXI CY7C1061G-10ZSXI CY7C1061GE-10ZSXI CY7C1061G-10ZXI CY7C1061GE-10ZXI 10 51-85150 48-ball VFBGA CY7C1061G30-10BVJXI 2.2 V–3.6 V 51-85150 48-ball VFBGA CY7C1061G30-10BVXI CY7C1061G30-10ZSXI CY7C1061GE30-10ZSXI CY7C1061G30-10ZXI CY7C1061GE30-10ZXI 15 1.65 V–2.2 V CY7C1061GE18-15BVXI CY7C1061G18-15BVXI CY7C1061GE18-15ZSXI CY7C1061G18-15ZSXI CY7C1061GE18-15ZXI CY7C1061G18-15ZXI Document Number: 001-81540 Rev. *P Dual Chip Enable Address MSB A19 at ball H6 Yes 51-85150 48-ball VFBGA No No No Yes No Yes No Single Chip Enable Address MSB A19 at ball G2 Yes Dual Chip Enable Address MSB A19 at ball G2 Yes 51-85183 48-pin TSOP I Single Chip Enable CY7C1061G18-15BV1XI CY7C1061G18-15BVJXI Yes 51-85160 54-pin TSOP II Dual Chip Enable CY7C1061GE18-15BV1XI CY7C1061GE18-15BVJXI Dual Chip Enable Address MSB A19 at ball G2 Dual Chip Enable Address MSB A19 at ball H6 CY7C1061GE30-10BVXI No Yes 51-85183 48-pin TSOP I Single Chip Enable CY7C1061G30-10BV1XI ERR Operating Pin/Ball Range Single Chip Enable Address MSB A19 at ball G2 51-85160 54-pin TSOP II Dual Chip Enable CY7C1061GE30-10BV1XI CY7C1061GE30-10BVJXI Key Features/ Differentiators No No Yes No Yes No Yes Single Chip Enable Address MSB A19 at ball G2 Yes Dual Chip Enable Address MSB A19 at ball G2 Yes Dual Chip Enable Address MSB A19 at ball H6 Yes 51-85160 54-pin TSOP II Dual Chip Enable 51-85183 48-pin TSOP I Single Chip Enable Industrial No No No Yes No Yes No Page 17 of 24 CY7C1061G/CY7C1061GE Ordering Code Definitions CY 7 C 1 06 1 G E XX - XX XXX I Temperature Range: I = Industrial Pb-free Package Type: XXX = ZX or ZSX or BVX ZX = 48-pin TSOP I; ZSX = 54-pin TSOP II; BVX = 48-ball VFBGA Speed: XX = 10 ns or 15 ns Voltage Range: 18 = 1.65 V–2.2 V; 30 = 2.2 V–3.6 V; no character = 4.5 V–5.5 V ERR output Single bit error indication Revision Code “G”: Process Technology – 65 nm Data width: 1 = × 16-bits Density: 06 = 16-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-81540 Rev. *P Page 18 of 24 CY7C1061G/CY7C1061GE Package Diagrams Figure 20. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline 51-85183 *D Document Number: 001-81540 Rev. *P Page 19 of 24 CY7C1061G/CY7C1061GE Package Diagrams (continued) Figure 21. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline 51-85160 *E Document Number: 001-81540 Rev. *P Page 20 of 24 CY7C1061G/CY7C1061GE Package Diagrams (continued) Figure 22. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline 51-85150 *H Document Number: 001-81540 Rev. *P Page 21 of 24 CY7C1061G/CY7C1061GE Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary metal oxide semiconductor A microampere I/O Input/output s microsecond OE Output Enable mA milliampere mm millimeter ns nanosecond ohm % percent pF picofarad V volt W watt SRAM Static random access memory TSOP Thin small outline package TTL Transistor-transistor logic VFBGA Very fine-pitch ball grid array WE Write Enable Document Number: 001-81540 Rev. *P Symbol Unit of Measure Page 22 of 24 CY7C1061G/CY7C1061GE Document History Page Document Title: CY7C1061G/CY7C1061GE, 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-81540 Rev. ECN No. Orig. of Change Submission Date *P 4791835 NILE 06/09/2015 Document Number: 001-81540 Rev. *P Description of Change Changed datasheet status to Final Page 23 of 24 CY7C1061G/CY7C1061GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-81540 Rev. *P Revised June 9, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 24 of 24